JP2001028443A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

(57) [Problem] To provide a field effect transistor having extremely low leakage current. Another object of the present invention is to provide a semiconductor memory device having excellent information retention characteristics. Further, the present invention provides a method for easily manufacturing a novel device, a field-effect transistor having extremely low leakage current, or a semiconductor memory device. SOLUTION: A structure in which a source and a drain electrode are formed by bonding a thin insulating film to a vertically arranged Schottky junction and a tunnel of the insulating film at the junction is controlled by a gate electrode. Further, the gate electrode is arranged on both sides of the vertical channel so that the electric field effect on the junction can be effectively exerted, so that the junction leakage in the off state can be extremely low.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device which can be integrated on a large scale, and a semiconductor memory device using the same. Further, the present invention relates to a method for manufacturing the semiconductor device or the semiconductor memory device.

[0002]

2. Description of the Related Art The main part of a ULSI transistor using a silicon substrate, which is a typical integrated semiconductor device at present, has a cross-sectional structure as shown in FIG. CMOS
The transistor used in (1) is configured using an insulated gate transistor in which a diffusion layer (200, 300) doped with a high concentration of impurities as a source and a drain is used as an electrode region in a semiconductor substrate 100. Note that reference numeral 500 is a gate electrode.

An insulated gate transistor, a typical example of a MOSFET, uses only a carrier of a channel to be controlled and a carrier of a conduction type opposite to a substrate to be a channel.
For this reason, the insulated gate transistor is called a unipolar device. In a unipolar device, it is fundamental in device operation that electrodes such as a source and a drain are electrically separated from the substrate 100. Normal,
The diffusion layer and the substrate have formed a PN junction by using different conduction types, and each electrode and the substrate have been electrically separated by a built-in barrier of the junction. However, as the distance between the source and the drain becomes shorter, good isolation cannot be achieved only with this barrier, and the problem of causing a leak to the substrate and a leak current between the source and the drain has become significant. It is considered that such a current leak occurs because the influence of the drain electric field extends to the source side. Therefore, in order to suppress the leakage, the depth of the impurity diffusion layers 200 and 300 is reduced (shallowed).
It is effective to reduce the facing area of the source and the drain. This depth is shown as Xj in FIG. However, when the depth of the diffusion layer is reduced, the resistance of the diffusion layer increases,
There is a problem that the current driving capability of the transistor is reduced.

[0004] Also, as a different approach,
It has been considered to surround the diffusion layer electrode with an insulating film layer and provide a barrier against leakage between the electrode and a channel (substrate). In addition, Japanese Patent Laid-Open Publication No.
The structure shown in 200001 is a structure in which a multilayer insulating film layer is interposed not only between the diffusion layer electrode and the channel but also in the channel portion. However, in the latter case, due to the manufacturing process, a kind of thin film transistor (TFT: Th) in which the channel portion is made of polycrystal instead of single crystal.
It can be regarded as a structure called “in Film Transistor”. In these structures, it is possible to suppress the leak without increasing the resistance of the diffusion layer, but it is necessary to flow a channel current through the insulating film, which causes a problem that the current driving force is reduced. come.

As a method of solving the increase in electrode resistance due to the shallow junction, it has been proposed to use a metal material for a source and a drain. Generally, the separation between the electrode and the substrate is made not by a PN junction but by a Schottky junction formed at a metal-semiconductor contact portion. Therefore, a Schottky barrier source / drain MOSFET (SB-MOSFET)
is called. These structures are described in, for example, Applied Physics, Letters, Vol. 65, pp. 618 to 620 (Appl. Phys. Lett. 65 (5), pp. 618-620, 19).
94) by Tucker et al. Also,
Actual prototypes include S, P, I, E, Conference, On, Microelectronic, Device, Technology, Two, July 1998, S, P, I, E, 3506, pp. 230-233 (P
art of the SPIE Conference on Microelectronic Devi
Wang et al. are reported in ce Technology II, SPIE vol. 3506, pp. 230-233). In these reports,
As an effect using the Schottky junction, it has become clear that leakage between the junctions can be effectively suppressed even in a short channel structure in which the distance between the source and the drain is reduced. However, since it is difficult to form a good junction as compared with a PN junction, leakage between the PN junction and the substrate increases, which negates the effect of reducing the leakage between the source and the drain or reduces the on-resistance of the junction. As a result, the effect of reducing the electrode resistance cannot be seen.

As a gain cell used in a semiconductor memory device, for example, a Shoji Shukuri using a p-type MOS for writing and an n-type MOS for reading is used.
IEDM 92, 1006-1008.

[0007]

The first object of the present application is to
An object of the present invention is to provide an insulated gate field effect transistor having extremely low leakage current. That is, the present invention suppresses a decrease in driving force caused by the above-described various measures that have been taken to reduce the leak current that has been increasing in order to shorten the channel.

A second object of the present invention is to provide a semiconductor memory device having good storage characteristics. Using the low insulated gate field effect transistor of the leakage current,
A three-terminal switching element with a small leakage current can be obtained. Therefore, this is particularly effective in forming a semiconductor memory element.

Still another object of the present invention is to provide a manufacturing method for providing the above-described semiconductor device or semiconductor memory device.

[0010]

First, in order to facilitate understanding of the present invention, the gist of the inventive concept of the present invention will be described. Further, various embodiments of the invention will be described in more detail in the section of the embodiments of the invention.

[0011] In the Schottky junction, an interface of different materials sandwiching the junction is formed, so that the junction leaks more than in the PN junction. When an SB-MOSFET is formed based on the conventional structure shown in FIG. 1, only the junction at the gate end is used for switching, and the bottom surface and the like are unnecessary for the switching operation. This bottom surface is the major source of leakage, as it will occupy most of the junction area. In order to suppress such unnecessary leaks, as shown schematically in FIG.
It is effective that the channel 101 is sandwiched from both sides by 0 and 510, unnecessary junction is eliminated, and the junction is made only in the channel direction. The specific structure of the present invention will be described in detail in the description of the embodiments based on a manufacturing method. In this structure, the junction is provided only at the gate end required for switching, and there is no occurrence of leakage due to unnecessary junction.

In order to further suppress leakage, a structure is employed in which an insulating layer serving as a barrier for preventing leakage is interposed between a metal and a semiconductor. This applies a structure in which the periphery of the diffusion layer electrode is surrounded by an insulating film.

FIG. 3 is a band structure diagram for explaining a conventional Shottky junction. FIG. 3 shows a junction region between the metal part 350 and the semiconductor part 110, the upper end of the valence band, the lower end of the conduction band, and the Fermi level Ef. FIG. 4 is a band structure diagram for explaining the bonding used in the present invention. In the structure of FIG. 4, an insulator layer 931 is provided in the structure of FIG.

That is, in the Schottky junction, as shown in the band diagram of FIG. 3, a leakage current is suppressed by a barrier Pm called a Schottky barrier. There, Figure 4
As can be seen, the barrier height Pi is larger than Pm.
By interposing an insulating film having a hole, carriers passing from the metal side to the semiconductor side can be reduced. Instead of the Schottky junction, the junction having the structure with the insulating layer interposed therebetween is formed by M
IS junction (MetalInsulation Junc
). This example is, for example, S
Physics of Semiconductor Devices, 2nd Edition, John Willie and Sons (Physics
of Semiconductor Devices, secondedition, JOHN WIL
EY & SONS), pp. 540-553.
Even if an insulating layer having a high barrier height Pi is sandwiched in this way,
Since the tunnel phenomenon can be promoted by making the thickness of the insulating layer extremely thin, the switching operation of the junction can be performed.

In general, carriers passing through the insulating film by the tunnel phenomenon depend on the barrier height, the film thickness, and the energy of the carriers. As the device structure, the barrier height between the metal material and the insulating film, the thickness of the insulating film, and the potential distribution in a non-equilibrium state can be controlled.

In the structure of the present invention, a device having a large channel length is formed without increasing the plane area by adopting a vertical channel arrangement. As a result, an increase in leakage current due to a short channel can be suppressed. Further, by arranging the gates on both sides, the electric field effect can be more effectively utilized. With this vertical structure, an asymmetric transistor, which has been difficult in the past, can be easily formed. Therefore, the barrier made of the insulating film can be formed only on one side, and a reduction in driving force can be suppressed.

By effectively drawing out these effects, it is possible to obtain a three-terminal transistor structure in which the leakage current can be suppressed to a very low level. Further, it will be described based on examples that the low leak characteristic is effective in forming a semiconductor memory device excellent in storage retention, writing and reading operations.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Prior to specifically describing the embodiments of the present invention, the outlines of main modes of the present invention will be listed and described.

Semiconductor Device According to the Present Application A typical first embodiment of a semiconductor device according to the present invention has a first conductive region, a first insulating film, a first semiconductor region, and a second conductive region. A semiconductor device having a semiconductor region, at least a second insulating film provided on the first semiconductor region, and a third conductive region provided on a film surface of the second insulating film.

The present invention can provide a novel switch element. And, as described later, it is extremely useful as a switch section of a novel semiconductor memory device. Also, the structure of the present invention can be manufactured by a general semiconductor manufacturing method. Therefore, the semiconductor device of the present invention can be provided at extremely low cost.

A second representative embodiment of the semiconductor device according to the present invention is a semiconductor laminated region in which a first conductive region, a first insulating film, a first semiconductor region, and a second conductive region are laminated. A second insulating film provided on at least a side surface of the first semiconductor region that intersects with a laminating direction of the semiconductor laminated region; and a third conductive region provided on a film surface of the second insulating film. And a semiconductor device having:

In the above embodiments, the first conductive region, the first conductive region,
The semiconductor region having the insulating film, the first semiconductor region, and the second conductive region constitutes a charge transfer unit and a charge transfer region of an insulated gate field effect transistor. The first semiconductor region corresponds to a so-called channel region, and the first and second conductive regions correspond to either a source or a drain. Whether these are referred to as a source or a drain is merely a difference depending on the operating state. The semiconductor region of the first conductive region, the first insulating film, and the first semiconductor region is a laminate having the band structure described with reference to FIG. In this embodiment, the point where the first insulating film is provided is particularly important.

The first insulating film is made of a metal oxide, a low-oxidation oxide, a nitride, a low-nitride nitride, a silicon-metal oxide, a silicon-metal oxide, which is usually used as the first conductive region. A metal nitride, an insulator containing at least two of them, or the like is used. More specifically,
If these metals and various examples of insulators suitable for them are described, refractory metals and their oxides, nitrides, or silicides are suitable. Further, according to a specific example, as a metal or a conductor equivalent to a metal, titanium, titanium silicide, tungsten, tungsten silicide, cobalt, cobalt silicide, platinum, platinum silicide, nickel, nickel silicide, and the like can be given. I can do it. Typical examples of the insulator include silicon oxide and silicon nitride. Further, examples of the insulator include oxides or nitrides of the above-mentioned various metals or heat-resistant metals. Titanium and titanium silicide are thermally stable and are preferred examples.
Silicon oxide, silicide, or the like is a material that is often used in the manufacturing process in a general semiconductor field, and is convenient for manufacturing the semiconductor device and the semiconductor storage device of the present invention. Needless to say, the above-mentioned metals and insulators can be appropriately combined and used depending on the requirement.

The thickness of these insulating films is such that a tunnel effect at the junction is exhibited. According to the example of the thickness of the insulating film, in the case of silicon oxide, 3 nm or less,
Preferably, about 2 nm is frequently used rather than 1 nm.

Although specific examples of the first conductive region and the first insulating film have been described, these examples are described below with respect to the embodiments and embodiments of the invention described in the present specification. Needless to say, this is also applicable.

According to a third mode, in an insulated gate field effect transistor having a source, a drain, a gate electrode, and a channel region, a first insulator layer is provided on a first conductive region to be a source or drain electrode. , The first
A semiconductor material layer serving as a channel region above the insulating film, a second conductive region serving as a drain or source electrode on the semiconductor layer, and a second insulating film layer on a side surface of the channel region. In addition, it can be said that the semiconductor device has a gate electrode which exerts an electric field effect on the channel region through the second insulating film layer.

Depending on the selection of the material of each part described above, the following various forms can be considered.

In a fourth mode of the present application, the first conductive region in each of the above modes is formed of a metal material.

In a fifth aspect of the present invention, the first conductive region in each of the above aspects is formed of a semiconductor material substantially metallized by doping impurities at a high concentration. is there.

Further, in a sixth embodiment of the present application, the second conductive region is formed of a semiconductor material substantially metallized by doping impurities at a high concentration.

In the present invention, the above conductive regions can be used in combination. That is, in a seventh embodiment of the present application, the first conductive region is formed of a metal material or a semiconductor material metallized by doping impurities at a high concentration, and the second conductive region is formed of a high concentration of impurities. Is formed of a semiconductor material that is metallized by doping.

According to an eighth aspect of the present invention, the first conductive region is formed of a semiconductor material that is metallized by doping impurities at a high concentration, and the second conductive region is formed of a metal material or a high concentration. It is formed of a semiconductor material which is metallized by doping impurities.

The doping amount of the impurity necessary for metallization using the semiconductor material as a base material is sufficient using the range in the usual semiconductor field. The doping amount of silicon is usually in the range of about 10 ²⁰ cm ⁻³ or more.

It is needless to say that these examples of the doping amount can be applied to the embodiments and embodiments of the invention described in the present specification.

In the semiconductor device of the present invention, the first
The semiconductor region sandwiched between the conductive region and the second conductive region constitutes a charge transfer region of a field effect transistor, that is, a so-called channel region. Therefore, in this sense, in the present invention, the charge transfer region constitutes the charge transfer region by both the semiconductor region and the tunnel insulating film. Therefore, an example of a form indicating this intention can be stated as follows.

According to a ninth aspect of the present invention, there is provided a semiconductor device having a first conductive region, a first insulating film, a first semiconductor region, and a second conductive region; A second insulating film provided on a side surface intersecting with the laminating direction of the semiconductor region, and a third conductive region provided on a film surface of the second insulating film; Second
One of the conductive regions is formed of polycrystalline silicon doped with impurities at a high concentration, and the other of the first or second conductive region is formed of a metal, and the first conductive region is formed of a metal. A semiconductor device in which silicon and a tunnel insulating film are arranged in a current path flowing from a region to a second conductive region.

More specifically, in this embodiment, the source is formed of polycrystalline silicon doped with a high concentration impurity, the drain is formed of a metal, and the current path flowing from the source to the drain is connected to silicon. It can be said that the semiconductor device has a tunnel insulating film.

A further practical form of the semiconductor device according to the various aspects of the present invention described above is a semiconductor device in which carriers in a channel portion are depleted when switching of the semiconductor device is off. I can say. Semiconductor Memory Device Next, the semiconductor device described above, that is, a semiconductor memory device using an insulated gate field effect transistor will be described.

According to a tenth embodiment of the semiconductor memory device, one of the above-described semiconductor devices of the present invention is an information writing device, the first conductive region is a charge holding portion, Is a semiconductor memory device having an information reading element electrically connected to the semiconductor memory device.

In a more practical semiconductor memory device, the information reading element is a field effect transistor.

In the semiconductor memory device according to this aspect, it is more preferable that the charge holding portion is surrounded by an insulating film, and the information is stored based on the amount of charge held in the charge holding portion.

As described above, when a semiconductor memory device is configured by using various aspects of the semiconductor device of the present invention as information writing means, a tunnel of the semiconductor device according to the present invention is provided on the charge storage node side of the semiconductor memory device. It is preferable to connect a conductive region provided in contact with the insulating film.
This is because it is more convenient to secure the accumulated charge. It goes without saying that a semiconductor memory device can be provided regardless of which of the first and second conductive regions of the semiconductor device is provided on the charge storage node side of the semiconductor memory device.

When a semiconductor memory device is constructed by using various aspects of the semiconductor device of the present invention as information writing means, an N-type insulated gate field-effect transistor is arranged as a lateral element and a P-type It is more convenient to use the gate type field effect transistor as a vertical element using the tunnel insulating film according to the present invention.

The first representative example of the semiconductor memory device of the present invention
In one mode, a first path for moving carriers, a means for accumulating a charge for generating an electric field that changes the conductivity of the first path, and a method for transferring a desired charge to a desired voltage are provided. Means for accumulating electric charge, and means for supplying desired electric charge to the means for accumulating the electric charge, the metal electrode section, the tunnel insulating film, and the semiconductor region It is characterized by having a joint having.

In other words, this embodiment has the source or drain electrode of the field effect transistor (T1) as the semiconductor device according to the present invention and the insulated gate field effect transistor (T2) formed on the semiconductor substrate. In the semiconductor memory device, T2 is transmitted through the channel of T1.
The semiconductor memory device is connected to the gate electrode of FIG. The switch operation is performed using the tunnel insulating film. The above-described field effect transistor (T1) as a semiconductor device according to the present invention has at least a laminated structure of a conductive region, a channel region, a tunnel insulating film, and a metal conductive region. Here, the conductive region or the metal conductive region corresponds to a source or a drain of the field-effect transistor. Accordingly, the connection between T1 and T2 has the following forms.

(1) Conductive region-semiconductor region-tunnel insulating film-metal conductive region-gate of T2 (2) Metal conductive region-tunnel insulating film-semiconductor region-conductive region-gate of T2 In the structure of (1),
It is more practical to form the gate of the metal conductive region -T2 in the above or the gate of the conductive region -T2 in the above (2) in the same layer, and also serve the role of both.

To summarize the operation of the semiconductor memory device of the present invention, in the semiconductor memory device according to the eleventh embodiment, in which information is stored by the electric charge, the electric charge is taken in and out via the write element T1, and the electric charge is stored in T2. It can be said that the readout element reads out the holding state.

A twelfth aspect of the semiconductor device of the present invention is a semiconductor device, comprising: a semiconductor substrate; a first impurity region and a second impurity region provided to face the semiconductor substrate; A first insulating film covering the first semiconductor region interposed between the second impurity regions; a first conductive region, a second insulating film, and a second insulating film provided on the first insulating film; A semiconductor region having a semiconductor region and a second conductive region; a third insulating film provided on a side surface of the second semiconductor region that intersects with a lamination direction of the semiconductor regions; and a third insulating film. And a third conductive region provided on the film surface.

In this embodiment, the field-effect transistor section constituting the switch element section is configured so that its channel region crosses or substantially orthogonally crosses the substrate of the semiconductor memory device. This is a so-called vertical semiconductor device. Therefore, this mode is advantageous for miniaturization of the device. Further, by employing a structure in which the side wall of the second semiconductor region is covered with an insulating film, a semiconductor memory device with less leakage current can be provided.

Another major aspect of the present invention is a thirteenth aspect of the present invention, which is an integrated semiconductor device according to the tenth semiconductor device, further comprising means for stabilizing a potential between a gate electrode wiring of a writing element and a substrate potential. is there. A more specific requirement is that the relative potential relationship between the gate electrode and the conductive region is fixed even when the power is turned off. The simplest and practical means of stabilizing this potential is a resistor. However, many circuits can be used to answer this request.

The fourteenth embodiment of the present application is, for example, the first embodiment.
1 or an integrated semiconductor device using at least two twelfth semiconductor memory devices, wherein the read element T2
Is a semiconductor device having an electrically vertically stacked arrangement.

The fifteenth aspect of the present invention is directed to, for example, changing the source and drain potentials of T2 without changing the gate electrode potential of the write element T1 in the above-mentioned semiconductor memory devices at the time of reading information. This is a semiconductor memory device that performs a read operation by giving a potential difference between a gate electrode and the source and drain electrodes.

As described above, since the gate potential needs to be fixed, in the semiconductor memory device of the present invention, it is preferable to fix the gate potential and change the source or drain potential.

According to a sixteenth aspect of the present invention, for example, in the above-mentioned various semiconductor memory devices, when information is read, the source, the source, and the gate of the read element T2 are not changed.
This is a semiconductor memory device in which a read operation is performed by giving a potential difference between the gate electrode and the source / drain electrodes by changing a drain potential.

The seventeenth mode of the present application is, for example, the first type.
A semiconductor memory in which a plurality of the first to twelfth semiconductor memory devices are arranged in an array, and the wiring layers connected to the source and drain electrodes of the read element T2 formed on the substrate are arranged in a plane so as to be orthogonal to each other. Device.

An eighteenth embodiment of the present invention is directed to a semiconductor device or a semiconductor memory device according to the present invention, for example, the first, second, or tenth or eleventh semiconductor device or the semiconductor memory device is an SOI (Silicon On) device. In
(sulator) An integrated semiconductor device formed on a substrate. Since the insulating substrate is used as the substrate, the demand for the semiconductor device or the semiconductor memory device in which the leakage current is suppressed according to the present invention functions more effectively.

According to a nineteenth aspect of the present invention, there is provided an integrated semiconductor device having a device for stabilizing a potential without consuming power between a gate electrode wiring of a writing element and a substrate potential in the integrated semiconductor memory device.

The twentieth aspect of the present application is a semiconductor memory device having a writing device using a field effect transistor and a reading device using a field effect transistor having a conductivity type different from that of the writing device.

According to a twenty-first aspect of the present invention, in the semiconductor memory device described in the above, for example, in the semiconductor memory device described above, a potential is applied to the gate electrode of the writing element at the time of reading information to turn off the channel of the writing element more than at the time of holding charges. Device.

According to a twenty-second aspect of the present invention, there is provided an integrated semiconductor device in which, for example, the potential information to be written has at least three values in the twenty semiconductor memory devices.

A twenty-third aspect of the present invention is directed to an integrated semiconductor device for reading out stored charge information as a continuous potential in the twenty-first semiconductor memory device, for example. The twenty-fourth aspect of the present application is a semiconductor device in which, for example, in the above-described twelfth or twentieth semiconductor device, a function of performing an arithmetic process using a held charge and a gate electrode potential is added.

Principal Embodiments of the Invention Related to the Manufacturing Method of the Present Invention A first embodiment of the manufacturing method of the present invention is a step of forming a first insulating film on a semiconductor substrate, and forming a metal layer or a high-level film on the insulating film. Forming a metalized semiconductor material layer by doping impurities at a concentration, forming a second insulating film on the metal material layer or on the metalized semiconductor material layer, Forming a semiconductor material layer on the insulating film, forming a third insulating film on the side surface of the semiconductor material layer, and doping a metal layer or a high concentration impurity on the side surface of the third insulating film. This is a method for manufacturing a semiconductor device including a step of forming a semiconductor material layer which is metallized by performing the method.

In a second mode according to the manufacturing method of the present application, a step of forming a first insulating film on a semiconductor substrate,
Forming a metal layer or a metallized semiconductor material layer by doping impurities at a high concentration on the insulating film, and a second insulating film on the metal material layer or the metallized semiconductor material layer. Forming a semiconductor material in an amorphous state, forming a predetermined metal layer on the amorphous semiconductor material layer, and crystallizing the amorphous semiconductor material layer with the metal by heating. This is a method for manufacturing a semiconductor device having a step of performing

This second method of manufacturing a semiconductor device is particularly effective in manufacturing the above-described vertical transistor. That is, the semiconductor device of the present invention includes a step of stacking a semiconductor layer on a metal or an insulator layer over a semiconductor layer.
This method of crystallization is effective.

A typical example of the metal used in the second method for manufacturing a semiconductor device is nickel (Ni). The thickness of the metal layer also depends on the thickness of the amorphous semiconductor material layer that needs to be crystallized. To give an example of the thickness, a thickness of about 2 nm to 15 nm or about 5 nm to 12 nm is frequently used. Heating is selected from a range of about 500 to 700 degrees Celsius. In actual manufacturing, it is preferable that the temperature is slightly lower, that is, about 500 to 560 degrees. Vacuum is sufficient for the heating atmosphere. The heating time also depends on the thickness of the semiconductor layer that promotes crystallization, but is generally about 20 hours.

A metal layer, for example, a nickel layer is formed on the semiconductor material layer in the amorphous state, and nickel is moved to the semiconductor layer by heating. In this movement process, the semiconductor material layer in the amorphous state is crystallized. . This phenomenon itself is caused by MILC (Metal Induced La
This is known as "terial Crystallization".

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 11 shows a cross-sectional structure of a typical device according to the present invention, and FIG. 12 shows a plan layout thereof. Since the wiring structure of the present element and the method of manufacturing the same are the same as those of a normal LSI, FIG. 11 shows the structure at the time when the formation of the element basic portion is completed, and omits a wiring layer formed between elements. . In FIG. 11, 250 and 350 are a source and a drain, and the gate 5 is connected to the channel 150 via an insulating film 980.
00 exerts an electric field effect from both sides. Drain 35
Carriers that pass (tunnel) through the insulating film 931 sandwiched between the channel 0 and the channel 150 are controlled by the gate 500. Reference numeral 600 denotes a buried wiring layer drawn from the drain 350.

In this structure, there is no unnecessary junction other than the channel shown in FIG. 2, and the insulating film 931 is interposed between the junction of the channel and the electrode, so that the leak current can be suppressed.

The manufacturing process will be described below with reference to FIGS.

The thickness of the silicon substrate 100 is 500 nm
Is formed. Next, a photoresist layer is formed on this, and this photoresist layer is patterned into a desired shape. Then, the thus prepared silicon substrate is formed into the thermal oxide film 900 by ordinary anisotropic dry etching, for example, the grooves 102 and 10 having a depth of 300 nm.
Form 3 (Fig. 5) Tungsten is deposited on the surface of the substrate, and the CMP (Chemic
al Mechanical Polishing), the grooves 102, 10
Tungsten deposited other than 3 is removed. This step is known as the damascene method. Thereby, the groove 10
A structure in which tungsten 600 is packed in 2, 103 is obtained. (FIG. 6) Titanium 100 nm (350) and titanium oxide 5 nm (931) are deposited on the substrate, and polycrystalline silicon 200 nm (150) is further deposited. This polycrystalline silicon layer 150 is a layer serving as a channel. By making this a single crystal, the level of a grain boundary that causes a leak current can be reduced. This element structure does not include a patterning step other than forming the grooves described with reference to FIG. Further, the lower wiring layer formed by using the groove is disposed below the channel portion 150 and the like as shown in FIG. Therefore, it can be formed by first laminating a laminated structure and patterning the laminated structure from above. Therefore, a channel using a single crystal can be realized. (FIG. 7) After the titanium oxide is deposited, a nickel thin film is deposited. After that, by depositing amorphous silicon and applying a low-temperature heat treatment at 550 ° C., nickel can be moved in the silicon and the polycrystalline silicon layer 150 can be crystallized. Thus, a channel region having good crystallinity can be obtained. The nickel thin film is selected in a thickness range of 2 nm to 10 nm, more preferably in a range of 3 nm to 6 nm. After the crystallization treatment, the nickel layer can be removed.

Patterning is performed using a photoresist to process polycrystalline silicon, titanium oxide, and titanium, exposing the surface of the oxide film 900 except for the grooves. An oxide film 920 is deposited on the semiconductor substrate thus prepared. Next, the oxide film 920 is etched on the surface by the CMP method, and the surface of the oxide film 920 is flattened to match the surface of the polycrystalline silicon layer 150. Next, a polycrystalline layer 25 doped with impurities at a high concentration
0, and a silicon nitride film 950 is further deposited. At this time, an extremely thin insulating film can be formed by nitriding the surface of the polycrystalline silicon layer 150 before depositing the polycrystalline layer 250 doped with impurities at a high concentration. With this thin insulating film, diffusion of impurities from the outside into the polycrystalline silicon layer 150 can be suppressed. Since this insulating film acts as a load for the current driving force of the channel, the insulating film can be directly deposited on the polycrystalline silicon layer 150 if the channel length can be secured as compared with the required heat treatment. Here, the channel length is polycrystalline silicon 1
Equivalent to a thickness of 50.

The electrode layer 250 is formed by depositing a silicide such as Pt or Er or a metal nitride film, for example, TiN or WN as a heat-resistant barrier layer, and further laminating a layer of a metal material (for example, tungsten or the like). be able to. The nitride film and the metal layer are etched to 920 surface.
Although not shown in the cross-sectional structure, at this time, a lead for forming the contact (720) is formed as shown by reference numeral 250 in FIG. (FIG. 8) A silicon oxide film 921 is deposited on the substrate thus prepared, and the surface is flattened by the CMP method. here,
Hereinafter, an oxide film layer which is deposited and laminated as an interlayer film is denoted by reference numeral 921.
Indicated by (FIG. 9) Further, a gate pattern using a usual photoresist is formed on the base. Then, by the etching method using this gate pattern, the interlayer insulating film 92 is formed.
1 is formed with a groove 104. The side surfaces of the electrode layer 250 and the polycrystalline silicon 150 serving as a channel are exposed. (FIG. 10) 5n is formed on the surface of the laminated body in the groove 104 by the CVD method.
After depositing a silicon oxide film 980 m, the gate 500
Is formed in the groove. As the gate insulating film, for example, a silicon nitride film or a titanium oxide can also be used. In FIG. 11, the silicon oxide film 980 is formed on the entire inner surface of the groove 104. This silicon oxide film
It is not always necessary to cover the entire surface of the groove 104. For example, the side walls of the interlayer insulating film 921 are not necessarily required. However, in this example, since the oxide film is formed by the CVD method, it is formed on the entire surface of the groove 104. This means
The same applies to the following embodiments. (FIG. 11) Thereafter, wiring is formed in the same manner as in a normal LSI manufacturing process.

FIG. 12 is a diagram showing a planar layout of a contact region for leading out from a main part of the semiconductor device. A region denoted by reference numeral 500 indicates a planar region corresponding to the gate. The figure shows a contact 710 to the buried extraction layer 600, a contact 730 to the gate 500,
An example of the arrangement of the contact 720 to the electrode 250 is shown. As can be seen in FIG.
Since the barrier 931 is sandwiched between the channel 0 and the channel 150, the leakage current can be strongly suppressed.

When polycrystalline silicon doped at a high concentration is used for the electrode 250, the electrode serves as a supply source of channel carriers. Therefore, N-type and P-type devices are formed depending on the conductivity type of impurities. be able to.

In the above embodiment, the drawer is formed by
Although the upper electrode 250 is formed after the channel patterning, it can be formed simultaneously with the channel 150. This example will be described with reference to FIGS.

In this embodiment, the device is manufactured in the same manner as in FIGS. 5 to 7 of the above embodiment. That is, the wiring 600, the titanium layer 350, and the titanium oxide layer 93 are formed on a predetermined base.
1. A polycrystalline silicon layer 150 is formed. On the substrate thus prepared, a titanium oxide layer 93 was further added.
2. A titanium layer 250 and an insulating film 950 are deposited. (Figure 1
3) A gate pattern using a usual photoresist is formed on the base. Then, the stacked film is etched by the etching method using the gate pattern until the surface of the oxide film 900 is exposed. (FIG. 14) Next, after depositing an oxide film 920 on the substrate, CM
The surface is flattened by the P method, and further etched back until the surface of the insulating film 950 is exposed. (FIG. 15) Further, a gate pattern using a usual photoresist is formed on the base. Then, the groove 1 is formed in the layer 920 by an etching method using this gate pattern.
05 is formed. A gate insulating film 980 is formed on the side wall of the stacked body in the groove 105 thus formed. Further, the groove 105
A gate layer 500 is deposited therein. Then, the gate layer 50
By etching back 0, the gate layer 500 is buried up to the side surface of the electrode layer 250. (FIG. 16) After filling the groove on the gate layer 500 with the insulating film 921, the surface is flattened and the insulating film 950 is exposed. Then, the insulating film 9
After removing 50, a wiring for the electrode layer 250 is formed by forming a layer 650 of a metal material. This step is the same as a normal contact hole forming and metal wiring forming process. Thus, contact formation and wiring formation on the gate layer 500 and the buried layer 600 can be performed simultaneously. (FIG. 17) In order to show the effectiveness when this element is used for an integrated circuit, an example in which an OR circuit and an AND circuit (or a NAND circuit), which are typical operation gates, are shown.

FIG. 18 is an equivalent circuit diagram showing a 4-input OR circuit. FIG. 19 is a diagram showing a planar layout of an electrode portion corresponding to this. In FIG. 19, only the gate layer 500, the lead-out part 600, and the lead-out of the electrode 250 and only the respective contacts are shown to show the entire arrangement.

Although the circuit itself shown in FIG. 18 is a typical one, the present invention is characterized by the structure of the channel region of the insulated gate field effect transistor constituting this circuit and the structure for removing each part thereof. For easy understanding in the drawings, the channel region of the insulated gate field effect transistor according to the present invention is indicated by a broken line.

FIG. 20 is an equivalent circuit diagram of a three-input AND circuit. FIG. 21 is a diagram showing a planar layout of an electrode portion corresponding to this. The lead portion 600 and the electrode 250 are
By connecting them alternately, a vertical stack of elements on the circuit can be formed. Therefore, this example is extremely advantageous for miniaturization.
In FIG. 21, the electrode layer 250, which is the upper extraction layer, is shown by hatching in order to easily understand this situation.

As described above, using the structure of the present invention,
By selecting an impurity, a complementary element such as a CMOS can be formed. That is, in the structure of the present invention, the conductivity type of the impurity to be doped can be changed by the ion implantation method when the electrode 250 is formed.

FIG. 22 is a diagram showing a planar layout of an electrode portion of an example of an inverter. In this example, an inverter is formed using the structure of the semiconductor device of the present invention and using N-type and P-type elements in the channel region. Of the two electrodes 250, the upper side is doped with arsenic and the lower side is doped with boron. Gate contact 7
30 is an input terminal, a contact 720 to the drawer 600
Is an output terminal. To the electrode layer 250 by the wiring 650
A ground potential and a power supply potential are supplied, respectively.

FIG. 23 is a diagram showing a planar layout of an electrode portion showing a state where inverters are connected in two stages. That is,
The structure of FIG. 23 is a structure in which the structure of FIG. 22 is connected in two stages. By overlapping the input 730 and the output 720, two inverters are connected.

In the process, by forming the contact 720 before depositing the gate 500, it is possible to directly connect to the next stage.

In the device structure of the present invention, since a vertical structure is used, one problem is to form a wiring extending from the upper electrode 250. A drawer forming method other than the above embodiment will be described with reference to FIGS. FIG.
FIGS. 4 to 29 are cross-sectional views of the device shown in the order of the manufacturing process for explaining the present example.

The same laminate as that of FIG. 13 is obtained by the steps described in the manufacturing method of the present invention. That is, the insulating layer 900 is provided on the semiconductor substrate 100, and the embedded wiring 600 and the like are formed in the insulating film. Then, a titanium layer forming the metal electrode 350, a titanium oxide layer forming the tunnel insulating film 931, a polycrystalline silicon layer forming the channel region 150, and a second conductive region 250 are formed on the base thus prepared. A titanium layer and a silicon oxide layer as an upper insulator layer 920 are stacked.
Then, in order to obtain a desired shape in the traveling direction of carriers of the field-effect transistor, that is, in the channel direction, patterning is performed by a usual method. FIG. 24 shows a columnar laminated film (layers 350 and 15) patterned in the direction perpendicular to the paper surface.
0, 250, and 920). (FIG. 24) After a gate insulating film is formed over the substrate thus prepared, the gate electrode layer 500 and the insulating film 955 are stacked. still,
The gate insulating film exists between the layer 500 and the layer 920, but is not shown in FIG. or,
As the insulating film 955, a silicon nitride film was used. Then, the stacked body, the layer 500, and the layer 955 are patterned into a desired shape. FIG. 25 shows the gate cross section only on the pillar depending on how the cross section is taken. For example, as seen in FIG. 16, the layer 500 is formed deep within the trench 105. A similar structure exists in this example. (FIG. 25) Next, an insulating film 956 serving as a spacer is deposited on the side walls of the layers 500 and 955. Using the regions of the insulating films 955 and 956 as mask regions, the stacked films 920 and
Etch 50, 150, 350 into the desired shape.
The insulating films 955 and 956 may be formed by, for example, a general CVD method. (FIG. 26) Thus, an oxide film 921 is deposited on the prepared base,
Further, the surface of the laminate is flattened by the CMP method.
(FIG. 27) A mask having an opening in a region corresponding to the lead formation portion is formed, and a groove is formed using the region of the insulating films 955 and 956 as a mask region to expose the side surface of the conductor layer 250. (FIG. 28) By embedding tungsten 625 inside this groove,
Form a lead wiring. This allows adjacent elements to be connected in a self-aligned manner. That is, FIG.
9, the regions of the respective conductive layers 250 are separated by the grooves 251, but are electrically connected to each other by the tungsten layer 625. The dimensions of the tungsten layer 625 are defined by the grooves 251 formed so far. That is, in the present example, subsequent dimensions are defined by forming a mask used for forming the groove. (FIG. 29) The semiconductor device of the present invention is characterized in that electrode leakage can be extremely suppressed. In utilizing this feature, application to a memory element that stores information by using electric charges is generally suitable. In particular, by using a type called a gain cell, an excellent semiconductor memory device can be provided.

FIG. 30 is a cross-sectional view of an application example of a semiconductor device according to the present invention in a gain cell schematically showing only a main part. The memory cell includes a reading unit using an element formed on the semiconductor substrate 100 and a storage information writing unit using the element of the present invention.

An impurity region 22 customary in the semiconductor substrate 100
0 and 320 are formed to form the channel region of the field effect transistor. A gate insulating film 970 is formed to cover the channel region. The transistor section configured in this manner is the read section. Then, a storage information writing section as described below is formed on this upper portion.
Since the semiconductor device serving as the storage information writing unit is the element according to the present invention described above, the detailed description thereof is omitted here. In FIG.
31 is a tunnel insulating film, 150 is a semiconductor layer serving as a channel, 250 is a second conductor layer, 980 is a gate insulating film,
500 is a gate electrode layer.

The conductive region 350 serving as an electrode is formed directly on the gate insulating film 970 and serves as a drain of a writing element and a gate electrode of a reading element. In this memory cell, information is stored as electric charge of the electrode 350, the channel characteristics are changed by an electric field effect applied to the read element, and the information is read as a current flowing between the electrodes 220 and 320. The small leak of the conductive region 350 serving as the memory holding unit enables good information holding performance. Here, the resistance value is not so important because the conductive region 350 is a storage unit. Therefore, the conductive region and the electrode layer may be formed using polycrystalline silicon metallized by doping impurities at a high concentration.

FIGS. 31 and 32 show examples of the basic circuit configuration of a typical memory element. Next, the operation of these memory cells will be described.

FIG. 31 is a circuit diagram of a memory cell equivalently showing the semiconductor element shown in FIG. In order to facilitate understanding of the circuit, two transistors T1 and T1 shown in FIG.
2, the reference numerals of the respective parts shown in the structural diagram of FIG. The transistor constituting the reading section of the element T1 and the element T2 are a storage information writing section using the semiconductor device according to the present invention.

D1 is a read word line, D2 is a write word line, D3 is a write data line, and D4 is a read data line. By turning on D2, the potential of D3 is written to the memory holding portion (gate electrode), and by turning off, the charge is held. At this time, the gate potential of the read element is determined. For example, when the gate potential exceeds the threshold value of the transistor, a current flows when a potential difference is applied between D1 and D4. On the other hand, when the gate potential is lower than the threshold value, no current flows even if a potential difference is applied between D1 and D4. Therefore, the gate potential can be read by this current.

FIG. 59 is a time chart showing an example of each signal in the above example. D1, D2, D3, and D4 indicate the application of voltages to the read word line, write word line, write data line, and read data line, respectively. Here, the wiring symbols shown in FIG. 31 are used. Figure 59
Means writing (tw) and reading (tr) by the memory cells used for writing and reading elements of the same conductivity type.
Is repeated. Here, at the time of reading,
An example is shown in which a potential change of D4 is read and driven by a sense amplifier. D4 shows an example in which an intermediate potential is applied once before the tr step, and reading is performed based on a change therefrom.

In this structure, since the writing section and the reading section are separated from each other in operation, the problem that the reading operation destroys information in other cells does not occur even if they are integrated. In the equivalent circuit diagram shown in FIG. 31, D1, D2, D3
And D4 are arranged so as to be geometrically parallel for each set. However, in the actual structure of the semiconductor device, at least D1 and D4 and D2 and D3 may be arranged so as to be orthogonal to each other. D1 and D2 and D3 and D4 need not necessarily be arranged geometrically parallel. This is because reading and writing are separated.

FIG. 32 shows a case in which the write and read word lines are shared by D4. In order to explain the operation, a capacitor 910 is positively added. However, in an actual structure, since the electrode 350 and the gate 500 have an overlap, they can be formed without adding a special process. It is possible to set a so-called parasitic capacitance and use this as this capacitance.

D1 and D3 are read data lines, D2 is a write data line, and D4 is a word line. When the write element and the read element are formed with opposite conductivity types, they can operate complementarily. For example, when the write element is P-type and the read element is N-type, the write element is turned on by applying a negative potential to the word line D4, and the potential is written. On the other hand, in the read element, the channel is turned on by applying a positive potential. That is, by applying a positive potential to D4, a positive potential can be applied to the gate of the reading element by capacitive coupling. At this time, in the writing element, the off state is further increased, so that charge leakage can be suppressed. In a conventional gain cell, complementary operation could not be performed, so that it was necessary to apply the highest gate voltage at the time of writing (erasing) and to read at a lower voltage so as not to destroy the information. Therefore, the potential range that can be used as information is narrow, and it is difficult to provide multi-value information. In the complementary operation, since there is no such restriction on the word line potential at the time of reading, multi-valued information (multi-stage potential state) can be used.

FIG. 60 shows a time chart of the basic operation of the complementary memory cell. The feature is that D2 is biased in the opposite direction at the time of writing (tw) and at the time of reading (tr). FIG. 60 illustrates an example in which quaternary potentials are sequentially written to storage nodes and read operations are repeated. Here, an example is shown in which a D4ha current sense is applied to operate at a constant potential. Note that D
1, D3 indicates a read data line, D2 indicates a write data line, and D4 indicates a voltage to a word line. As seen from the voltage state of D3, for example, it is possible to use substantially four-valued information.

Further, since there is no restriction on the gate potential at the time of reading due to data destruction, the applied potential can be given freely, so that the stored charge state can be read out as a continuous state instead of digitized one. .
In addition, since the read result is given by the gate applied voltage and the state of the retained charges, arithmetic processing can be performed using the read result.

FIG. 33 shows an example in which the memory cells of FIG. 31 are arranged in an array. C0 is a write word line driver, C1 is a write data line driver, C2 is a read word line driver, and C3 is a read data line sense. Since each memory cell section has been described above in FIG. 33, the details are omitted here. In this example, a general method of driving a memory device can be used.

The suppression of the leakage current in the structure of the semiconductor device of the present invention is achieved by effectively controlling the tunnel phenomenon of the insulating film sandwiched between the electrode and the channel by the gate electrode. That is, it is important to maintain the potential relationship between the write element gate and the drain electrode serving as the memory holding section in reducing the leak current. Therefore, in this memory element application, it is effective to provide a device R capable of stabilizing the write word line at a certain potential state. As for this means, as described above, it is sufficient to connect a resistor as the device R, for example. This means R
Thereby, the potential of the write word line can be normally set to the ground potential.

That is, even if the storage device is disconnected from the power supply, the word line is fixed at the ground potential and the leak current can be suppressed, so that the information can be kept for a long time. When a resistor is used as the device R, power consumption increases in an operating state, that is, in a state in which a word line is selected. However, the number of selected word lines is at most one in the array, and an appropriate size is selected. By selecting such a resistor, good information retention characteristics can be obtained without significantly increasing power consumption.

Even if the memory cell shown in FIG. 32 is used, a memory cell array can be formed in the same manner as in FIG. On the other hand, as shown in FIG. 34, it is effective to form a so-called NAND type array in which multiple stages of memory cells are stacked. This is because they can work complementarily, so that cells connected to the same read data line B0, B1, and B2 can be turned on by sequentially applying voltages to A0 to A7. Therefore, since the data line is formed by the diffusion layer and the channel, the number of wirings and contacts can be reduced. Therefore, miniaturization of the memory cell is facilitated, and high integration can be achieved.

A typical memory cell forming process will be described with reference to FIGS. These figures show a cross-sectional structure of the semiconductor memory device. The figure also shows different cross sections on the left and right sides of the center gap. The cross section on the left side of the drawing is a cross section in which the gate electrode 500 extends perpendicularly to the plane of the paper, and the cross section on the right side is a cross section including the gate electrode 500 in the plane of the paper.

Normal MOSLS on silicon substrate 100
An element isolation insulating film 900 is formed by a shallow trench element isolation method used for forming I. Next, by thermally oxidizing the exposed silicon surface, the read element gate insulating film 90 is formed.
5 is formed. On top of that, a metal electrode 3 serving as a storage node
50, the tunnel film 931 and the channel 150 are stacked. (FIG. 35) Semiconductor Layer 150 and Electrode 350 to Be Channel Region
Is patterned into a desired shape by a conventional photoresist method. Thus, a groove 105 is formed. Next, ion implantation is performed on the region opened by the above-described processing to form the diffusion layer 220. (FIG. 36) An oxide film 921 is deposited on the substrate thus prepared, and its surface is planarized by the CMP method.
Etch back until is exposed. (FIG. 37) After forming a thin nitride film for suppressing impurity diffusion, polycrystalline silicon 250 doped with high-concentration impurities is deposited. Then, the polycrystalline silicon 250 is processed into a desired shape to form a write element data line 250. Here, the illustration of a thin nitride film for suppressing the impurity diffusion is omitted. (FIG. 38) A groove 107 is formed by etching the oxide film in the write element gate formation portion. Thus, the exposed channel region 1
A gate insulating film 980 is deposited on at least the side surfaces of the gate insulating film 50. It is known that an insulating film formed on a diffusion layer has a large deterioration in breakdown voltage. Therefore, here, the withstand voltage is improved by providing the insulating layer 935 serving as a spacer. By forming a gate insulating film over the substrate except for the spacer and the diffusion layer, the source and the drain may be formed by an inversion layer due to the electric field effect of the gate instead of the diffusion layer. (FIG. 3
9) Form a gate layer 500 and then pattern this layer 500 as a write element word line. In the sectional view on the right side of FIG. 40, the gate 500 having a desired shape is shown, and in the sectional view on the left side, the gate electrode existing in the groove 107 is shown. Since this memory cell is formed on a silicon substrate, it can be integrated with a conventional MOSFET with good consistency. (FIG. 40) Next, another memory cell forming method different from the above is described in FIG.
This will be described with reference to FIG. In these figures,
As described above, the two cross-sectional structures are combined.

A gate insulating film 905 of a read element, an electrode 250 serving as a storage node, a tunnel film 931, a channel 150, an upper electrode 250, and an electrode protection film 950 are stacked on the silicon substrate 100 having the element isolation region 900 formed thereon. (FIG. 41) The laminated film is processed into a groove 201 in the read data direction, and the electrode 220 is formed by ion implantation. (FIG. 4
2) The laminated film is processed by a word line pattern in a word line direction orthogonal to the data lines. (FIG. 43) After the gate insulating film 980 is formed, the gate 500 is deposited and etched to form a spacer-like gate around the columnar laminated film. At this time, as shown on the right side of the drawing, the column interval in the word line direction is made narrower than that in the data line direction (left side in the drawing), and the deposition thickness of 500 is reduced to 1/1 / the word line direction interval.
By setting it to 2 or more and 1/2 or less of the data line direction interval,
The gate electrodes can be connected in a self-aligned manner only in the word line direction. (FIG. 44) An interlayer film 921 is deposited on the substrate thus prepared.
Then, this is flattened to expose the electrode protection film 950. (FIG. 45) The electrode protection film 950 is removed, and a metal wiring 625 is deposited. Then, by processing the metal wiring 625 into a desired shape, a writing element data line can be formed. (FIG. 46) In this memory cell, before the gate 500 is formed (FIG.
After the first step), the shield layer 935 can be formed by once flattening with an oxide film and etching back. (FIG. 47) Thereby, the mutual interference between the write element and the read element can be reduced, and the withstand voltage of the read element can be improved.

Further, another method of forming a memory cell will be described with reference to FIGS. FIG. 48 shows a layout of a semiconductor memory device in which the memory cells shown in FIG. 31 are arranged in an array. Here, it is shown using 12 cells. D1, D2, D3, and D4 in FIG. 48 each correspond to those in FIG. That is, D1 is a read word line, D2 is a write word line, D3 is a write data line, and D4 is a read data line. The figure schematically shows each data line, each word line, a contact hole, and an impurity diffusion region in the base. The read word line D1 and read data line D4 represented by thin lines are
The write word line D2 represented by a bold line is disposed in the lower layer of the semiconductor laminated body and in the upper layer. The hatched region is an impurity diffusion region. A contact hole 1003 indicated by a thin line is an opening for connecting D3 and D4 or D3 and D1 disposed in a lower layer. On the other hand, a contact hole 1002 represented by a thick line
Is an opening for connecting D3 and the write word line D2 arranged in the upper layer. More specifically, FIG.
58 through FIG. 58.

FIGS. 49 to 58 show A-
A and B-B cross sections are shown separately on the left and right sides, respectively.

FIGS. 49 to 58 show SOI (Sil)
2 shows a method for forming a memory cell using an icon on insulator (Ion) substrate. Obviously, also in the memory cell, the read element can be formed on the SOI substrate.

First, a wafer having a silicon layer (SOI) 100 on a buried oxide film 900 mounted on a support substrate 1200 and an oxide film as a protective layer 910 is prepared. The support substrate 1200 is typically silicon. Since the supporting substrate is not directly related to the structure and the basic operation, the supporting substrate is not shown in the following drawings. (FIG. 49) The element isolation region 960 and the protective film 910 are formed again on the wafer by the usual shallow trench isolation method. The necessary diffusion layer 220 is formed by applying heat treatment. (FIG. 50) An opening 901 corresponding to the contact formation portion is formed in the protective film 910.
I do. Then, polycrystalline silicon 360 heavily doped is deposited through the opening 901 to form a read word line and a lead layer. Then, insulating films 9900 and 9901 are formed thereon, and these are patterned into a desired shape. (FIG. 51) An opening 902 is made in the upper part of the lead layer of the semiconductor substrate thus prepared. Then, a polycrystalline silicon film 660 heavily doped and an interlayer insulating film 9902 are again deposited on this upper portion. Then, the interlayer insulating film 9902 is formed into a desired shape by a usual method, and the polycrystalline silicon film 660 is formed in a desired shape of the read data line using the interlayer insulating film 9902 as a mask region. (FIG. 52) Next, after depositing an interlayer insulating film 922 and an interlayer insulating film layer 923, the surface is flattened by a CMP method. Here, the insulating film 922 is, for example, a silicon nitride film, an insulating film 92.
3 is a silicon oxide film, for example. (FIG. 53) Next, the interlayer film in the write element formation portion is removed, and an opening 90 is formed.
Form 3 The surface of the silicon 100 is exposed in this opening. (FIG. 54) Further, after forming the gate oxide film 905, the metal electrode 350,
A tunnel film 931 and polycrystalline silicon 150 are stacked.
(FIG. 55) The laminated films 350, 931 and 150 are etched and processed into a columnar shape up to the surface of the insulating film 923. An interlayer insulating film 921 is deposited on the upper portion and etched back to expose the polycrystalline silicon film 150. (FIG. 56) The write data line 2 is formed on the polycrystalline silicon film 150.
Form 50. Further, an interlayer insulating film 926 is formed to cover the write data line 250, and the surface of the stacked body is flattened by this layer. (FIG. 57) A groove 904 corresponding to the gate pattern is formed in the interlayer insulating films 926 and 921. At least the exposed semiconductor layer 150
A gate insulating film 980 is formed on the side wall of. Then, the write word line 500 is formed to cover the gate insulating film 980. In this structure, the gate electrode and the write word line are formed in the same layer. (FIG. 58) By these methods described above, a semiconductor memory device having excellent writing and storage holding performance can be formed.

In the field-effect transistor, the leakage current of the electrodes serving as the source and drain could be suppressed to a very low level by controlling the tunnel phenomenon by sandwiching an insulating film between the Schottky junctions. Further, by applying this low leak characteristic, a semiconductor memory device having excellent information retention characteristics can be formed.

As described above, according to the present invention, a field effect transistor having extremely low leakage current can be provided.

According to another aspect of the present invention, it is possible to provide a semiconductor memory device having excellent information retention characteristics.

According to the manufacturing method of the present invention, it is possible to easily manufacture a novel device such as a field effect transistor having a very low leak current or a semiconductor memory device.

[0114]

According to the present invention, a field effect transistor having extremely low leakage current can be provided.

According to another aspect of the present invention, it is possible to provide a semiconductor memory device having excellent information retention characteristics.

According to the manufacturing method of the present invention, it is possible to easily manufacture a novel device such as a field effect transistor having extremely low leakage current or a semiconductor memory device.

[Brief description of the drawings]

FIG. 1 is a typical element cross-sectional view showing a conventional element structure.

FIG. 2 is a sectional structural view schematically showing another conventional element structure.

FIG. 3 is a band diagram illustrating a conventional Schottky junction.

FIG. 4 is a band diagram for explaining bonding used in the present invention.

FIG. 5 is a sectional structural view for explaining an element manufacturing process.

FIG. 6 is a sectional structural view for explaining an element manufacturing process.

FIG. 7 is a sectional structural view for explaining an element manufacturing process.

FIG. 8 is a sectional structural view for explaining an element manufacturing process.

FIG. 9 is a sectional structural view for explaining an element manufacturing process.

FIG. 10 is a sectional structural view for explaining an element manufacturing process.

FIG. 11 is a sectional structural view for explaining an element manufacturing process.

FIG. 12 is a plan layout diagram for explaining an element plane arrangement.

FIG. 13 is a cross-sectional structural view for explaining an element manufacturing process in another mode.

FIG. 14 is a cross-sectional structural view for explaining an element manufacturing process in another mode.

FIG. 15 is a cross-sectional structure diagram for explaining an element manufacturing process in another mode.

FIG. 16 is a cross-sectional structure diagram for explaining an element manufacturing process in another mode.

FIG. 17 is a cross-sectional structural view for explaining an element manufacturing process in another mode.

FIG. 18 is an equivalent circuit diagram illustrating an OR gate.

FIG. 19 is a plan layout diagram for explaining a plan layout of an OR gate;

FIG. 20 is an equivalent circuit diagram illustrating an AND gate.

FIG. 21 is a plan layout diagram for explaining a plan layout of an AND gate;

FIG. 22 is a plan layout diagram illustrating a plan layout of inverter gates.

FIG. 23 is a plan layout diagram for explaining a plan layout of a multi-stage inverter gate;

FIG. 24 is a sectional structural view for explaining another element manufacturing process.

FIG. 25 is a sectional structural view for explaining another element manufacturing process.

FIG. 26 is a sectional structural view for explaining another element manufacturing process.

FIG. 27 is a sectional structural view for explaining another element manufacturing process.

FIG. 28 is a sectional structural view for explaining another element manufacturing process.

FIG. 29 is a sectional structural view for explaining another element manufacturing process.

FIG. 30 is a sectional structural view schematically showing a memory cell element structure.

FIG. 31 is an equivalent circuit diagram illustrating a memory cell.

FIG. 32 is an equivalent circuit diagram illustrating another memory cell.

FIG. 33 is an equivalent circuit diagram illustrating a memory cell array.

FIG. 34 is an equivalent circuit diagram illustrating a memory cell array.

FIG. 35 is a cross-sectional structure diagram illustrating a memory cell element manufacturing process.

FIG. 36 is a cross-sectional structure diagram for explaining a memory cell element manufacturing process.

FIG. 37 is a cross-sectional structure diagram for explaining an element manufacturing process of the memory cell;

FIG. 38 is a cross-sectional structure diagram illustrating a memory cell element manufacturing process.

FIG. 39 is a cross-sectional structure diagram illustrating a memory cell element manufacturing process.

FIG. 40 is a cross-sectional structure diagram illustrating a memory cell element manufacturing process.

FIG. 41 is a cross-sectional structure diagram for explaining an element manufacturing process of another memory cell.

FIG. 42 is a cross-sectional structure diagram for explaining an element manufacturing process of another memory cell.

FIG. 43 is a cross-sectional structural view for explaining an element manufacturing process of another memory cell;

FIG. 44 is a cross-sectional structure diagram for explaining an element manufacturing process of another memory cell;

FIG. 45 is a cross-sectional structural view for explaining an element manufacturing process of another memory cell.

FIG. 46 is a cross-sectional structure diagram for explaining an element manufacturing process of another memory cell;

FIG. 47 is a cross-sectional structure diagram for explaining an element manufacturing process of another memory cell;

FIG. 48 is a plan layout diagram illustrating a plan layout of a memory cell array.

FIG. 49 is a plan layout diagram illustrating a plan layout of a multi-stage inverter gate;

FIG. 50 is a plan layout diagram for explaining a plan layout of a multi-stage inverter gate;

FIG. 51 is a plan layout diagram for explaining a plan layout of a multi-stage inverter gate;

FIG. 52 is a plan layout diagram for explaining a plan layout of a multi-stage inverter gate;

FIG. 53 is a plan layout diagram for explaining a plan layout of a multi-stage inverter gate;

FIG. 54 is a plan layout diagram illustrating a plan layout of a multi-stage inverter gate;

FIG. 55 is a plan layout diagram for explaining a plan layout of a multi-stage inverter gate;

FIG. 56 is a plan layout diagram for explaining a plan layout of a multi-stage inverter gate;

FIG. 57 is a plan layout diagram for explaining a plan layout of a multi-stage inverter gate;

FIG. 58 is a plan layout diagram for explaining a plan layout of a multi-stage inverter gate;

FIG. 59 is a diagram showing a time chart for the basic operation of the semiconductor memory;

FIG. 60 is a diagram showing a time chart for a basic operation of a semiconductor memory device handling multi-valued information.

[Explanation of symbols]

100, 110: silicon substrate, 150: polycrystalline silicon, 320: impurity diffusion layer electrode, 500, 510: gate electrode, 250, 350: electrode, 600, 625, 66
0: metal wiring, 710, 720, 730: contact,
900, 901, 905, 910, 920, 921, 9
22, 923, 924, 925, 926, 931, 93
2, 955, 956, 960, 980: insulating film layer.

Claims (10)

[Claims] A semiconductor region having a first conductive region, a first insulating film, a first semiconductor region, and a second conductive region; and a second insulating film provided in the first semiconductor region. When,
A third conductive region provided on a film surface of the second insulating film. 2. A semiconductor laminated region in which a first conductive region, a first insulating film, a first semiconductor region, and a second conductive region are laminated, and the semiconductor laminated region of at least the first semiconductor region. A semiconductor device comprising: a second insulating film provided on a side surface that intersects with a direction in which regions are stacked; and a third conductive region provided on a film surface of the second insulating film. 3. An insulated gate field-effect transistor having a source, a drain, a gate electrode, and a channel region, wherein the transistor has a first insulator layer on a first conductive region serving as a source or drain electrode. A semiconductor material layer serving as a channel region over the first insulating film, a second conductive region serving as a drain or source electrode on the semiconductor material layer, and a second insulating film on a side surface of the channel region A semiconductor device, comprising: a gate electrode that has a layer and exerts an electric field effect on the channel region through the second insulating film layer. 4. The semiconductor device according to claim 1, wherein said first conductive region is made of a metal material. 5. The semiconductor device according to claim 1, wherein the first conductive region is made of a semiconductor material which is metallized by doping impurities at a high concentration. 6. The method according to claim 1, wherein the first conductive region is formed of a metal material or a semiconductor material metallized by doping impurities at a high concentration, and the second conductive region is formed by doping impurities at a high concentration. The semiconductor device according to claim 1, wherein the semiconductor device is formed of a metallized semiconductor material. 7. A semiconductor laminated region in which a first conductive region, a first insulating film, a first semiconductor region, and a second conductive region are laminated, and a semiconductor laminated region of the second semiconductor region. A second insulating film provided on a side surface intersecting with the laminating direction, and a third conductive region provided on a film surface of the second insulating film, wherein the first or second conductive film is provided. One of the regions is formed of polycrystalline silicon doped with impurities at a high concentration, and the other of the first or second conductive regions is formed of metal, and the first or second conductive region is formed of metal. A semiconductor device, wherein silicon and a tunnel insulating film are arranged in a current path flowing through a second conductive region. 8. The semiconductor device according to claim 1, wherein the semiconductor device is an information writing device, the first conductive region is a charge holding portion, and the semiconductor device is electrically connected to the charge holding portion. A semiconductor memory device having an information reading element. 9. A semiconductor substrate, a first impurity region and a second impurity region provided opposite to the semiconductor substrate,
A first insulating film covering at least the first semiconductor region interposed between the first impurity region and the second impurity region; a first conductive region provided on the first insulating film;
A semiconductor region having an insulating film, a second semiconductor region, and a second conductive region, and a third insulating film provided on a side surface of the second semiconductor region that intersects with a lamination direction of the semiconductor regions. And a third conductive region provided on a film surface of the third insulating film. 10. A step of forming a first insulating film on a semiconductor substrate, and forming a metal layer or a semiconductor material layer metallized by doping impurities at a high concentration on the first insulating film. Forming a second insulating film on the metal material layer or the metalized semiconductor material layer; forming the semiconductor material layer in an amorphous state; A method for manufacturing a semiconductor device, comprising: forming a predetermined metal layer; and crystallizing the amorphous semiconductor material layer with the metal by heating.