JP2001084171A - Image processing device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To miniaturize the constitution by sharing a circuit for operating plural different segmentation processing to plural processors. SOLUTION: In this picture processor, one part of data read from a DRAM 4 being an outside memory connected with a shared bus 2 connecting plural processors 1A and 1B in parallel is segmented by a funnel shifter 31 being a first segmenting circuit, and the segmented data are segmented by a second segmenting circuit, and written through local buses 6A and 6B in the processor in local memories 7A and 7B.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing apparatus for performing an operation suitable for displaying stored image data on a screen.
It is used in an image processing device that performs decompression.

[0002]

2. Description of the Related Art Conventionally, as a basic configuration of an image processing apparatus of this kind, for example, the one shown in FIG. 8 is known. In FIG. 8, the image processing apparatus has a multi-processor configuration in order to realize high arithmetic performance, and a plurality of processor cores 101A and 101B are connected by a shared bus 102 so that data can be easily shared between the processors. Then, a DRAM controller 103 is connected to the bus 102.
, A DRAM 104 serving as a large-capacity main memory is connected. In addition, the processor cores 101A, 101B
In order to perform data transfer efficiently in parallel with the operation of
Bridges 105A and 105B are inserted between the shared bus 102 and the processor cores 101A and 101B, respectively.
6A, 106B, and the local bus 105A,
105B, small capacity but high speed local memory 107A,
107B, and the local memories 107A, 107B
And DMA (direct memory access) controllers A and B for controlling DMA data transfer between the DRAM 104 serving as a main memory.
Here, for example, the data widths of the external memory DRAM 104 and the shared bus 102 are both 8 bytes, and one word is 8 bytes.
Defined as bytes.

In the image processing apparatus having the above configuration, the following processing is performed. First, in one or a plurality of processors, as shown in FIG. 9, a continuous 18 bytes that are not always aligned with a word boundary are cut out from three words read from the DRAM 104, and a local 8-byte width is cut out. The operation of sequentially writing data in the memories 107A and 107B is repeated. Also similar, but in one or more processors, as shown in FIG.
From the two words read from the DRAM 104, eight consecutive bytes not necessarily aligned with a word boundary are cut out, and the local memory memory 107A having a width of eight bytes is extracted.
The operation of writing to 107B is repeated. However, some processors perform both processes, while others perform only the latter.

In such a process, when trying to read consecutive 18 bytes, data of a total of three words (24 bytes) is first read from three consecutive addresses of the DRAM 104, and then necessary data is read from the data. It is necessary to perform processing of cutting out only continuous 18 bytes. If an attempt is made to read from the DRAM 104 eight consecutive bytes that are not aligned with a word boundary, the DRAM 1
04 from two consecutive addresses for a total of two words (16
(Byte) data, and then a process of cutting out only necessary continuous 8 bytes from the data is required.

When such processing is performed by the image processing apparatus shown in FIG. 8, conventionally, as shown in FIG. 11, a clipping circuit 108A for performing the processing shown in FIG. 9 and a clipping circuit for performing the processing shown in FIG. 108B are separately prepared, a cutout circuit 108A for performing the processing shown in FIG. 9 is inserted between the local bus 106A and the local memory 107A, and a cutout circuit 108B for performing the processing shown in FIG. 10 is connected to the local bus 106B and the local memory. 107B.

[0006]

As described above,
In a conventional image processing apparatus that performs a plurality of different cutout processes on image data, since each cutout process is different, a circuit suitable for each cutout process is separately prepared, and each cutout process of the image data is performed. The processing was performed by a circuit corresponding to the processing. For this reason, a problem such as an increase in the size of the configuration has been caused.

Accordingly, the present invention has been made in view of the above, and it is an object of the present invention to reduce the size of the configuration by sharing a circuit for performing a plurality of different extraction processes for a plurality of processors. An object of the present invention is to provide an image processing apparatus that can be achieved.

[0008]

Means for Solving the Problems To achieve the above object, a first means for solving the problems is a processor core for controlling data transfer, a local memory connected to a local bus, and the processor core. A plurality of processors including a bridge connecting the local bus and a plurality of processors are connected to the shared bus in parallel via the respective bridges, and a main memory is connected to the shared bus via a memory controller for the main memory; In the image processing device that performs data transfer between the local memory and the main memory in parallel with the operation of the plurality of processor cores and processes image data, the image processing device is provided in a memory controller for the main memory, and Upon receiving the read data, a part of the data is cut out, and the cut out data is A first cutout circuit that outputs the data to the shared bus, provided in each of the bridges, receives data output from the first cutout circuit to the shared bus, and cuts out a part of the data; A second cutout circuit for giving the cutout data to the local memory via the local bus.

[0009] The second means is the first means,
The first cutout circuit is characterized in that a shifter for shifting input data by a predetermined shift amount comprises a funnel shifter in which a plurality of stages are cascaded.

The third means is characterized in that, in the second means, the funnel shifter cuts out continuous data which is not aligned with a boundary of the unit data from a plurality of continuous unit data.

According to a fourth aspect of the present invention, in the first, second or third aspect, the second cutout circuit comprises a byte conversion circuit having a shifter or a multiplexer.

[0012] The fifth means may be the one, two, three or four.
Means, wherein said shared bus is 8 bytes wide, at least one of said local buses is 9 bytes wide,
At least one of the local buses different from the byte-wide local bus has an 8-byte width.

[0013]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a diagram showing a configuration of an image processing apparatus according to an embodiment of the present invention. In FIG. 1, the image processing apparatus according to this embodiment has a basic configuration shown in FIG.
By adopting a multiprocessor system, the processor cores 1A and 1B, the shared bus 2, and the memory controller D
RAM controller 3, D functioning as main memory
RAM 4, bridges 5A, 5B, local buses 6A, 6
B, a local memory 7A, 7B, a DMA controller A, B, and a DRAM controller 3 serving as a main memory controller, a bridge 5A, and a 9-byte local bus 6A are different from those shown in FIG. Similarly, the two types of cutout processing described above are performed.
Note that such an image processing apparatus is configured as a one-chip IC, or the configuration excluding the DRAM 4 is a one-chip IC.
It consists of. The main memory is not limited to the DRAM 4, but may be a memory having another configuration.

The DRAM controller 3 functions as a memory controller serving as a main memory controller, and includes a funnel shifter 31 serving as a first cutout circuit. The funnel shifter 31, as shown in FIG.
A 4-byte shifter composed of eleven multiplexers (MUX) 32, a 2-byte shifter composed of nine multiplexers 33, and one composed of eight multiplexers
The funnel shifter 31 is composed of a byte shifter.
The processor cores 1A and 1B receive the data supplied from the 8-byte register 35 for receiving and holding the data supplied from the AM 4 and the data provided from the 8-byte register 36 for receiving and holding the data stored in the register 32. The shift is performed based on the shift amount instructed from, and the shifted data is given to and held in an 8-byte width register 37.

The bridge 5A includes a shifter 51 serving as a second extraction circuit for performing byte conversion of data transferred between the shared bus 2 and the local bus 6A. As shown in FIG. 4, the shifter 51 is a one-byte shifter composed of nine multiplexers. The shifter 51 includes a part of data held in an 8-byte width register 52 receiving data supplied from the shared bus 2, and The data held in the register 52, which receives the data held in the register 52, is input, the 8-byte data is converted into 9-byte data by byte conversion, and the converted data is transferred to the local bus 6.
A and 6B.

In such a configuration, as shown in FIG. 9, three words of data are read from the DRAM 4, and one of them is not necessarily aligned with a word boundary.
The flow of processing for cutting out 8 bytes will be described. First, DR
Three consecutive words (24 bytes) are read from the AM 4, necessary 18 bytes are cut out by the funnel shifter 31 built in the DRAM controller 3, and transferred to the bridge 5 A via the shared bus 2. Next, the data is converted into a 9-byte width by the bridge 5A and is sequentially transferred to the local memory 7A via the local bus 6A.

In the process of cutting out 18 bytes from 3 words (24 bytes), it is assumed that one word can be read from the DRAM 4 per cycle. Therefore, it takes three cycles to read data of three words (24 bytes). At this time, in the cutout processing, one word (8 bytes) is cut out when the first two-word data is read from the DRAM 4, and the next one-word data is read out from the DRAM 4
The next one word (byte) is cut out at the stage of reading from, and the last two bytes are cut out in the next cycle. By doing this, DRA
Since the rate at which data is read from M4 and the rate at which the cut-out result is output to the shared bus 2 coincide with three cycles per row, no extra buffer is required, which is convenient. Further, since the maximum number of bytes to be transferred per cycle is 8, the width of the shared bus 2 can be kept at 8, which is convenient.

However, the width of the local memory 7A for finally writing data is 9 bytes, and it is necessary to write 9 bytes per cycle. Therefore, if the byte is converted from 8 bytes to 9 bytes per cycle on the way, No. This conversion is performed by the shifter 51 of the bridge 5A. When the data of the first two words (16 bytes) in one row is transferred via the shared bus 2, the necessary 9 bytes are cut out of the data and output to the local bus 6A. Next, when the last word (valid data is only 2 bytes) is transferred, a total of 9 bytes including the 2 bytes and the 7 bytes remaining in the previous cycle are output to the local bus 6A.

Next, the details of the cut-out process will be described with reference to FIGS. 3 and 3 by taking as an example a case where 18 consecutive bytes from a position two bytes to the right of a word boundary are cut out and sequentially written in a 9-byte wide local memory 7A. This will be described with reference to FIG. The numbers in the squares in FIGS.
4 represents the byte position in the number 4, and
In this case, 18 bytes up to the ninth byte are written in the local memory 7A.

First, in a cycle 0 not shown in FIG. 3, one word (8 bytes) of data is read from the DRAM 4 and stored in the right-side 8-byte register 35 in the DRAM controller 3. As a result, the state of cycle 1 in FIG. 3 is obtained. Next, in cycle 1, the next one word is
4 and read it out to the right, 8-byte wide register 3.
Put in 5. At the same time, data is transferred from the right 8-byte width register 35 to the left 8-byte width register 36. As a result, the funnel shifter input becomes the cycle 2 in FIG.
The state shown in is shown.

In cycle 2, the shift amount in the funnel shifter 31 is set to 2. As a result, the output of the funnel shifter 31 becomes 8 bytes from the second to the ninth. Also, the next one word is read out from the DRAM 4 and put into the right-side 8-byte width register 35, and the right-side 8-byte width register 35 is shifted to the left side 8-byte width register 36.
Transfer data to As a result, the data output to the shared bus 2 and the funnel shifter input correspond to the cycle 3 shown in FIG.
State.

In cycle 3, the shift amount in funnel shifter 31 is set to 2. As a result, the output of the funnel shifter 31 becomes 8 bytes from No. 10 to No. 17. Further, the bridge 5A takes in data from the shared bus 2 and stores the data in the right-side 8-byte register 52 in the bridge. The operation of reading from the DRAM 4 and storing the read data in the register is the same in any cycle. As a result, the input of the funnel shifter 31, the shared bus 2, and the buffers (registers 52 and 53) in the bridge 5A enter the state of cycle 4 shown in FIG.

In cycle 4, the shift amount in funnel shifter 31 is set to 2. As a result, as shown in FIG. 4, six bytes from No. 18 to No. 23 are output from the funnel shifter 31. The bridge 5A fetches data from the shared bus 2 and fetches it into the right 8-byte width register 52, and at the same time, the right 8-byte width register 5
The data is transferred from 2 to the left-side 8-byte register 53. As a result, the state shown in cycle 5 of FIG. 4 is obtained.

In cycle 5, the shifter 51 in the bridge
Is selected on the left side by the multiplexer constituting. As a result, 9 bytes from No. 2 to No. 10 are output to the local bus 6A. In addition, data is taken in from the shared bus 2 and taken into the right-side 8-byte width register 52, and at the same time, data is transferred from the right-side 8-byte width register 52 to the left-side 8-byte width register 53. As a result, the state shown in cycle 6 of FIG. 4 is obtained.

In cycle 6, the right side is selected by the multiplexer in the bridge. This corresponds to performing an operation of shifting one byte to the left. As a result, 9 bytes from No. 11 to No. 19 are output to the local bus 6A.

As described above, consecutive 18 bytes which are not aligned with the word boundaries from No. 2 to No. 19 are sequentially written in the local memory 7A by 9 bytes. The throughput in this case is 3 cycles per row, which is D
This matches the rate at which one row of data is read from the RAM 4.

On the other hand, as shown in FIG. 10, eight consecutive bytes not necessarily aligned with a word boundary are cut out from two words read from the DRAM 4 and written into the local memory 7B having an 8-byte width. The clipping process is
Two words of data are sequentially read from the DRAM 4 and the read data is stored in the register 3 of the DRAM controller 3.
5. The data is sequentially stored and held in the register 36, the stored data is shifted by a predetermined amount by the funnel shifter 31, and 8-byte data is cut out. The cut-out 8-byte data is stored and held in the register 37, and the held data is stored in the shared bus 2. , The bridge 5B and the local bus 6B to the local memory 7B.

As described above, in the above embodiment, a processor made on the assumption that 18 consecutive bytes not always aligned on a word boundary is read, and a continuous 8 bytes not aligned on a word boundary are read. The second cutout circuit necessary for the former, while sharing as much as possible the circuit necessary for cutout between processors made on the assumption that reading is performed but not reading 18 consecutive bytes, Can be minimized. This makes it possible to reduce the size of the configuration.

Next, another embodiment of the present invention will be described.

The feature of this embodiment is shown in FIG.
A funnel shifter 62 having a configuration shown in FIG. 5 is employed in place of the funnel shifter 31 shown in FIG.
A multiplexer 67 shown in FIG.
The other configuration is the same as that of FIGS. 1 and 2.

The funnel shifter 62 includes four sets of shifters 63, 64, 65, each including eight multiplexers.
66.

Next, the same clipping processing as described above is performed.
This will be described with reference to FIGS. 6 and 7, the numbers in the squares represent the byte positions in the DRAM 4, in which 18 bytes from the second to the 19th are written in the local memory 7A. .

First, in a cycle 0 not shown in FIG. 6, one word (8 bytes) of data is read from the DRAM 4 and stored in the right-side 8-byte register 35 in the DRAM controller 3. As a result, the state becomes the cycle 1 shown in FIG.

Next, in cycle 1, the next one word is
The data is read from AM4, and is stored in an 8-byte width register 35 on the right side. At the same time, right-side 8-byte register 3
The data is transferred from 5 to the register 36 having a width of 8 bytes on the left side. As a result, the funnel shifter input enters the state shown in cycle 2 in FIG.

In cycle 2, the shift amount in the funnel shifter 62 is set to 2. As a result, the output of the funnel shifter 62 becomes 8 bytes from the second to the ninth. Further, the next one word is read from the DRAM 4 and put into the right-side 8-byte width register 35, and the right-side 8-byte width register 35 is shifted to the left side 8-byte width register 36.
Transfer data to As a result, the data output to the shared bus 2 and the input of the funnel shifter 62 enter the state of cycle 3 shown in FIG.

In cycle 3, the shift amount in the funnel shifter 62 is increased by one from the previous cycle and set to 3. Only the 10th byte is the funnel shifter 6
The leftmost input is selected by the third multiplexer from the left of the top stage in 2. As a result, the output of the funnel shifter 62 becomes 8 bytes from No. 10 to No. 17 in the format as shown in FIG. The bridge 5A takes in the data from the shared bus 2 and stores the data in the right-side 8-byte register 52 in the bridge 6A. The operation of reading from the DRAM 4 and storing the read data in the register is the same in any cycle. As a result, the funnel shifter input, the shared bus 2, and the buffer in the bridge enter the state of cycle 4 shown in FIG.

In cycle 4, the shift amount in the funnel shifter 62 is further increased by 1 and set to 4. Also,
With respect to the two bytes of Nos. 18 and 19, the leftmost input is selected by the third and fourth multiplexers from the left in the uppermost stage in the funnel shifter 62. As a result, six bytes from No. 18 to No. 23 are output from the funnel shifter 62 in a format as shown in FIG. The bridge 5A takes in data from the shared bus 2 and takes in the right-side 8-byte width register 52A, and simultaneously transfers the data from the right-side 8-byte width register 52 to the left-side 8-byte width register 53. As a result, the state shown in cycle 5 of FIG. 7 is obtained.

In cycle 5, the multiplexer 67 in the bridge 5A selects the left input. As a result, 9 bytes from No. 2 to No. 10 are output to the local bus 6A. In addition, data is taken in from the shared bus 2 and taken into the right-side 8-byte width register 52, and at the same time, data is transferred from the right-side 8-byte width register 52 to the left-side 8-byte width register 53. As a result, the state shown in cycle 6 of FIG. 7 is obtained.

In cycle 6, the right input is selected by the multiplexer 67 in the bridge 5A. As a result, 9 bytes from No. 11 to No. 19 are output to the local bus 6A.

As described above, consecutive 18 bytes that are not aligned with the word boundaries from No. 2 to No. 19 are sequentially written in the local memory 7A by 9 bytes. The throughput in this case is 3 cycles per row, which is D
It matches the rate at which one row is read from the RAM 4.

On the other hand, as shown in FIG. 10, eight consecutive bytes that are not necessarily aligned with word boundaries are cut out from two words read from the DRAM 4 and written into the local memory 7B having a width of eight bytes. The clipping process is
This is performed in the same manner as in the previous embodiment.

Comparing the respective configurations of the previous embodiment and this embodiment, the number of the multiplexers constituting the funnel shifter 31 and the shifter 51 of the bridge 5A shown in FIG. 2 is 37, whereas FIG. In the similar configuration shown, the number is reduced to 33. Thereby, in this embodiment, the control of the shift amount is simple and the control is easy in the above-described embodiment as compared with the above-described embodiment, whereas the control of the shift amount is plural in this embodiment. However, the configuration can be further reduced in size.

[0044]

As described above, according to the present invention, most of the hardware of the cutout circuit can be shared by a plurality of processors, and the circuit scale can be reduced as compared with the related art. As a result, the configuration can be reduced in size.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of an image processing apparatus according to an embodiment of the present invention.

FIG. 2 is a diagram showing a configuration of a DRAM controller and a bridge shown in FIG. 1;

FIG. 3 is a diagram illustrating operation timings in the image processing apparatus according to the embodiment of the present invention.

FIG. 4 is a diagram illustrating operation timings in the image processing apparatus according to the embodiment of the present invention.

FIG. 5 is a diagram illustrating a configuration of a DRAM controller and a bridge in an image processing apparatus according to another embodiment of the present invention.

FIG. 6 is a diagram showing operation timings in an image processing apparatus according to another embodiment of the present invention.

FIG. 7 is a diagram illustrating operation timings in an image processing apparatus according to another embodiment of the present invention.

FIG. 8 is a block diagram illustrating one configuration of a conventional image processing apparatus.

FIG. 9 is a diagram illustrating clipping of 18 bytes that are not aligned with word boundaries.

FIG. 10 is a diagram illustrating clipping of 8 bytes not aligned with a word boundary.

FIG. 11 is a block diagram illustrating a configuration of a conventional image processing apparatus including a cutout circuit.

[Explanation of symbols]

 1A, 1B Processor core 2 Shared bus 3 DRAM controller 4 DRAM 5A, 5B Bridge 6A, 6B Local bus 7A, 7B Local memory 31, 62 Funnel shifter 32, 33, 34, 51, 63-66 Shifter 35, 36, 37, 52 , 53 register 67 multiplexer

Claims (5)

[Claims] 1. A plurality of processors each including a processor core for controlling data transfer, a local memory connected to a local bus, and a bridge connecting the processor core and the local bus, via the respective bridges. Connected in parallel to a shared bus, a main memory is connected to the shared bus via a memory controller for the main memory, and data is transferred between the local memory and the main memory in parallel with the operation of the plurality of processor cores. In the image processing apparatus for processing image data, provided in a memory controller for the main memory,
A first cutout circuit that receives data read from the main memory, cuts out a part of the data, and outputs the cutout data to the shared bus; and a first cutout circuit provided in each of the bridges, And a second cutout circuit for receiving data output to the shared bus from the cutout circuit, cutting out a part of the data, and providing the cutout data to the local memory via the local bus. Image processing apparatus. 2. The image processing apparatus according to claim 1, wherein said first cutout circuit comprises a funnel shifter in which a plurality of stages of shifters for shifting input data by a predetermined shift amount are connected in cascade. 3. The image processing apparatus according to claim 2, wherein the funnel shifter cuts out continuous data that is not aligned with a boundary of the unit data from a plurality of continuous unit data. 4. The image processing apparatus according to claim 1, wherein said second cutout circuit comprises a byte conversion circuit having a shifter or a multiplexer. 5. The shared bus is 8 bytes wide, at least one of the local buses is 9 bytes wide, and at least one of the local buses different from the 9 byte wide local bus is 8 bytes wide. The image processing apparatus according to claim 1, 2, 3, or 4, wherein: