JP2000133594A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To efficiently remove catalytic elements from a crystal semiconductor film. SOLUTION: An Ni film 13 is formed to be brought into contact with a low rank crystal semiconductor thin film 12 constituted of an amorphous silicon film or a microcrystalline silicon film. The low rank crystal semiconductor thin film 2 is heated at 450-650 deg.C, so that a crystalline semiconductor thin film 14 in which Ni is dispersed can be formed. This is heated at 500-1,100 deg.C again so that amorphous components remaining in the semiconductor film 14 can be crystallized, and a crystalline semiconductor film 15 with high crystallinity can be formed. Then, the crystalline semiconductor film 15 is irradiated with laser beams or strong lights, so that Ni locally existing in a silicide state in the semiconductor film 15 can be turned into an easily dispersed state. Then, catalytic elements are selectively added to the crystalline semiconductor film 15, and a 15 group dopant region 15a can be formed. Then, this is heated at 500-850 deg.C, and the catalytic elements remaining in a region 15b to be gettered can be absorbed by the 15 group element dopant region 15a.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for manufacturing a semiconductor device using a crystalline semiconductor thin film. The semiconductor device of the present invention is not limited to a semiconductor element such as a thin film transistor or a MOS transistor, but also an electronic device having a semiconductor circuit composed of these insulated gate semiconductor elements, or an electro-optical display device (typically, an active matrix substrate). Also, electronic equipment such as a personal computer or a digital camera having a liquid crystal display device is included in the category.

[0002]

2. Description of the Related Art At present, a thin film transistor (TFT) is known as a semiconductor element using a semiconductor film. TF
Although T is used in various integrated circuits, it is particularly used as a switching element in a pixel portion of an active matrix liquid crystal display device. Further, in recent years, the mobility of the TFT has been increased, and the TFT is used as an element of a driver circuit for driving a pixel portion. For use in a driver circuit, a crystalline silicon film having higher mobility than an amorphous silicon film needs to be used as a semiconductor layer. This crystalline silicon film is called polycrystalline silicon, polysilicon, microcrystalline silicon, or the like.

Conventionally, to form a polycrystalline silicon film,
A method of forming a polycrystalline silicon film directly, and a method of forming an amorphous silicon film by a CVD method at a temperature of 600 to 1100 ° C.
A method of crystallizing polycrystalline silicon by performing heat treatment for 0 to 48 hours is known. The amorphous silicon film formed by the latter method has larger crystal grains, and the characteristics of the manufactured semiconductor element are better.

When a crystalline silicon film is formed on a glass substrate by the latter method, the upper limit of the crystallization process temperature is about 600 ° C., and the crystallization step requires a long time. Further, the temperature of 600 ° C. is close to the lowest temperature for crystallizing silicon, and if it is lower than 500 ° C., it is impossible to crystallize in a short time that is industrially profitable.

In order to shorten the crystallization time, a crystallization temperature may be raised to about 1000 ° C. by using a quartz substrate having a high strain point, but the quartz substrate is very expensive compared to a glass substrate. It is difficult to increase the area. For example, Corning 7 widely used in active-type liquid crystal display devices
059 glass has a glass strain point of 593 ° C. and 600 ° C.
Heating at the above temperature for several hours causes shrinkage or bending of the substrate. For this reason, there is a demand for a lower temperature and a shorter crystallization process so that a glass substrate such as Corning 7059 glass can be used.

[0006] The crystallization technique using an excimer laser is one of the techniques that has made it possible to reduce the temperature and time of the process.
Excimer laser light can give energy comparable to thermal annealing at about 1000 ° C. to a semiconductor film in a short time with almost no thermal influence on the substrate, and can form a highly crystalline semiconductor film. it can. However,
Since the energy distribution on the irradiation surface of the excimer laser varies, the crystallinity of the obtained crystallized semiconductor film also varies, and the device characteristics of each TFT also vary.

Accordingly, the present applicant has disclosed a technique in which the crystallization temperature is lowered while using a heat treatment as disclosed in Japanese Patent Laid-Open No. Hei 6-2320.
No. 59, JP-A-7-321339 and the like. The technique disclosed in the above publication is to obtain a crystallized silicon film by introducing a small amount of a catalytic element into an amorphous silicon film and then performing a heat treatment. The catalyst elements that promote crystallization include Ni, Fe, Co, Ru, Rh, Pd, O
An element selected from s, Ir, Pt, Cu, Au, and Ge is used.

In the crystallization of the above publication, heat treatment
The catalyst element diffuses into the amorphous silicon film, and crystallization of the amorphous silicon proceeds. Therefore, by using the crystallization technique disclosed in the above publication, crystalline silicon can be formed by heat treatment at 450 to 600 ° C. for 4 to 12 hours, and a glass substrate can be used.

[0009] However, the crystallization disclosed in the above publication has a problem that the catalytic element remains in the crystalline silicon film. Such a catalytic element impairs the semiconductor characteristics of the silicon film, and impairs the stability and reliability of the device to be manufactured.

Therefore, in order to solve this problem, the present applicant has studied a method of removing (gettering) a catalytic element from a crystalline silicon film. The first method is a method of performing heat treatment in an atmosphere containing a halogen element such as chlorine. In this method, the catalyst element in the film is vaporized as a halide.

The second method is a method in which phosphorus is selectively added to a crystalline silicon film to perform a heat treatment. By performing the heat treatment, the catalyst element diffuses into the phosphorus-added region and is captured in this region.

However, in the first method, the heat treatment temperature needs to be 800 ° C. or higher to obtain the effect of gettering, and a glass substrate cannot be used. On the other hand, in the second method, the heating temperature can be set to 600 ° C. or less,
There is a drawback that the processing time takes over ten hours.

[0013]

SUMMARY OF THE INVENTION An object of the present invention is to provide a method for efficiently performing a catalyst element removing step when using the catalyst element removing technique of the second method.

Another object of the present invention is to make it possible to form a high-performance semiconductor device on a glass substrate at a process temperature of 600 ° C. or lower.

[0015]

The reason why it takes time to remove the catalyst element is that the catalyst element in the crystalline silicon film does not exist in an atomic state at the time of completion of the crystallization, but most of the silicon is removed. It is considered that this is because it exists in a state combined with In order to remove the catalytic element from the crystalline silicon film, it is necessary to break this bond. For example, when nickel is used as a catalyst element, it is considered that nickel is present as nickel silicide.

To confirm this, a silicon film crystallized by using nickel was subjected to FPM (50% HF and 50% HF).
% Of H ₂ O ₂ 1: was about 30 second etch with 1 mixed etchant in). Since FPM removes nickel silicide in a short time, the presence of nickel silicide can be confirmed by the presence or absence of a hole by etching.

Holes were irregularly formed in the crystallized silicon film by the FPM process. As will be described later, this indicates that nickel is localized in the crystallized region, and silicide is formed by bonding with silicon at the localized portion.

Therefore, in the present invention, the main structure is to irradiate the crystallized semiconductor film with laser light or infrared light to break the bond between the catalyst element and the semiconductor and disperse the catalyst element in an atomic state. And With this configuration, the catalyst element is easily diffused in the semiconductor film, so that the temperature of the catalyst element removing step can be reduced and the time can be shortened.

The present invention for solving the above-mentioned problems includes an introduction step of introducing a catalytic element into a lower crystalline semiconductor film, a first heat treatment step of heating the lower crystalline semiconductor film, A second heat treatment step of heating the treated semiconductor; a heat treatment of the semiconductor film after the second heat treatment to remove a catalyst element in the film (gettering); And a light annealing step of irradiating the semiconductor film after the second heat treatment with a laser or strong light before the catalyst element removing step.

In the above introduction step, the lower crystalline semiconductor film is an amorphous semiconductor film having no crystallinity or a semiconductor thin film having crystallinity but having almost no crystal grains on the order of 100 nm or more. Refers to an amorphous semiconductor film and a microcrystalline semiconductor film. A microcrystalline semiconductor film is a semiconductor film in which microcrystals including crystal grains having a size of several nm to several tens of nm and amorphous are in a mixed phase.

More specifically, the lower crystalline semiconductor film is an amorphous silicon film, a microcrystalline silicon film, an amorphous germanium film, a microcrystalline germanium film, an amorphous Si ₁ Ge film.
_1-x (0 <x <1), and these semiconductor films are formed by a chemical vapor method such as a plasma CVD method or a low pressure CVD method.

The catalytic element is an element having a function of promoting crystallization of semiconductors, particularly silicon, and Ni, Fe, Co, Ru, an interstitial metal element with respect to silicon.
One or more elements selected from Rh, Pd, Os, Ir, Pt, Cu, Au, and Ge can be used.

The method for introducing the catalyst element is a method in which the catalyst element is added to the lower crystalline semiconductor film, and the film containing the catalyst element is formed in contact with the upper or lower surface of the lower crystalline semiconductor film.

In the former method, a method of forming a lower crystalline semiconductor film and then adding a catalytic element to the lower quality semiconductor film by an ion implantation method, a plasma doping method or the like can be used.

In the latter method, a film containing a catalyst element is formed by a deposition method such as a CVD method or a sputtering method, or a coating method of applying a solution containing a catalyst element using a spinner. Either the formation of the film containing the catalyst element or the formation of the lower crystalline semiconductor film may be performed first. If the lower crystalline semiconductor film is formed first, the film containing the catalyst element is in close contact with the upper surface of the semiconductor film. If the order of formation is reversed, the film containing the catalyst element is formed in close contact with the lower surface of the semiconductor film. The term “close contact” in the present invention means that not only the semiconductor film and the catalytic element are literally in close contact with each other, but also if the catalytic element can diffuse into the semiconductor film, an oxide film or a natural oxide film having a thickness of about 10 nm exists between the films. Also includes the configuration that is.

For example, in the introduction step, Ni is used as a catalyst element.
Is used, a Ni film or a Ni silicide film may be formed by a deposition method.

When the coating method is used, nickel bromide, nickel acetate, nickel oxalate, nickel carbonate,
Nickel salts such as nickel chloride, nickel iodide, nickel nitrate and nickel sulfate are used as solutes, and water, alcohol, acid,
A solution using ammonia as a solvent or a solution using nickel as a solute and using a solvent selected from benzene, toluene, xylene, carbon tetrachloride, chloroform, and ether can be used. Alternatively, even if nickel is not completely dissolved, a material such as an emulsion in which nickel is dispersed in a medium may be used.

Alternatively, nickel alone or a nickel compound may be dispersed in a solution for forming an oxide film to form an oxide film containing nickel. As such a solution, OCD (Ohka Diffusio) of Tokyo Ohka Kogyo Co., Ltd.
n Source) can be used. With the use of this OCD solution, a silicon oxide film can be easily formed by applying it on the surface to be formed and baking it at about 200 ° C. The same applies to other catalyst elements.

As a method for introducing the catalyst element, the coating method can most easily adjust the concentration of the catalyst element in the lower crystalline semiconductor film as compared with the doping method or the method of forming a Ni film by sputtering. Also, the process is simplified.

The first heat treatment step is a step for diffusing the catalytic element into the lower crystalline semiconductor film. When the lower crystalline semiconductor film into which the catalytic element is introduced is heat-treated, the catalytic element immediately enters the semiconductor film and diffuses. The catalyst element diffuses and exerts a catalytic action on the molecular chains in the amorphous state to crystallize the lower crystalline semiconductor film.

Regarding the catalytic action, the applicant of the present invention disclosed in Japanese Patent Application Laid-Open Nos.
No. 44104, and the like. Since the catalyst element is an interstitial atom with respect to silicon, silicon in contact with the catalyst element is combined with the catalyst element to form silicide. Then, it was found that silicide reacts with the amorphous silicon bond, and crystallization proceeds. this is,
This is because the interatomic distance between the catalyst element and silicon is very close to the interatomic distance of single crystal silicon, and the Ni-Si distance is closest to the single crystal Si-Si distance, and is about 0.6% shorter.

When a reaction for crystallizing an amorphous silicon film using Ni as a catalyst element is modeled, Si [a] -Ni (silicide) + Si [b] -Si [c] (amorphous) → Si It can be represented by a reaction formula of [a] -Si [b] (crystalline) + Ni-Si [c] (silicide).

In the above reaction formula, [a],
The indices [b] and [c] indicate Si atom positions.

In the above reaction formula, since the Ni atom in the silicide replaces the Si [b] atom of silicon in the amorphous portion, the distance between Si [a] and Si [b] is almost the same as that of the single crystal. It has become. In addition, it shows that Ni grows crystal while diffusing in the lower crystalline semiconductor film. At the time when the crystallization reaction is completed, Ni becomes Si
In this state, it is localized at the end of diffusion (or the tip of crystal growth). That is, NiSi
_{In the} silicide state represented by _x , it is irregularly distributed in the film after crystallization. As described above, the existence of this silicide is obtained by subjecting the film after crystallization to FPM treatment.
It can be confirmed as a hole.

It is known that in order to provide energy for causing the crystallization reaction to proceed, heating at 450 ° C. or more in a heating furnace is sufficient. The upper limit of the heating temperature is 650 ° C. This is to prevent crystallization of the amorphous semiconductor film from progressing in a portion that does not react with the catalytic element. If crystallization occurs in a portion that does not react with the catalyst element, the catalyst element cannot diffuse into that portion, so that the crystal grains cannot be made large and the particle size varies.

The second heating step aims at improving and improving the crystallinity of the crystalline semiconductor film crystallized by the catalytic element.

The crystalline semiconductor film formed by the first heat treatment has a defect in a crystal grain and an amorphous portion remains. Therefore, in the present invention, the amorphous portion is crystallized,
Further, heat treatment is performed again to eliminate defects in the grains. This heating temperature is higher than that of the first heat treatment, specifically 500 to 1100 ° C., more preferably 600 ° C.
１1100 ° C. Needless to say, the upper limit of the actual temperature is determined by the heat resistant temperature of the substrate.

In this step, an excimer laser beam can be applied instead of the heat treatment. However, as described above, since the excimer laser has inevitable irradiation energy variation, there is a possibility that the crystallization of the amorphous portion may vary. In particular, in this state, the distribution of the amorphous portion varies from one film to another, so that not only the characteristics between elements in one semiconductor device vary, but also the characteristics between semiconductor devices may vary. .

Therefore, after the crystallization step, it is desired to always perform a heat treatment before irradiating the excimer laser beam to crystallize the amorphous portion and reduce defects. Therefore, when an excimer laser is used in the next optical annealing step, it is important to perform a process for improving crystallinity by heat treatment.

As a heating method equivalent to the heating treatment in the heating furnace, a wavelength of 0.6 to 4 μm, more preferably 0.1 to 4 μm is used.
The RTA method of irradiating infrared light having a peak at 8 to 1.4 μm for several tens to several hundreds of seconds is known. Since the absorption coefficient of infrared light is high, the semiconductor film is 800
Heat to ~ 1100 ° C in a short time. However, since the RTA method has a longer irradiation time than the excimer laser beam, heat is easily absorbed by the substrate, and when a glass substrate is used, attention must be paid to the occurrence of warpage.

It is an object of the present invention to remove (gettering) a catalytic element localized in a crystallized semiconductor film. In the present invention, a Group 15 element is used for gettering the catalytic element. Here, the group 15 elements are P, A
s, N, Sb, and Bi. P has the highest gettering ability, followed by Sb.

In the present invention, the catalyst is removed by selectively adding a Group 15 element to a crystalline semiconductor film to form a region (film) containing a Group 15 element, followed by heat treatment.
There are a method in which a catalyst element is absorbed in a region containing a Group V element, and a method in which a film containing a Group 15 element is formed in contact with a crystalline semiconductor film and heat treatment is performed to include a Group 15 element.

In the former method, 1 is added to the crystalline semiconductor film.
In order to form a region containing a group V element, a gas-phase method such as a plasma doping method or an ion implantation method can be used as in the method of introducing a catalytic element into a lower crystalline semiconductor film.

In the latter method, the film containing a Group 15 element can be a silicon film or a silicon oxide film containing a Group 15 element by a deposition method such as a CVD method or a sputtering method or a coating method. Typically, a microcrystalline silicon film containing P for forming an NI junction and a PSG film are given.

The concentration of the Group 15 element in the region containing the Group 15 element and the film containing the Group 15 element is 10 times the concentration of the catalytic element remaining in the semiconductor film. In the crystallization method of the present invention, since the catalytic element remains on the order of 10 ¹⁸ to 10 ²⁰ atoms / cm ³ , the group 15 element concentration is 1 × 10 ¹⁹ to 1 ×.
It is set to 10 ²¹ atoms / cm ³ .

To remove (getter) the catalytic element, a heat treatment is performed. By the heat treatment, the catalyst element diffuses into the region to which the Group 15 element is added or the film containing the Group 15 element, where it is combined with the Group 15 element and inactivated. Therefore, this catalyst removal step can be regarded as a step of causing the region to which the Group 15 element is added or the film containing the Group 15 element to absorb (getter) the catalyst element.

Also, it has been found that by adding not only the Group 15 element but also the Group 13 element to the region or film where the catalytic element is absorbed, a higher removal effect can be obtained than that of the Group 15 element alone. . In this case, the group 13 element concentration is set to 1.3 to 2 times the group 15 element concentration. Group 13 elements are B, Al, Ga, In, and Ti.

According to the catalyst removing step of the present invention, the concentration of the catalyst element is 5 × 10 ¹⁷ atoms / cm ³ or less (preferably 2 × 10 ¹⁷ atoms / cm ^3).
A crystalline semiconductor region reduced to ¹⁷ atoms / cm ³ or less can be obtained.

At present, SIMS (mass secondary ion)
Analysis) lower limit of detection 2 × 10¹⁷atoms / cm^ThreeAbout
Therefore, it is not possible to determine the concentration below that. Only
However, by performing the removal step described in this specification,
At least 1 × 10¹⁴~ 1 × 10 ^Fifteenatoms / cm^ThreeTo the extent,
It is assumed that the catalytic element is reduced.

In the present invention, the temperature of the catalyst removing step is reduced.
Before this heat treatment, the crystalline semiconductor film is irradiated with laser light or strong light in order to shorten the time. By this light irradiation (light annealing), the catalytic element localized in the crystalline semiconductor film is easily diffused.

[0051] As described above, the catalytic element as NiSi _x, remain attached to the semiconductor molecules, although distributed semiconductor film, by the energy of light annealing, Ni-S
Since the i-bond is broken and the catalyst element is changed to an atomic state or the Ni-Si bond energy is reduced, the remaining catalyst element is in a state where it is easily diffused in the crystalline semiconductor film.

The energy required for diffusing the catalytic element can be reduced by the photo-annealing of the present invention, so that the catalytic element can be diffused by heating at 500 ° C. or more, and the processing time can be reduced. It can be shorter. Further, the effect of reducing the area of the catalyst element or the area of the film can be expected, and the area where the element can be formed can be enlarged. The upper limit of the heating temperature in the catalyst removal step is a temperature at which the group 15 element in the region where the catalyst element is absorbed or the film does not move is about 850 ° C.

Further, in the light annealing step, a portion to be irradiated with light may be irradiated to a portion of the semiconductor film which will be a semiconductor layer forming a semiconductor element, and at least a region (channel) where a depletion layer of this semiconductor layer is formed. Formation region).

The light source used for light annealing is 400 nm
Excimer lasers having the following wavelengths can be used. For example, a KrF excimer laser (wavelength 248n)
m), XeCl excimer laser (wavelength 308 nm),
XeF excimer laser (wavelengths 351 and 353 nm),
An ArF excimer laser (wavelength 193 nm) or the like can be used. A XeF excimer laser having a wavelength of 483 nm or an ultraviolet lamp can be used. Alternatively, an infrared lamp such as a xenon lamp or an arc lamp can be used. Excimer laser light of a pulse oscillation method can be used.

Embodiments of the present invention will be described with reference to FIGS.

Embodiment 1 This embodiment will be described with reference to FIG.

As shown in FIG. 1A, a substrate 10 is prepared, and a base film 11 is formed on the surface of the substrate 10. The substrate 10 includes an insulating substrate such as a glass substrate, a quartz substrate, and a ceramic substrate, a single crystal silicon substrate, a stainless substrate, a Cu substrate, a high melting point metal material such as Ta, W, Mo, Ti, and Cr, or an alloy thereof ( For example, a conductive substrate such as a substrate made of a nitrogen-based alloy) can be used.

The base film 11 has a function of preventing impurities from diffusing from the substrate into the semiconductor device, a function of increasing the adhesion of the semiconductor film and the metal film formed on the substrate 10 and a function of preventing peeling. As the base film 11, an inorganic insulating film such as a silicon oxide film, a silicon nitride film, or a silicon nitride oxide film formed by a CVD method or the like can be used. For example, when a silicon substrate is used, its surface can be oxidized by thermal oxidation to form a base film. When a heat-resistant substrate such as a quartz substrate or a stainless steel substrate is used, an amorphous silicon film may be formed, and the silicon film may be thermally oxidized.

Further, as the base film 11, tungsten,
A laminated film in which a high-melting-point metal film such as chromium or tantalum or a film having high conductivity such as an aluminum nitride film is formed as a lower layer and the above-described inorganic insulating film is formed as an upper layer may be used. In this case, since the heat generated in the semiconductor device is radiated from the film under the base film 11, the operation of the semiconductor device can be stabilized.

On the underlying film 11, plasma CVD, reduced pressure C
Lower crystalline semiconductor thin film 1 by vapor phase method such as VD method and thermal CVD
2 is formed. Here, an amorphous silicon film is formed to a thickness of 10 to 150 nm by a low-pressure CVD method. Plasma C
The VD method has higher productivity than the low pressure CVD method,
The VD method requires a long time for film formation, but has the advantage that a denser film can be formed than the plasma CVD method. (Fig. 1 (A))

Next, a catalytic element is introduced into the lower crystalline semiconductor film 12. Here, a method of forming a film 13 containing a catalytic element on the surface of the lower crystalline semiconductor film 12 is used. For example, in a spinner, a Ni acetate solution is applied, and this state is maintained for several minutes. By drying using a spinner, a Ni film is formed as the film 13. The concentration of nickel in the solution is 1 ppm or more, preferably 10 ppm
Above is practical. (FIG. 1 (B))

Then, in a heating furnace, the lower crystalline semiconductor film 12 into which the catalytic element has been introduced is heat-treated to form a crystalline semiconductor thin film 14. The heat treatment conditions are such that the nitrogen atmosphere is an inert atmosphere such as nitrogen, the temperature is 450 ° C. to 650 ° C., and the time is 4 to 12 hours. In the present embodiment, since the nickel element contacts the entire surface of the lower crystalline semiconductor film, the nickel diffusion direction film diffuses from the lower crystalline semiconductor film surface in the direction of the underlying film, that is, in a direction substantially perpendicular to the substrate surface, and Progress. (Fig. 1 (C))

Semiconductor film 1 having crystallinity by heat treatment
After forming 4, a heat treatment is performed at 500 to 1100 ° C. to crystallize the amorphous component remaining in the semiconductor film 14 and to reduce defects in crystal grains to improve crystallinity.
A crystalline semiconductor film 15 with increased crystallinity is formed.

Next, the crystalline semiconductor film 15 is irradiated with laser light or strong light, so that nickel localized in the silicide state in the semiconductor film 15 is easily diffused. (Fig. 1 (D))

Then, the crystalline semiconductor film 15 is selectively
Group elements are selectively added. First, a mask insulating film 16 is formed on the semiconductor film 15. As the mask insulating film 16,
A resist, silicon oxide, or the like can be used. Here 1
A silicon oxide film having a thickness of 00 nm is formed and patterned to form a mask insulating film 16. Then, a group 15 element is selectively added by a plasma doping method, a coating method, or the like to form a group 15 added region 15 a in the semiconductor film 15. The region 15b to which the group 15 element is not added is referred to as a gettered region for convenience. (FIG. 1 (E))

The group 15 element concentration in the region 15a is
10 times the concentration of the catalytic element in the rolling region 15b. This implementation
In the method of the embodiment, 10 is set in the area 15b.¹⁹-10²⁰atoms /
cm^ThreeSince the catalytic element remains in the order,
The concentration of group 15 elements is 1 × 10 ²⁰~ 1 × 10^{twenty one}atoms / cm^Three
And

Next, by heating at 500 ° C. to 850 ° C., the catalyst element remaining in the gettering region 15b diffuses into the group 15 element addition region 15a and is absorbed there. By this heat treatment, the concentration of the catalytic element (Ni) in the region 15b is reduced to 2 × 10 ¹⁷ atoms / cm ³ or less. (FIG. 1 (F))

Then, after the catalyst removing step, the region 15b is patterned into an island shape to form an island-shaped semiconductor layer 17. A semiconductor element such as a TFT may be manufactured using the semiconductor layer 17. (Fig. 1 (G))

In the present invention, since the gettered region 15b is optically annealed before the catalyst removing step, the time required for the removing step can be shortened, and the area of the group 15 element region 15a can be reduced, and the element formation A possible region (corresponding to the gettered region 15b in this case) can be enlarged.

Embodiment 2 This embodiment will be described with reference to FIG. This embodiment is a modification of the catalyst introduction method of the first embodiment. In addition, a method for forming a gate insulating film after formation of a semiconductor layer is described. The rest is the same as in the first embodiment.

In this embodiment, since there is a thermal oxidation step,
As the substrate 20, a quartz substrate or a high-melting-point metal substrate such as tungsten among the above-described substrates is prepared, and a base film 21 is formed on the surface of the substrate 20.

Next, an amorphous silicon film is formed as the lower crystalline semiconductor film 22 by a low pressure CVD method. The thickness of the amorphous silicon film is 20 to 100 nm (preferably 40 nm).
７５75 nm). Here, the film thickness is 65 nm. Note that a plasma CVD method may be used as long as film quality equivalent to that of an amorphous silicon film formed by a low-pressure CVD method can be obtained.

Next, a mask insulating film 23 is formed on the lower crystalline semiconductor film 22 made of an amorphous silicon film. An opening 23a is provided in the mask insulating film 23 by patterning. The opening 23a defines a region to which the catalyst element is added. As the mask insulating film 23, a resist or a silicon oxide film can be used. Here, a 120-nm-thick silicon oxide film is used.

Next, a solution prepared by dissolving nickel acetate containing 5 to 10 ppm by weight of nickel in ethanol is applied by a spin coating method and dried, and a Ni film is used as a mask insulating film as a film 24 containing a catalytic element. 23. In this state, nickel comes into contact with the lower crystalline semiconductor film 22 at the opening 23 a provided in the mask insulating film 23. (Fig. 2 (A))

Next, after dehydrating at 450 ° C. for about 1 hour in a heating furnace, the catalyst element is diffused from the film 24 containing the catalyst element to the lower crystalline semiconductor film 22. In an active atmosphere, a hydrogen atmosphere, or an oxygen atmosphere, heat treatment is performed at a temperature of 450 to 650 ° C. for a heating time of 4 to 24 hours. By heating, the catalyst element diffuses in the lower crystalline semiconductor film 22 as schematically shown by arrows,
Allow to crystallize. Here, heat treatment is performed at 570 ° C. for 8 hours to form the crystalline semiconductor film 25 in which the catalytic element is diffused. (FIG. 2 (B))

In this catalyst diffusion step, a crystal region (referred to as a lateral growth region) 25b which proceeds preferentially from nickel silicide reacted in the region 22a to which the catalyst is added and has grown substantially parallel to the substrate surface of the substrate 20 Is formed. Since the individual crystal grains are aggregated in a relatively uniform state in the lateral growth region 25b, there is an advantage that the overall crystallinity is excellent. Note that the region 25a is a region into which a catalytic element has been introduced, and is unsuitable for an element because the catalytic element is crystallized but remains at a high concentration. The non-crystallized region 25c is a region where the catalytic element has not diffused, and is a region where crystallization has not progressed. Therefore, only the lateral growth region 25b is suitable for forming a high-performance device.

After the catalyst element diffusion step is completed, the mask insulating film 23 is removed, and the mask
A heat treatment is performed at 0 ° C. to form a crystalline semiconductor film 26 with improved crystallinity. (Fig. 2 (C))

According to TEM (transmission electron microscopy) observation, in the crystalline semiconductor film, the crystal grains in the lateral growth region 26b are rod-shaped or flat rod-shaped, and the orientations of these crystal grains are almost aligned. Almost all of these crystal grains are roughly $ 11
The crystal orientation is 0 °, and the directions of the <100> axis and the <111> axis are the same for each crystal grain, and the <110> axis slightly fluctuates by about 2 ° between the crystal grains. As described above, since the orientation of the crystal axis is uniform in the lateral growth region 26b, the bonding of atoms at the crystal grain boundaries becomes smooth, and the number of dangling bonds becomes small.

On the other hand, in the conventional polycrystalline silicon, since the direction of the crystal axis is irregular for each crystal grain, there are many atoms that cannot be bonded at the grain boundary. In this point, the crystal structures of the lateral growth region 26b of the present embodiment and the conventional polycrystalline silicon film are completely different. In the lateral growth region 26b, almost all of the atoms are not broken at the crystal grain boundaries and the two crystal grains are bonded to each other with extremely high consistency. This makes it very difficult to create trap levels caused by such factors.

Next, by irradiating a laser beam or an intense light, the catalytic element remaining in the lateral growth region 26b, here NiSi
Nickel localized in the bonding state of _x is easily diffused.

Next, as in the first embodiment, a mask insulating film 27 made of a silicon oxide film is formed. Lateral growth area 26
b is included in the gettered region 26d. Then, P (phosphorus) is added as a Group 15 element to form a Group 15 element added region 26c. Since the concentration of nickel remaining in the lateral growth region 26b is about 1/10 of that in the first embodiment, that is, 10 ¹⁸ to 10 ¹⁹ atoms / cm ³ , the region 2
The phosphorus concentration of 6c is 1 × 10 ¹⁹ to 1 × 10 ²⁰ atoms / cm ³
And

Since the Group 15 element is added to the underlying film 21 and the substrate 20 through the region 26c film, the underlying film 2
Only one or a specific region in the substrate 22 contains a high concentration of a Group 15 element. However, such a group 15 element is TF
There is no adverse effect on the T characteristics.

After forming the additional region 26c,
A heat treatment is performed at 00 to 850 ° C. for 2 to 24 hours to diffuse the catalyst element in the gettering region 26 d into the group 15 element-added region 26 c and to absorb it into the region 26 c (the diffusion direction is indicated by an arrow). . Thus the catalyst is 5 × 10 ¹⁷ atom
A lateral growth region reduced to s / cm ³ or less, 1 × 10 ¹⁴ to 1 × 10 ¹⁵ atoms / cm ³ is obtained. (FIG. 2 (D))

After the catalyst element removing step is completed, the mask insulating film 23 is removed, and then the island-shaped semiconductor layer 28 is formed using only the gettered region 26d.

Next, plasma CVD or low pressure CVD
An insulating film 30 made of silicon nitride oxide is formed to cover silicon oxide, silicon nitride, and the semiconductor layer 28 by a method. The insulating film 30 forms a gate insulating film, and has a thickness of 50 to 150 nm. (Figure 2
(E))

After the insulating film 30 is formed, a heat treatment is performed in an oxidizing atmosphere at 800 to 1100 ° C. (preferably 950 to 1050 ° C.) in a heating furnace to heat the interface between the semiconductor layer 28 and the insulating film 30. An oxide film 31 is formed.

The oxidizing atmosphere is a dry O ₂ atmosphere,
The atmosphere may be a wet O ₂ atmosphere or an atmosphere containing a halogen element (typically, hydrogen chloride). When a halogen element is included, gettering effect of nickel by the halogen element can be expected if the insulating film on the semiconductor layer is thin.

The optimum temperature and time of the thermal oxidation step may be determined in consideration of the thickness of the thermal oxide film and the throughput. Here, in a heating furnace, a dry oxygen atmosphere,
A heat treatment is performed at 950 ° C. for 30 minutes to form a 50 nm thermal oxide film 31. In this thermal oxidation step, the semiconductor layer 28 having a thickness of 25 nm is oxidized, and the thickness of the semiconductor layer 32 finally becomes 4 nm.
0 nm. (FIG. 2 (F))

It is important that the thermal oxidation process is performed after the formation of the insulating film 30 as described above. Since the Group 15 element for removing the catalyst is added to the base film 21, the element is diffused into the atmosphere of the thermal oxidation process by forming the insulating film 30 and is added again to the semiconductor layer (phosphorus (Also referred to as doping).

Further, by thermally oxidizing the interface between the semiconductor layer 32 and the insulating film 30, the interface level is greatly reduced, so that the interface characteristics can be significantly improved. Further, the film quality of the insulating film 30 formed by the CVD method is improved, and a reduction in light leakage current can be expected by thinning the semiconductor layer. Further, intragranular defects in the semiconductor layer are also reduced.

This is a semiconductor layer 28 made of crystalline silicon.
It is considered that excess silicon atoms generated when is thermally oxidized move to defects in the crystal grains and greatly contribute to the generation of Si—Si bonds. This concept is known as the reason that there are few defects in the crystal grains of the high-temperature polysilicon film.

Further, by performing a heat treatment at a temperature higher than the crystallization temperature (typically 700 to 1100 ° C.), the semiconductor layer 32 and the base film 21 are fixed, and the adhesion is increased, so that a defect is caused. It can be assumed that the model disappears.

The difference in thermal expansion coefficient between the crystalline semiconductor film and the underlying silicon oxide film is nearly 10 times. Therefore, when the crystalline silicon film is transformed from the amorphous silicon film to the crystalline silicon film, a very large stress is applied to the crystalline silicon film when the crystalline silicon film is cooled, and the adhesiveness between the underlying film and the crystalline silicon film is reduced. Is small. It is considered that this causes defects such as stacking faults and dislocations to occur easily.

That is, since the crystalline silicon is in a state of being easily moved, it is considered that a tensile stress easily causes defects such as stacking faults and dislocations. Such a state remains after the catalyst removing step is performed.

Then, a thermal oxidation step is performed to form the base film 2.
1 and the semiconductor layer 32, the semiconductor layer 3
The generation of defects in the crystal grains in 2 is suppressed.

That is, the semiconductor layer 32 is formed by the thermal oxidation process.
Are adhered to the base 21 to enhance the adhesion to the substrate, and at the same time, the defects in the crystal grains can be compensated by the excess silicon atoms.

Using the semiconductor layer 32 obtained in the above steps, the insulating film 30 and the thermal oxide film 31 as a gate insulating film,
An FT can be made.

[Embodiment 3] The group 15 element is composed of N
It is an element that imparts the conductivity type of the mold. Therefore, in the present embodiment, the N-type source / drain region is used for a region where the catalyst element is absorbed.

First, according to the steps described in the first and second embodiments, the steps up to the laser / strong light irradiation step are performed, and the obtained crystalline semiconductor film is patterned to form the semiconductor layer 42. Note that reference numeral 40 denotes a substrate, and reference numeral 41 denotes a base film 41. (FIG. 3 (A))

The laser or intense light irradiation for facilitating the diffusion of the catalytic element may be performed after the semiconductor layer 42 is formed. In the present embodiment, since the purpose is to reduce the catalytic element in the channel formation region, the timing of the irradiation step does not matter as long as the portion to be the channel formation region is irradiated with laser light / strong light.

Next, the gate insulating film 43 and the gate electrode 44
To form The gate electrode 44 is formed of a material that can withstand a heat treatment temperature in a later catalyst removing step. For example, P-added silicon, Ta, W, Mo, Ti, Cr, or other high melting point metal alloys or alloys thereof (for example, alloys of high melting point metals, alloys of high melting point metal and nitrogen, etc. Can be.

Next, using the gate electrode 44 as a mask, a Group 15 element is added to the semiconductor layer 42 to form an N-type source region 45, an N-type drain region 46, and a channel formation region 47.
Are formed in a self-aligned manner. Here, P and As are used as Group 15 elements, and the added amount is 1 × 10 ¹⁹ to 1 × 10 ²¹ atom.
s / cm ³ . You. (FIG. 3 (B))

Next, heat treatment is performed at 500 to 850 ° C., more preferably 550 to 650 ° C., for 4 to 8 hours to remove the catalyst element in the channel formation region 47 from the source / drain region 4.
Diffusion to 5, 46. Source / drain regions 45, 4
The catalyst element reaching 6 combines with the group 15 element. For example, when the catalyst element is Ni and the group 15 element is P, NiP ₁ , NiP ₂ Ni _2.
It exists in a connected state such as This coupling state is very stable and hardly affects the operation of the TFT.
(FIG. 3 (C))

By this heat treatment, the concentration of the catalyst element in the channel forming region 47 is set to 1 × 10 ¹⁴ to 1 × 10 ¹⁵ atoms / cm.
It can be reduced to ³ . In addition, by activating the Group 15 element added to the source / drain regions 45 and 46, the resistance of the source / drain regions 45 and 46 can be reduced.

After the catalyst removing step is completed, an interlayer insulating film 49, a source electrode 50, and a drain electrode 51 are formed according to a known method to complete a TFT. (FIG. 3
(D))

In the first and second embodiments, apart from the element forming portion,
It is necessary to form the group 15 additive region in the semiconductor film. However, in this embodiment, the source / drain regions 45 and 46 are used as the group 15 additive region, that is, since the group 15 additive region is formed in the element forming portion, the Integration can be achieved.

[0106]

Embodiment An embodiment of the present invention will be described with reference to FIGS.

[Embodiment 1] This embodiment is an example in which the present invention is applied to a TFT, in which an N-channel TFT and a P-channel TFT are formed on the same substrate, and a CMOS circuit is manufactured. 4 to 6 are used for the description.

FIG. 4 shows a schematic top view of a CMOS circuit. 4, reference numeral 111 denotes a gate wiring, 108 denotes a semiconductor layer of an N-channel TFT, and 109 denotes a P-channel TF.
T is a semiconductor layer. 161 and 162 are the semiconductor layers 10
8, 109 and contact portions of the source wiring, 16
Reference numerals 3 and 164 denote contact portions between the semiconductor layers 108 and 109 and the drain wiring. Reference numeral 165 denotes a contact portion (gate contact portion) between the gate wiring 111 and the extraction wiring.

A manufacturing process of the TFT will be described with reference to FIGS. 5 and 6, the left side shows a cross-sectional view of an N-channel TFT, and the right side shows a cross-sectional view of a P-channel TFT. The cross-sectional view of each TFT is shown by a chain line AA ′ in FIG.
This corresponds to a cross-sectional view cut along a chain line BB ′.

First, a 1737 glass substrate manufactured by Cornings is used as the substrate 100. A 300-nm-thick silicon oxide film is formed as a base film 101 over a glass substrate 100.

When the substrate having the insulating surface is thus prepared, an amorphous silicon film 102 is formed as a lower crystalline semiconductor film by using a low pressure CVD method with disilane as a source gas. The thickness of the amorphous silicon film 102 is 55 nm.
Next, a mask insulating film 103 made of a 120-nm-thick silicon oxide film is formed over the amorphous silicon film 102. An opening 103 is formed in the mask insulating film 103 by patterning.
a and 103b are provided.

Next, a solution prepared by dissolving nickel acetate containing 10 ppm by weight of nickel in ethanol is applied by a spin coater and dried to form a Ni film 104. The Ni film 104 is formed in the openings 103 a and 103 b provided in the mask insulating film 103.
Contact 2 Note that since the amorphous silicon film 102 has poor infiltration property, U
By V irradiation etc. When an oxide film of about several nm is formed, it is easy to form the Ni film 104 in a state where the Ni film 104 is in contact with the openings 103a and 103b. (FIG. 5 (A))

When the state shown in FIG. 5A is obtained,
After performing heat treatment at 450 ° C. for about 1 hour in a heating furnace to release hydrogen from the amorphous silicon film 102,
Heat treatment is performed in a nitrogen atmosphere at 550 ° C. for 8 hours. Ni
Ni diffuses from the film 104 into the amorphous silicon film 102, crystallization proceeds, and the lateral growth regions 106a, 106b
Is formed. (FIG. 5
(B))

When the crystallization step is completed,
The crystalline silicon film 106 is heat-treated for 4 hours to crystallize an amorphous portion, thereby forming a crystalline silicon film 107 with improved crystallinity. Next, the crystalline silicon film 107 is irradiated with a KrF excimer laser beam so that Ni localized in the film is easily diffused. The excimer laser is processed by an optical system into a linear laser beam having a width of 0.5 mm and a length of 12 cm, and the substrate is scanned in one direction relative to the linear laser beam so that the entire surface of the substrate is irradiated with the laser beam. I do. Alternatively, a laser beam is applied on a side of 5 to 10
Irradiation can also be performed by processing into a rectangular shape of about cm.
(FIG. 5 (C))

Next, the crystalline silicon film 107 is patterned into an island shape to form semiconductor layers 108 and 109.
Note that the above excimer laser irradiation is applied to the semiconductor layer 10.
It may be after the formation of 8,109. (FIG. 5 (D))

Next, SiH _{4 was formed} by plasma CVD.
And N ₂ O as source gas, silicon nitride oxide film 110
Is formed to a thickness of 120 nm. Next, a tantalum film (Ta film) having a thickness of 40 nm is formed over the silicon nitride oxide film 110 by a sputtering device and patterned. Then, the patterned Ta film is anodized to form an anodized film 112 made of tantalum oxide. The Ta film remaining without being anodized functions as the gate wiring 111. The above excimer laser beam irradiation is performed using Ta.
It may be performed before the film is formed. In this embodiment, at least a region to be a channel formation region may be irradiated with laser light. (FIG. 5E)

Next, a resist mask 115 is formed, and the silicon nitride oxide film 110 is patterned to form a gate insulating film 116. The gate insulating film 116 is an anodic oxide film 1
11 and has a shape extending outside, and the portion extending outside defines a low concentration impurity region. (FIG. 5 (F))

Next, after removing the resist mask 115, a Group 15 element is added to the semiconductor layers 108 and 109 to form source / drain regions of the N-channel TFT. P is added to the doping gas using phosphine diluted to 5% with hydrogen. First, doping is performed at a high acceleration and at a low dose so that phosphorus is added to the semiconductor layer through the gate insulating film 116. Next, doping is performed at a low acceleration and at a high dose to form the gate insulating film 116. Functioned as a mask. The first condition was an acceleration voltage of 80 kV,
The set dose is 6 × 10 ¹³ atoms / cm ² , the second condition is an acceleration voltage of 10 kV, and the set dose is 5 × 10 ¹⁴ atoms / cm 2
^{Assume 2} .

In two N-type impurity doping steps, the N ⁺ -type regions 121, 122, 131,
132, and N ^- type regions 124, 125, 134, 13
5 are formed. Here, the N ⁺ type region 1 of the semiconductor layer 108
Reference numerals 21 and 122 serve as source / drain regions, and N ⁻ -type regions 124 and 125 serve as low-concentration impurity regions.
3 becomes a channel formation region. (FIG. 6 (A))

By performing heat treatment in this state, it is possible to cause the N ⁺ -type regions 121, 122, 131, and 132 to absorb nickel in the regions 123 and 133 to which phosphorus has not been added. P-channel type TFT
After adding B (boron), which is a Group 13 element, to the semiconductor layer 109, a catalyst element removing step is performed.

Therefore, after the N-channel type TFT is covered with the resist mask 140, B is added to the semiconductor layer 109. Diborane diluted to 5% with hydrogen is used as a doping gas, and P ⁺ -type source / drain regions 141 and 14 are used.
2. P ^- type low-concentration impurity regions 144 and 145 and a channel formation region 143 are formed in a self-aligned manner. The formation of the P ⁺ type region and the P ⁻ type region can be controlled by controlling the acceleration voltage and the dose in the same manner as in the N-channel TFT. (FIG. 6
(B))

P-channel source / drain region 14
In order to cause 1, 142 to absorb the catalytic element, the concentration of boron ions is set to 1.
Make it about 3 to 2 times.

After forming the source / drain regions, heat treatment is performed at 500 ° C. for 2 hours in an electric furnace. By this heat treatment, Ni intentionally added for crystallization of the amorphous silicon film is removed from the respective source / source regions from the channel formation regions 123 and 143 as schematically shown by arrows in FIG. Drain regions 211, 212, 271, 2
Spread to 72. As a result, the channel formation region 123,
143 and the low concentration impurity regions 124, 125, 144,
145, while the source / drain regions 121, 122, 141,
The Ni concentration in 142 depends on the channel formation regions 123 and 143.
Higher than. (FIG. 6 (C))

Further, simultaneously with gettering by this heat treatment, the source / drain regions 211, 212, 271, 2
72, and low concentration impurity regions 214, 215, 274,
The phosphorus and boron added to 275 are activated.

Next, an interlayer insulating film 1 made of a silicon oxide film
Form 50. After forming a contact hole in the interlayer insulating film 150, a laminated film made of titanium / aluminum / titanium is formed as an electrode material, and patterned to form a wiring 15.
1 to 153 are formed. Here, an N-channel TFT and a P-channel TFT are connected by a wiring 153 to form a CMOS circuit. Gate wiring 111 not shown
Are also formed. Finally, a hydrogenation treatment is performed at 350 ° C. for about 2 hours in a hydrogen atmosphere to obtain TF
A hydrogen termination process is performed on the entire T. (FIG. 6 (D))

[Embodiment 2] This embodiment will be described with reference to FIGS. This embodiment is an example in which a CMOS circuit is formed by an inverted staggered TFT.

First, a 1737 glass substrate 200 manufactured by Cornings is prepared. A base film 201 made of a 120-nm-thick silicon oxide film is formed on the surface of the substrate 200. next,
A conductive film for forming the gate wiring 202 is formed. Here, three layers of tantalum nitride (TaN _x ) / Ta / TaN _x were formed by a sputtering method. The thickness of each TaN _x film is 50 n
m, and the thickness of the Ta film is 250 nm. Then, the three-layer film is patterned to form the gate wiring 202. Although the gate wiring 202 is separated in FIG.
And one CMOS circuit (see FIG. 4).

Next, a gate insulating film 203 is formed so as to cover the gate wiring 202. Here, a 20-nm-thick silicon nitride film / 100-nm-thick silicon nitride oxide film is formed. Since a gate wiring made of a Ta material easily causes occlusion of oxygen and hydrogen, a dense silicon nitride film is formed as a lower layer to cover the gate wiring in order to prevent the occlusion.

Next, an amorphous silicon film 204 is formed on the gate insulating film 203 to a thickness of 55 nm by a low pressure CVD method. Then, a nickel acetate aqueous solution containing 10 ppm by weight of nickel is applied by a spin coater using a spinner and dried to form a nickel film 205.
(FIG. 7 (A))

Next, after performing a dehydration step at 500 ° C. for 1 hour in a heating furnace, a heating process is performed in a heating furnace at 550 ° C. for 4 hours in a nitrogen atmosphere to form a crystalline silicon film 206.
Thereafter, similarly to the first embodiment, a heat treatment is performed at 600 ° C. in a heating furnace to crystallize the remaining amorphous component and to reduce intragranular defects to form a crystalline silicon film 206 with improved crystallinity. I do. Then, the crystalline silicon film 206 is irradiated with an excimer laser beam so that Ni in the crystalline silicon film 206 is easily diffused. (FIG. 7 (B))

The crystalline silicon film 206 is patterned to form semiconductor layers 207 and 208 of an N-channel TFT and a P-channel TFT. In this state, an excimer laser beam may be irradiated. (FIG. 7 (C))

Next, in contact with the semiconductor layers 207 and 208,
Channel stoppers 209 and 210 made of a silicon oxide film
To form A microcrystalline silicon film 211 is formed over the entire surface of the substrate 200 by a plasma CVD method using monosilane and hydrogen as source gases by a plasma CVD method. The microcrystalline silicon film 211 is formed without adding a dopant such as phosphorus or boron. (FIG. 7 (D))

Next, P, which is a Group 15 element, is added to the microcrystalline silicon film 211 by a plasma doping method to form an N-type microcrystalline silicon film 212 to which P is added. The doping condition is such that the P concentration is N which remains in the semiconductor layers 207 and 208.
1 × 10 ¹⁹ to 1 × 10 ²² atoms / cm
^{Assume 3} . (FIG. 7E)

Although the microcrystalline silicon film 211 shows N-type conductivity, the microcrystalline silicon film 212 to which P (phosphorus) is added is added.
Is formed, the conductivity is further increased, and the film can be used as a film for absorbing the catalyst element.

Therefore, by performing the heat treatment in this state,
Although the catalytic element in the semiconductor layers 207 and 208 can be absorbed, in the present invention, a catalytic element removing step is performed after forming the N layer of the P-channel TFT.

Therefore, a resist mask covering the N-channel type TFT is formed, and a group 13 element B is added to form a resist mask.
A type microcrystalline silicon film 213 is formed. The concentration of boron in the microcrystalline silicon film 213 is set to 1.3 to 2 times that of phosphorus. (FIG. 8A)

Next, in a heating furnace at a nitrogen atmosphere at 550 ° C.
Heat treatment for 4 hours. Ni in the semiconductor layers 207 and 208
Is absorbed by the N-type microcrystalline silicon film 212 and the P-type microcrystalline silicon film 213. Region 207 where depletion layer is induced
C and 208C are not directly in contact with the microcrystalline silicon films 212 and 213, but the distance for diffusing Ni can be as short as about several μm.
The concentration of the catalyst element in the microcrystalline silicon film 212,
13 can be diffused. Further, by this heat treatment, P and B added to the microcrystalline silicon films 212 and 213 are activated. (FIG. 8 (B))

Next, the microcrystalline silicon films 212 and 213 are divided by dry etching using CF ₄ gas, and the source / drain regions 207S and 207 of the semiconductor layer 207 are separated.
N-type microcrystalline silicon films 212S and 212D are formed in contact with D to form an NI junction. At the same time, the semiconductor layer 208
In contact with the source / drain regions 208S and 208D of
Type microcrystalline silicon films 213S and 213D are formed, and PI
Form a bond. (FIG. 8 (C))

Next, an interlayer insulating film 2 made of a silicon oxide film
Form 30. After forming a contact hole in the interlayer insulation 230, a laminated film made of titanium / aluminum / titanium is formed as an electrode material, and patterned to form a wiring 231.
To 233 are formed. Here, N
Channel type TFT and P channel type TFT are connected and C
A MOS circuit is formed. Further, a gate wiring 1 (not shown)
Eleven extraction wirings are also formed. Finally, hydrogenation is performed at 350 ° C. for about 2 hours in a hydrogen atmosphere,
The whole hydrogen termination processing is performed. (FIG. 8 (D))

[Embodiment 3] In this embodiment, the TFT described in Embodiment 1 is applied to an active matrix substrate. The active matrix substrate of this embodiment is used for a flat-type electro-optical device such as a liquid crystal display device and an EL display device.

This embodiment will be described with reference to FIGS. 9 to 11, the same reference numerals indicate the same components. FIG. 9 is a schematic perspective view of the active matrix substrate of this embodiment. The active matrix substrate is a glass substrate 40
A pixel portion, a scan line driver circuit 402, and a signal line driver circuit 403 are formed over the pixel portion 0. Scan line drive circuit 40
2. The signal line driving circuit 403 is connected to the pixel portion by a scanning line 502 and a signal line 503, respectively, and these driving circuits 402 and 403 are mainly constituted by CMOS circuits.

The scanning lines 502 are formed for each row of the pixel portion 401, and the signal lines 503 are formed for each column. In the vicinity of the intersection of the scanning line 502 and the signal line, each wiring 502, 5
A pixel TFT 500 connected to the pixel TFT 03 is formed.
The pixel TFT 500 includes a pixel electrode 505 and a storage capacitor 521.
Is connected.

First, according to the manufacturing process of the TFT of the first embodiment, the N-channel type TFs of the driving circuit circuits 402 and 403 are formed.
The T and P channel type TFT and the pixel TFT 500 in the pixel portion are completed.

FIG. 10A is a top view of a pixel portion, and is a top view of substantially one pixel. FIG. 10B shows the driving circuit 40.
FIG. 2 is a top view of a CMOS circuit forming the second and third circuits 403; FIG. 11 is a cross-sectional view of the active matrix substrate, which is a cross-sectional view of a pixel portion and a CMOS circuit. A cross-sectional view of the pixel portion is a cross-sectional view taken along a chain line AA ′ in FIG.
A cross-sectional view of the OS circuit is a cross-sectional view along a dashed line BB ′ in FIG.

The pixel TFT 500 in the pixel portion is an N-channel type TFT. The semiconductor layer 501 has a “U” shape (horse-shoe shape). A scan line 502 which is a first layer wiring
Intersect with the semiconductor layer 501 with the gate insulating film 510 interposed therebetween.

The semiconductor layer 501 includes N ⁺ -type regions 511 to 511.
513, two channel formation regions 514 and 515, and low-concentration impurity regions (N ⁻ -type regions) 516 to 519 are formed. N ⁺ type regions 511 and 512 are source / drain regions.

On the other hand, in a CMOS circuit, one gate wiring 601 crosses two semiconductor layers 602 and 603 with a gate insulating film 610 interposed therebetween. In the semiconductor layer 602,
Source / drain regions (N ⁺ type regions) 611, 612,
A channel formation region 613 and low-concentration impurity regions (N ⁻ -type regions) 614 and 615 are formed. Semiconductor layer 603
Include source / drain regions (P ⁺ type regions) 621 and 6
22, a channel forming region 623, a low concentration impurity region (P
^- type region) 624 and 625 are formed.

After forming source / drain regions in the semiconductor layers 501, 602 and 603, the interlayer insulating film 4 is formed on the entire surface of the substrate.
30 are formed. The signal line 503 and the drain electrode 50 are formed on the interlayer insulating film 430 as second-layer wiring and electrodes.
4. Source electrodes 631 and 632 and a drain electrode 633 are formed.

The scanning lines 502 and the signal lines 503 are orthogonal to each other with the interlayer insulating film 430 interposed therebetween as shown in FIG. The drain electrode 504 is an extraction electrode for connecting the drain region 512 to the pixel electrode 505, and is a lower electrode of the storage capacitor 521. In order to increase the capacitance of the storage capacitor 521, the drain electrode 504 is made as wide as possible as long as the opening is not reduced.

As shown in FIG. 10B, the drain electrode 633 of the CMOS circuit is connected to the gate wiring 650 of another TFT.
(The first layer wiring).

A first flattening film 440 is formed on the second layer wiring / electrode. In this embodiment, a stacked film of silicon nitride (50 nm) / silicon oxide (25 nm) / acryl (1 μm) is used as the first planarization film 440. Acrylic, polyimide, benzocyclobutene (B
Since the organic resin film such as CB) is a solution-coated insulating film that can be formed by a spin coating method, a film thickness of about 1 μm can be formed with high throughput, and a good flat surface can be obtained. Furthermore, since the organic resin film has a lower dielectric constant than silicon nitride or silicon oxide, the parasitic capacitance can be reduced.

Next, on the first flattening film 440, as a third layer wiring, a source wiring 641, a drain electrode 642, a drain wiring 643, and a black mask 520 made of a light-shielding conductive film such as titanium or chrome. Are formed. As shown in FIG. 10A, the black mask 520 is integrated in the pixel portion and is formed so as to overlap with the periphery of the pixel electrode 505 and cover all portions that do not contribute to display. In addition, it is as shown by the dotted line in FIG.
The potential of the black mask 520 is fixed at a predetermined value.

These third layer wirings 641, 642, 5
Prior to the formation of the trench 20, the first flattening film 440 is etched to leave only the lowermost silicon nitride film.
30 is formed on the drain electrode 504.

In the recess 530, the drain electrode 504 and the black mask 520 face each other with only the silicon nitride film interposed therebetween.
4. A storage capacitor 521 is formed using the black mask 520 as an electrode and a silicon nitride film as a dielectric. Silicon nitride has a high relative dielectric constant, and a larger capacitance can be ensured by reducing the film thickness.

A second planarizing film 450 is formed on the third-layer wirings 641, 642, and 520. The second flattening film 450 is formed of 1.5 μm thick acrylic. Although the portion where the storage capacitor 521 is formed has a large step,
Such a step can be sufficiently flattened.

A contact hole is formed in the first flattening film 440 and the second flattening film 450, and a pixel electrode 505 made of a transparent conductive film is formed. Metal oxides or alloys of metal oxides such as ITO, tin oxide, zinc oxide, alloys of indium oxide and zinc oxide are used for the transparent conductive film. Thus, an active matrix substrate is completed.

When the active matrix substrate of this embodiment is used for a liquid crystal display device, an alignment film (not shown) is formed to cover the entire surface of the substrate. Rubbing treatment is applied to the alignment film if necessary

Note that when a conductive film having high reflectance, typically aluminum or a material containing aluminum as a main component, is used for the pixel electrode 505, an active matrix substrate for a reflective AMLCD can be manufactured.

Although the pixel TFT 500 has a double gate structure in this embodiment, it may have a single gate structure or a multi-gate structure such as a triple gate structure. In addition, the inverted staggered TF shown in Embodiment 1
It can also be formed of T. The structure of the active matrix substrate of this embodiment is not limited to the structure of this embodiment. Since the feature of the present invention lies in the configuration of the gate wiring,
Other configurations may be determined by the practitioner as appropriate.

Embodiment 4 In this embodiment, as an example of the electro-optical device using the active substrate shown in Embodiment 3, an active matrix type liquid crystal display device (AML)
A description will be given of an example in which a CD is described.

FIG. 12 shows the appearance of the AMLCD of this embodiment. In FIG. 12A, the same reference numerals as those in FIG. 9 denote the same components. The active matrix substrate is a glass substrate 40
A pixel portion, a scan line driver circuit 402, and a signal line driver circuit 403 are formed over the pixel.

Active matrix substrate and counter substrate 70
0 is pasted. Liquid crystal is sealed in the gap between these substrates. Note that external terminals are formed in the active matrix substrate in a manufacturing process of the TFT, and a portion where the external terminals are formed does not face the counter substrate 700. An FPC (flexible print circuit) 710 is connected to the external terminal, and an external signal and power are transmitted to the circuits 401 to 403 via the FPC 710.

The opposing substrate 700 has an I
A transparent conductive film such as a TO film is formed. The transparent conductive film is a counter electrode to the pixel electrode in the pixel portion, and the pixel electrode,
The liquid crystal material is driven by the electric field formed between the opposing electrodes. Further, an alignment film and a color filter are formed on the counter substrate 700 if necessary.

IC chips 711 and 712 are mounted on the active matrix substrate of this embodiment using the surface on which the FPC 710 is mounted. These IC chips are configured by forming circuits such as a video signal processing circuit, a timing pulse generating circuit, a gamma correction circuit, a memory circuit, and an arithmetic circuit on a silicon substrate. In FIG. 12A, two IC chips are attached, but one or three or more IC chips may be attached.

Alternatively, the configuration shown in FIG. 12B is also possible. 12B, the same components as those in FIG. 12A are denoted by the same reference numerals. Here, FIG. 12A illustrates an example in which signal processing performed by an IC chip is performed by a logic circuit 720 formed using TFTs over the same substrate. In this case, the logic circuit 720 is also the driving circuit 4
It is configured on the basis of a CMOS circuit as in the case of 02 and 403.

In this embodiment, a configuration in which a black mask is provided on an active matrix substrate (BMon TFT) is employed. In addition, a configuration in which a black mask is provided on the opposite side may be employed.

A color display may be performed using a color filter, or a liquid crystal may be driven in an ECB (electric field controlled birefringence) mode, a GH (guest host) mode, or the like.
It is good also as composition not using a color filter. Also,
As described in JP-A-8-15686, a configuration using a microlens array may be adopted.

Embodiment 5 The TF shown in Embodiments 1 and 2
T can be applied to various other electro-optical devices and semiconductor circuits other than AMLCD.

As an electro-optical device other than AMLCD, E
Examples include an L (electroluminescence) display device and an image sensor.

As the semiconductor circuit, an arithmetic processing circuit such as a microprocessor composed of an IC chip, and a high-frequency module (MMIC) for handling input / output signals of a portable device are used.
Etc.).

As described above, the present invention can be applied to all semiconductor devices functioning with a circuit constituted by an insulating gate type TFT.

[Embodiment 6] A CMOS circuit and a pixel matrix circuit formed by carrying out the present invention are used for various electro-optical devices (active matrix liquid crystal display, active matrix EL display, active matrix EC display). be able to. That is, the invention of the present application can be applied to all electronic devices incorporating such electro-optical devices as display media.

Examples of such electronic devices include a video camera, a digital camera, a projector (rear or front type), a head mounted display (goggle type display), a car navigation, a personal computer, and a portable information terminal (mobile computer, mobile phone). Or an electronic book). Examples of those are shown in FIGS.

FIG. 13A shows a personal computer, which includes a main body 2001, an image input section 2002, and a display device 2.
003 and a keyboard 2004. The present invention can be applied to the image input unit 2002, the display device 2003, and other signal control circuits.

FIG. 13B shows a video camera, which includes a main body 2101, a display device 2102, an audio input unit 2103, an operation switch 2104, a battery 2105, and an image receiving unit 21.
06. The present invention can be applied to the display device 2102, the audio input unit 2103, and other signal control circuits.

FIG. 13C shows a mobile computer (mobile computer), which comprises a main body 2201, a camera section 2202, an image receiving section 2203, operation switches 2204, and a display device 2205. The present invention relates to a display device 22.
05 and other signal control circuits.

FIG. 13D shows a goggle type display, which includes a main body 2301, a display device 2302, and an arm 23.
03. The present invention can be applied to the display device 2302 and other signal control circuits.

FIG. 13E shows a player using a recording medium (hereinafter, referred to as a recording medium) on which a program is recorded, and includes a main body 2401, a display device 2402, and a speaker unit 24.
03, a recording medium 2404, and operation switches 2405. This device uses a DVD (Digi
(tal Versatile Disc), CDs, etc., to enjoy music, movies, games and the Internet. The present invention can be applied to the display device 2402 and other signal control circuits.

FIG. 13F shows a digital camera, which includes a main body 2501, a display device 2502, an eyepiece section 2503, operation switches 2504, and an image receiving section (not shown). The present invention can be applied to the display device 2502 and other signal control circuits.

FIG. 14A shows a front type projector, which comprises a display device 2601 and a screen 2602. The present invention can be applied to a display device and other signal control circuits.

FIG. 14B shows a rear type projector, which includes a main body 2701, a display device 2702, and a mirror 270.
3. It is composed of a screen 2704. The present invention can be applied to a display device and other signal control circuits.

FIG. 14C is a diagram showing an example of the structure of the display devices 2601 and 2702 in FIGS. 14A and 14B. Display devices 2601, 27
02 denotes a light source optical system 2801, mirrors 2802 and 280
4 to 2806, dichroic mirror 2803, prism 2807, liquid crystal display device 2808, retardation plate 280
9, the projection optical system 2810. Projection optical system 28
Reference numeral 10 denotes an optical system including a projection lens. In the present embodiment, an example of a three-plate type is shown, but there is no particular limitation, and for example, a single-plate type may be used. Further, the practitioner may appropriately provide an optical system such as an optical lens, a film having a polarizing function, a film for adjusting a phase difference, or an IR film in the optical path indicated by the arrow in FIG. Good.

FIG. 14D is a diagram showing an example of the structure of the light source optical system 2801 in FIG. In this embodiment, the light source optical system 2801 includes a reflector 2811, light sources 2812, 2813, 2814, a polarization conversion element 2815, and a condenser lens 2816.
Note that the light source optical system shown in FIG. 14D is an example and is not particularly limited. For example, a practitioner may appropriately provide an optical system such as an optical lens, a film having a polarizing function, a film for adjusting a phase difference, and an IR film in the light source optical system.

As described above, the applicable range of the present invention is extremely wide, and the present invention can be applied to electronic devices in various fields. Further, the electronic apparatus of the present embodiment can be realized by using a configuration composed of any combination of the first to fifth embodiments.

As described above, the applicable range of the present invention is extremely wide, and the present invention can be applied to electronic devices in various fields. In addition, the present invention can be used for an electronic bulletin board, a display for advertising, and the like.

[0186]

According to the present invention, when a technique for crystallizing a semiconductor film using a catalytic element or using a technique for enhancing crystallinity is used, the catalytic element is irradiated with laser light / strong light before the catalytic element removing step. This makes it possible to efficiently perform the catalyst element removing step for making the state easy to diffuse. In addition, since the process temperature of the catalyst element removing step can be performed at a temperature lower than 600 ° C., a glass substrate can be sufficiently used.

[Brief description of the drawings]

FIG. 1 is a view showing a manufacturing process of Embodiment 1.

FIG. 2 is a cross-sectional view illustrating a manufacturing process of Embodiment 2.

FIG. 3 is a cross-sectional view illustrating a manufacturing process of Embodiment 3.

FIG. 4 is a plan view of the CMOS circuit according to the first embodiment.

FIG. 5 is a cross-sectional view illustrating a manufacturing process of a TFT.

FIG. 6 is a cross-sectional view illustrating a manufacturing process of a TFT.

FIG. 7 is a cross-sectional view illustrating a manufacturing process of a TFT of Example 2.

FIG. 8 is a cross-sectional view illustrating a manufacturing process of a TFT.

FIG. 9 is a perspective view of an active matrix substrate according to a third embodiment.

FIG. 10 is a top view of a pixel matrix circuit and a CMOS circuit.

FIG. 11 is a cross-sectional view of an active matrix substrate.

FIG. 12 is an external perspective view of a liquid crystal display device according to a fourth embodiment.

FIG. 13 is a configuration diagram of an electronic device according to a sixth embodiment.

FIG. 14 is a configuration diagram of a projector according to a sixth embodiment.

[Explanation of symbols]

 Reference Signs List 100 substrate 102 amorphous silicon film 104 Ni film 106 crystalline silicon film 108, 109 semiconductor layer

Claims (30)

[Claims] A step A of introducing a catalytic element into the lower crystalline semiconductor film; a step B of heating the lower crystalline semiconductor film to diffuse the catalytic element into the semiconductor film; Heating the diffused semiconductor film to increase the crystallinity; step C of selectively adding a Group 15 element to the semiconductor film having the increased crystallinity; After heat treatment,
A step E of causing the region to which the group element is added to absorb the catalyst element, and before the step E, a step F of irradiating the semiconductor film having increased crystallinity with laser light or strong light. A method for manufacturing a semiconductor device, comprising: 2. A method for manufacturing a semiconductor device having at least one thin film transistor having a source region, a drain region, and a channel formation region formed of a semiconductor film, wherein a step A of introducing a catalytic element into the lower crystalline semiconductor film is performed. A step B of heating the lower crystalline semiconductor film to diffuse a catalyst element into the semiconductor film; and a step C of heating the semiconductor film in which the catalyst element is diffused to increase crystallinity. At least a region where the source region and the drain region are formed with respect to the semiconductor film having enhanced crystallinity;
A step D of adding a group V element;
A step E of causing the region to which the group element is added to absorb the catalyst element, and before the E, a step F of irradiating the crystalline semiconductor film having increased crystallinity with laser light or strong light. A method for manufacturing a semiconductor device, comprising: 3. The method according to claim 2, wherein the at least one thin film transistor is a P-channel type, and in the step D, at least the P-channel type TF
The region where the source and drain regions of T are formed is 1
A method for manufacturing a semiconductor device, comprising adding a Group 5 element and a Group 13 element. 4. The method for manufacturing a semiconductor device according to claim 1, wherein the heating temperature is from 450 to 650 ° C. 5. The method for manufacturing a semiconductor device according to claim 1, wherein the heating temperature is higher than the heating temperature in the step B in the step C according to claim 1. 6. The method for manufacturing a semiconductor device according to claim 1, wherein the heating temperature is in the range of 500 to 1100 ° C. 7. A step A of introducing a catalytic element into the lower crystalline semiconductor film, a step B of heating the lower crystalline semiconductor film to form a crystalline semiconductor film having an amorphous portion, A step C of heating the crystalline semiconductor film to increase the crystallinity; a step D of selectively adding a Group 15 element to the crystalline semiconductor film having the increased crystallinity; Heating the crystalline semiconductor film to absorb the catalytic element in the region to which the group 15 is added. Before the step E, a laser is applied to the crystalline semiconductor film having increased crystallinity. A method for manufacturing a semiconductor device, comprising a step F of irradiating light or strong light. 8. A method for manufacturing a semiconductor device having at least one thin film transistor having a source region, a drain region, and a channel formation region formed of a semiconductor film, wherein a step A of introducing a catalytic element into the lower crystalline semiconductor film A step B of heating the lower crystalline semiconductor film to form a crystalline semiconductor film having an amorphous portion, and a step C of heating the crystalline semiconductor film to increase crystallinity. A step D of adding a Group 15 element to at least a region where the source region and the drain region are formed with respect to the crystalline semiconductor film having improved crystallinity; A heat treatment to cause the region to which the group XV element is added to absorb the catalyst element, and before the step E, a laser is applied to the crystalline semiconductor film having increased crystallinity. -A method for manufacturing a semiconductor device, comprising a step F of irradiating light or strong light. 9. The method according to claim 8, wherein at least one thin film transistor is a P-channel type, and in the step D, at least the P-channel type TF
A method for manufacturing a semiconductor device, comprising adding a Group 15 element and a Group 13 element to a region to be a source region and a drain region of T. 10. The method for manufacturing a semiconductor device according to claim 7, wherein the heating temperature is 450 to 650 ° C. 11. The method for manufacturing a semiconductor device according to claim 7, wherein the heating temperature is higher than the heating temperature in the step B in the step C according to claim 7. 12. The method for manufacturing a semiconductor device according to claim 7, wherein a heating temperature is 500 to 1100 ° C. in the step C according to claim 7. 13. The method for manufacturing a semiconductor device according to claim 1, wherein the heating temperature is 450 to 850 ° C. 14. A step A of introducing a catalytic element into the lower crystalline semiconductor film; a step B of heating the lower crystalline semiconductor film to diffuse the catalytic element into the semiconductor film; Heating the diffused semiconductor film to increase the crystallinity; step D of forming a film containing a Group 15 element in contact with the crystallized semiconductor film; and increasing the crystallinity. The semiconductor film is subjected to heat treatment,
A step E of causing the film containing the group element to absorb the catalyst element, and before the step E, a step F of irradiating the semiconductor film having increased crystallinity with laser light or strong light. A method for manufacturing a semiconductor device. 15. A method for manufacturing a semiconductor device having at least one thin film transistor having a source region, a drain region, and a channel formation region formed of a semiconductor film, wherein a step A of introducing a catalytic element into the lower crystalline semiconductor film is performed. A step B of heating the lower crystalline semiconductor film to diffuse a catalyst element into the semiconductor film; and a step C of heating the semiconductor film in which the catalyst element is diffused to increase crystallinity. A step D of forming a film containing a Group 15 element in contact with at least a region where the source region and the drain region are formed, with respect to the semiconductor film having improved crystallinity; The film is subjected to heat treatment,
A step E of causing the film containing the group element to absorb the catalyst element, and before the step E, a step F of irradiating the semiconductor film having increased crystallinity with laser light or strong light. A method for manufacturing a semiconductor device. 16. The method according to claim 15, wherein at least one thin film transistor is a P-channel type, and in the step D, at least the P-channel type TF
In contact with the source and drain regions of T,
A method for manufacturing a semiconductor device, comprising forming a film containing a Group 15 element and a Group 13 element. 17. The method for manufacturing a semiconductor device according to claim 14, wherein the heating temperature is from 450 to 650 ° C. 18. The method for manufacturing a semiconductor device according to claim 14, wherein the heating temperature is higher than that of the step B in the step C according to claim 14. 19. The method for manufacturing a semiconductor device according to claim 14, wherein the heating temperature is in the range of 500 to 1100 ° C. 20. A step A of introducing a catalytic element into the lower crystalline semiconductor film, and a B step of heating the lower crystalline semiconductor film to form a crystalline semiconductor film having an amorphous portion. A step C of heating the crystalline semiconductor film to increase the crystallinity; a step D of forming a film containing a Group 15 element in contact with the crystalline semiconductor film having the increased crystallinity; Heat-treating the enhanced crystalline semiconductor film to cause the film containing the group 15 element to absorb the catalyst element, and the crystalline semiconductor having enhanced crystallinity before the step E A method for manufacturing a semiconductor device, comprising a step F of irradiating a film with laser light or strong light. 21. A method for manufacturing a semiconductor device having at least one thin film transistor having a source region, a drain region, and a channel formation region formed of a semiconductor film, wherein a step A of introducing a catalytic element into the lower crystalline semiconductor film A step B of heating the lower crystalline semiconductor film to form a crystalline semiconductor film having an amorphous portion, and a step C of heating the crystalline semiconductor film to increase crystallinity. Forming a film containing a Group XV element in contact with at least a region where the source region and the drain region are formed in the crystalline semiconductor film having improved crystallinity;
And heating the crystalline semiconductor film having increased crystallinity to cause the film containing the Group 15 element to absorb the catalyst element. A step F of irradiating a laser light or an intense light to the crystalline semiconductor film in which the height is increased. 22. The method according to claim 21, wherein at least one thin film transistor is a P-channel type, and in the step D, at least the P-channel type TF
In contact with the source and drain regions of T,
A method for manufacturing a semiconductor device, comprising forming a film containing a Group 15 element and a Group 13 element. 23. The method for manufacturing a semiconductor device according to claim 20, wherein the heating temperature is 450 to 650 ° C. 24. The method for manufacturing a semiconductor device according to claim 20, wherein a heating temperature is higher than a heating temperature in the step B in the step C according to claim 20. 25. The method for manufacturing a semiconductor device according to claim 20, wherein the heating temperature is in the range of 450 to 1100 ° C. 26. The method for manufacturing a semiconductor device according to claim 14, wherein the heating temperature is 500 to 850 ° C. 27. The process A according to claim 1, wherein the lower crystalline semiconductor film is an amorphous silicon film formed by a low pressure CVD method. A method for manufacturing a semiconductor device. 28. The process A according to claim 1, wherein the catalyst element is Ni, Fe, Co, Ru, Rh,
A method for manufacturing a semiconductor device, comprising using one or more elements selected from Pd, Os, Ir, Pt, Cu, Au, and Ge. 29. An active matrix display device manufactured using the manufacturing method according to claim 1. Description: 30. An electronic apparatus comprising the active matrix display device according to claim 29.