JP2000183043A - Semiconductor device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide wiring structure that can prevent charging damages in a plasma process such as reactive ion etching(RIE), etc. SOLUTION: This semiconductor device is provided with a first semiconductor element of a MIS structure, in which the film thickness of a gate insulation film 13 is larger than a prescribed film thickness, a second semiconductor element of a MIS structure, in which the film thickness of a gate insulation film 113 is smaller than a prescribed film thickness, functional wirings 17 and 18 for circuit operation which are connected respectively to at least an interlayer insulation film 16 having one layer or more and at least a gate 14 of a first semiconductor element, and dummy wirings 20 and 21 which are provided in a region apart from the functional wiring and are connected selectively to a well 11, where the first semiconductor element is formed and are not used for circuit operation.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to a semiconductor device having a wiring structure for reducing charging damage and a method of manufacturing the same.

[0002]

2. Description of the Related Art In the manufacture of semiconductor devices, charging damage due to plasma such as RIE often occurs, which is a problem. There are several causes of charging damage, one of which is the following mechanism. That is, wiring, contacts, vias, and the like connected to the gate electrode receive charges from the plasma and charge is generated in the gate insulating film. As a result, a high electric field is applied to the gate insulating film due to a rise in gate potential, and FN current flows. This is to damage the gate insulating film.

FIG. 16 is a view for explaining a damaging mechanism when wiring such as Al is patterned by RIE. 51 is a silicon substrate (not shown)
An interlayer insulating film formed thereon, 52 is a metal film for wiring using Al or the like, and 53 is a resist.

FIG. 16A shows a stage in the middle of etching. The metal film 52 for wiring is a continuous film, and the gate of the MOS transistor (not shown) passes through the metal film 52. Since it is connected to the substrate, no charging damage occurs in the gate portion.

FIG. 16B shows a stage where the etching has further progressed. Due to the characteristics of RIE, etching progresses faster in a region with a sparse pattern than in a region with a high density. Therefore, even in the middle of etching, an island-shaped pattern is formed according to the density of the wiring pattern. At this time, if the island-shaped metal film pattern is connected to the substrate, no charging damage occurs, but if it is not connected to the substrate, charges are accumulated in the gate insulating film of the MOS transistor. Therefore, the potential of the gate is increased by the accumulated charges, and high electric field stress is applied to the gate insulating film.

FIG. 16C shows a stage in which the etching has further progressed and the pattern of the metal film 52 has been completely separated. At this stage, charges are received from the side wall portions of the separated pattern of the metal film 52, and a high electric field stress is applied to the gate insulating film due to an increase in the gate potential.

The above example describes charging damage during wiring processing by RIE or the like.
Charging damage also poses a problem when forming connection holes and wiring grooves by RIE or the like when fabricating a buried wiring structure. That is, when a connection hole or a wiring groove is formed in an interlayer insulating film by RIE or the like, a potential difference is generated between the gate of the MOS transistor and the substrate due to accumulation of electric charges, so that high electric field stress is applied to the gate insulating film. .

[0008]

As described above, in the prior art, M is not used in a plasma process such as RIE at the time of wiring processing.
Charging damage occurred in the IS structure, causing deterioration of the gate insulating film. Also, in the buried wiring structure, charging damage occurs in the MIS structure in a plasma process such as RIE at the time of forming a connection hole or a wiring groove, causing deterioration of the gate insulating film.

An object of the present invention is to provide a semiconductor device having a wiring structure capable of preventing charging damage in a plasma process such as RIE, and a method of manufacturing the same.

[0010]

A semiconductor device according to the present invention comprises: a first semiconductor element having a MIS structure formed on a main surface side of a semiconductor substrate and having a gate insulating film having a thickness larger than a predetermined thickness; A second semiconductor element having a MIS structure formed on the main surface side of the substrate and having a gate insulating film having a thickness smaller than a predetermined thickness, at least one or more interlayer insulating films, and a connection hole of the interlayer insulating film. A first functional wiring portion formed on the substrate and a second functional wiring portion formed on the interlayer insulating film, wherein at least a functional wiring connected to a gate of the first semiconductor element and used for a circuit operation is provided; A dummy wiring provided in a region separated from the functional wiring and selectively used for a circuit operation and selectively connected to a well in which the first semiconductor element is formed. A).

In the configuration A, it is preferable that the dummy wiring is provided near the functional wiring (referred to as configuration B).

In the above-described configuration A, one or more intermediate wirings may be provided between the functional wiring and the dummy wiring, and the dummy wiring and the functional wiring may be provided near the one or more intermediate wirings. Good (referred to as configuration C).

As described above, by forming the dummy wiring, the gate potential and the well potential can be kept at the same potential during most of the plasma process such as RIE in wiring processing. Therefore, charging damage in a plasma process such as RIE at the time of wiring processing can be prevented, and deterioration of the gate insulating film can be prevented. In particular, by adopting the configuration B or C, the functional wiring and the dummy wiring can be connected with a higher probability until immediately before the end of RIE, and the charging damage can be further prevented.

The reason that the dummy wiring is selectively connected only to the well in which the first semiconductor element (the semiconductor element in which the gate insulating film is thicker than a predetermined thickness) is formed is as follows. by.

FIG. 8 schematically shows the relationship between the thickness of the gate insulating film and the non-defective product rate. When the thickness of the gate insulating film becomes about 40 ° or less, the non-defective product rate increases. As described above, the gate insulating film suffers from charging damage in the plasma process, but the gate insulating film has a thickness of 4 μm.
When the temperature becomes about 0 ° or less, the charge of the gate electrode passes through the gate insulating film without damaging the gate insulating film by direct ton ring. Therefore, when the thickness of the gate insulating film is smaller than about 40 °, accumulation of charges in the gate electrode in the plasma process is significantly suppressed, and charging damage can be reduced.

Therefore, only the first semiconductor element having a thick gate insulating film needs to be protected by the dummy wiring against charging damage due to plasma. In this way, if only the first semiconductor element is protected by the dummy wiring, there is no need to provide an extra dummy wiring (dummy wiring for protecting the second semiconductor element). As a result, effects such as an increase in the degree of freedom in layout, a decrease in the chip size, and a possibility of disposing a dummy wiring for protecting the first semiconductor element in an empty space can be obtained.

From the viewpoint described above, the “predetermined film thickness” of the gate insulating film can be typically set to 40 °, but if the film thickness is selected from the range of 30 to 50 °. Good. A typical example of the gate insulating film is an insulating film having a relative dielectric constant of 3.9 or more, such as a silicon oxide film, a silicon nitride film, a silicon nitride oxide film, and a tantalum oxide film.

The more specific structures of the above structures A to C are as follows.

The dummy wiring comprises a first dummy wiring portion formed in a connection hole of at least one interlayer insulating film and a second dummy wiring portion formed on at least one interlayer insulating film. (Constitution D).

The dummy wiring consists only of the first dummy wiring portion formed in the connection hole of the interlayer insulating film (referred to as configuration E).

A plurality of first dummy wiring portions formed in each connection hole of the plurality of interlayer insulating films and one or more second dummy wiring portions formed on an interlayer insulating film other than the uppermost interlayer insulating film. (The configuration F).

In the structures E and F, the second dummy wiring portion is not provided on the uppermost interlayer insulating film (if the interlayer insulating film is a single layer, the single dummy interlayer insulating film is not provided). The dummy wiring is terminated by the wiring part. Since there is no second dummy wiring portion, there is an effect that the probability of occurrence of a short circuit in the first functional wiring in the uppermost layer is reduced and the capacitance between wirings can be reduced. In this case, if the first dummy wiring portion and the second functional wiring portion are made of different materials, the second functional wiring portion is selectively etched with respect to the first dummy wiring portion. The first dummy wiring portion can be left in the connection hole without being etched.

The distance between the functional wiring and the dummy wiring, the distance between the functional wiring and the intermediate wiring, or the distance between the dummy wiring and the intermediate wiring is at least partly within five times the minimum design wiring distance rule. Or a distance of 1 μm or less.

The semiconductor device according to the present invention has a first semiconductor element having a MIS structure formed on a main surface side of a semiconductor substrate and having a gate insulating film having a thickness larger than a predetermined thickness, and a main surface of the semiconductor substrate. A second semiconductor element having a MIS structure and a gate insulating film having a thickness smaller than a predetermined thickness formed on the second side, at least one or more interlayer insulating films, and formed in connection holes of the interlayer insulating film. A first functional wiring portion and a second functional wiring portion embedded in a wiring groove of the interlayer insulating film, the functional wiring being used for a circuit operation connected to at least a gate of the first semiconductor element; A dummy wiring provided in a region separated from the functional wiring and selectively used for a circuit operation and selectively connected to a well in which the first semiconductor element is formed (Configuration G) And).

The more specific configuration of the configuration G is as follows. A first dummy wiring portion in which a dummy wiring is formed in a dummy connection hole of at least one or more layers of an interlayer insulating film and a second dummy wiring portion embedded in a dummy wiring groove of at least one or more layers of an interlayer insulating film (Referred to as configuration H).

According to the above configuration, the dummy regions (dummy connection holes and dummy wiring grooves) where the dummy wirings are to be finally formed are simultaneously formed in the plasma process such as RIE for processing the connection holes and the wiring grooves. Will be formed. Therefore, in the plasma process, charge is supplied not only to the gate but also to the well through the dummy region, and the potential difference between the gate potential and the well potential can be reduced.
Therefore, charging damage in a plasma process such as RIE when processing a connection hole or a wiring groove can be prevented, and deterioration of the gate insulating film can be prevented.

Note that the dummy wiring is connected to the first semiconductor element (a semiconductor element having a gate insulating film having a thickness larger than a predetermined thickness).
The reason for selectively connecting only to the well in which is formed is the same as the reason described above. The “predetermined film thickness” of the gate insulating film and the type of the gate insulating film are the same as those described above.

In any of the above structures A to H, the dummy wiring may extend to a region above the well in which the second semiconductor element is formed (referred to as structure I).

As described above, the dummy wiring is selectively connected only to the well in which the first semiconductor element is formed, thereby protecting the second semiconductor element having a thin gate insulating film. There is no need to provide extra dummy wiring. Therefore, an empty space may be formed above the well where the second semiconductor element is formed. By extending the dummy wiring to this empty space, the area of the dummy wiring can be increased. as a result,
Since a larger amount of plasma charge can be injected into the substrate and the potential difference between the gate potential and the substrate potential can be reduced, charging damage can be further reduced. Further, by filling the empty space with the dummy wiring, the density of the wiring pattern can be made uniform, and the variation in the wiring processing time can be reduced, so that the charging damage can be further reduced. .

In the above structures A to I, the method of connecting the dummy wiring to the semiconductor substrate is as follows.

A dummy wiring is connected to a region of the same or opposite conductivity type as that of the impurity diffusion layer via an impurity diffusion layer (P ⁺ diffusion layer or N ⁺ diffusion layer) provided in the well.

A dummy wiring is connected to the well via an impurity diffusion layer (P ⁺ diffusion layer or N ⁺ diffusion layer) constituting a source or a drain of the semiconductor element. By connecting the dummy wiring to the source or drain region in this manner, the occupied area can be reduced.

In the structures D and F, the short sides of the wiring pattern of the second functional wiring portion and the wiring pattern of the second dummy wiring portion are opposed to each other, or the wiring pattern of the second functional wiring portion is If one short side and the other long side of the wiring pattern of the second dummy wiring section are opposed to each other, the wiring between the second functional wiring section and the second dummy wiring section is reduced. The capacity can be reduced.

The method for manufacturing a semiconductor device according to the present invention comprises:
A first semiconductor element having a MIS structure formed on the main surface side of the semiconductor substrate and having a gate insulating film having a thickness larger than a predetermined thickness;
A second semiconductor element having a MIS structure formed on the main surface side of the semiconductor substrate and having a gate insulating film having a thickness smaller than a predetermined thickness;
At least one or more interlayer insulating films;
A lower function wiring portion connected to at least a gate of the first semiconductor element through at least one layer of an interlayer insulating film and serving as a part of a function wiring used for a circuit operation;
A lower dummy wiring portion selectively connected to a well in which the first semiconductor element is formed through at least one interlayer insulating film and serving as a part of a dummy wiring not used for a circuit operation; Forming a conductive film on the substrate and selectively removing the conductive film by etching using plasma to form an upper function wiring portion which becomes a part of the function wiring and is connected to the lower function wiring portion. And forming an upper dummy wiring portion which becomes a part of the dummy wiring and is connected to the lower dummy wiring portion.

This is a manufacturing method generally corresponding to the above-described configuration D, and has the same operation and effect as those described above.

Further, according to the method of manufacturing a semiconductor device of the present invention, a first semiconductor element having an MIS structure formed on a main surface side of a semiconductor substrate and having a gate insulating film having a thickness larger than a predetermined thickness is provided. A second semiconductor element having a MIS structure formed on the main surface of the semiconductor device and having a gate insulating film having a thickness smaller than a predetermined thickness, at least one or more interlayer insulating films, and at least one or more interlayer insulating films Through at least the first
A lower function wiring portion connected to the gate of the semiconductor device and serving as a part of a function wiring used for circuit operation; and a well in which the first semiconductor device is formed through the at least one or more interlayer insulating films. Forming a conductive film on a lower structure having a lower dummy wiring portion which is selectively connected to the semiconductor device and is at least a part of a dummy wiring not used for a circuit operation; and etching the lower dummy by using plasma. Forming an upper function wiring portion which becomes a part of the function wiring and is connected to the lower function wiring portion by selectively removing the conductive film including the upper portion of the wiring portion.

This is a manufacturing method generally corresponding to the above-described configurations E and F, and has the same operation and effects as those described above.

Further, according to the method of manufacturing a semiconductor device of the present invention, a first semiconductor element having a MIS structure formed on a main surface side of a semiconductor substrate and having a gate insulating film having a thickness larger than a predetermined thickness is provided. Forming an interlayer insulating film on the main surface side of a semiconductor substrate on which a second semiconductor element having a MIS structure formed with a gate insulating film having a thickness smaller than a predetermined thickness and formed on the main surface side of A connection hole and a wiring groove for forming a functional wiring connected to at least a gate of the first semiconductor element and used for a circuit operation are formed in the interlayer insulating film by etching using plasma, and
Forming a dummy connection hole and a dummy wiring groove in the interlayer insulating film for forming a dummy wiring which is selectively connected to the well in which the semiconductor element is formed and which is not used for a circuit operation; Forming the functional wiring in the inside and the wiring groove, and forming the dummy wiring in the dummy connection hole and the dummy wiring groove.

This is a manufacturing method generally corresponding to the above-described configuration H, and has the same functions and effects as those described above.

[0040]

Preferred embodiments of the present invention will be described below with reference to the accompanying drawings.

(Embodiment 1) FIG. 1 shows a first embodiment of the present invention.

Reference numeral 11 denotes a P well formed in the silicon substrate. The P well 11 is formed with an N-channel MOS transistor including a gate insulating film 13, a gate 14, and an impurity diffusion layer 15 serving as a source or a drain. I have. The thickness of the gate insulating film 13 is, for example, 50 °, which is larger than a predetermined thickness (for example, 40 °). 12
Denotes an element isolation insulating film, and 16 denotes an interlayer insulating film.

The gate 14 is connected to a functional wiring used for an actual circuit operation. The functional wiring is formed in a wiring portion formed in a connection hole of the interlayer insulating film 16 (hereinafter referred to as an interlayer connection functional wiring portion). 17) and a wiring portion (hereinafter, referred to as an on-layer functional wiring portion) 18 formed on the interlayer insulating film. To the impurity diffusion layer 19 of the P well 11, a dummy wiring which is not used for an actual circuit operation (is electrically separated from a functional wiring or the like) is connected. This dummy wiring is connected to the interlayer insulating film 16. A wiring portion (hereinafter, referred to as an interlayer connection dummy wiring portion) 20 formed in the hole and a wiring portion (hereinafter, referred to as an on-layer dummy wiring portion) 21 formed on the interlayer insulating film. On-layer functional wiring section 18
And the on-layer dummy wiring section 21 are arranged adjacent to each other at least in some places (a distance within 5 times the minimum design wiring distance rule, or a distance of 1 μm or less. preferable.).

In the same silicon substrate, an N well 111 is provided.
The N well 111 has a gate insulating film 11
3, a P-channel MOS transistor including a gate 114 and an impurity diffusion layer 115 serving as a source or a drain is formed. The thickness of the gate insulating film 113 is, for example, 3
0 °, which is smaller than a predetermined film thickness (for example, 40 °). The function wiring used for the actual circuit operation is connected to the gate 114. The function wiring includes a wiring part (interlayer connection function wiring part) 117 formed in the connection hole of the interlayer insulating film 16 and an interlayer insulating film. The wiring section (functional wiring section on a layer) 118 is formed on the film. In addition,
Unlike the well 11, the dummy wiring is not connected to all the wells 111 on the same substrate.

The on-layer functional wiring portions 18 and 118 can be obtained by forming a wiring metal on the interlayer insulating film 16 and then processing it using RIE. In this RIE step, the on-layer functional wiring portions 18 and 118 are obtained. The pattern of the on-layer dummy wiring portion 21 is formed in the vicinity of this pattern. By forming the on-layer dummy wiring portion 21 in the vicinity of the on-layer functional wiring portion 18 in this manner, the potential of the gate 14 of the MOS transistor formed in the P well 11 and the P well 11 can be maintained at a conductive potential. Therefore, a high electric field is not applied to the gate oxide film 13, and charging damage can be suppressed.

The MOS formed in the N well 111
Since the gate insulating film 113 of the transistor has a small thickness, electric charges generated in the RIE process pass through the gate insulating film 113 by direct ton ring. Therefore, no high electric field is applied to gate oxide film 113. Therefore, charging damage can be prevented without connecting a dummy wiring to the N well 111.

If the length of the on-layer dummy wiring section 21 is made as short as possible, the capacitance between the wirings formed by the on-layer dummy wiring section 21 and the on-layer functional wiring section 18 can be reduced, and the circuit operation is reduced. However, if the increase in inter-wiring capacitance does not cause a significant problem in terms of circuit operation, it is preferable to increase the length of the on-layer dummy wiring portion 21 from the viewpoint of suppressing charging damage.

(Embodiment 2) FIG. 2 shows a second embodiment of the present invention. Components that are substantially the same as or correspond to those in the first embodiment shown in FIG. 1 are denoted by the same reference numerals, and detailed description thereof is omitted (the same applies to other embodiments).

In the first embodiment shown in FIG. 1, the dummy wiring is constituted by the interlayer connection dummy wiring section 20 and the on-layer dummy wiring section 21. In the present embodiment, however, the dummy wiring is formed by the interlayer connection dummy wiring section. Composed only of the part 20,
The on-layer dummy wiring section 21 shown in FIG. 1 is not provided. The on-layer function wiring section 18 and the interlayer connection dummy wiring section 20 are arranged adjacent to each other at least in some places. By omitting the on-layer dummy wiring section 21 as described above, the short-circuit of the on-layer functional wiring section 18 can be reduced, and the capacitance between wirings can be reduced.

The on-layer functional wiring portions 18 and 118 can be obtained by forming a wiring metal on the interlayer insulating film 16 and then processing it using RIE. In this RIE step, the on-layer functional wiring portions 18 and 118 are obtained. And 118 only. Unlike the first embodiment, the on-layer dummy wiring portion 21 is not formed, but the wiring metal remains on the interlayer insulating film 16 until immediately before the end of the RIE process. For most of the time, the potential of the gate 14 of the MOS transistor and the potential of the P well 11 can be maintained at the conductive potential.
Therefore, similarly to the first embodiment, the gate oxide film 13
Is not applied with a high electric field, and charging damage can be suppressed.

If the interlayer connection dummy wiring section 20 and the on-layer function wiring sections 18 and 118 are made of different materials (for example, tungsten is used for the interlayer connection dummy wiring section 20 and the on-layer function wiring section 18 and 118). By selectively etching the on-layer function wiring portions 18 and 118 with respect to the interlayer connection dummy wiring portion 20, the interlayer connection dummy wiring portion 20 is left in the connection hole without being etched. it can.

(Embodiment 3) FIG. 3 shows a third embodiment of the present invention.

In this embodiment, the present invention is applied to a multilayer wiring structure. That is, the interlayer insulating film 31 is formed on the upper layer side of the interlayer insulating film 16, and in the region of the P well 11, the function wirings are the interlayer connection function wiring portion 17, the on-layer function wiring portion 18, the interlayer connection function wiring portion 32 The dummy wiring includes an interlayer connection dummy wiring section 20, an interlayer dummy wiring section 21, an interlayer connection dummy wiring section 34, and a layer dummy wiring section 35. In the region of the N-well 111, the function wiring is composed of an interlayer connection function wiring section 117, an on-layer function wiring section 118, an inter-layer connection function wiring section 132, and an on-layer function wiring section 133.

In the example shown in FIG.
And the on-layer dummy wiring portion 21 are arranged adjacent to each other at least in some places, and the on-layer functional wiring portion 33 and the on-layer dummy wiring portion 35 are arranged adjacent to each other in at least some places. Have been. Therefore, charging damage can be suppressed in each of the RIE step for forming the on-layer function wiring section 18 and the RIE step for forming the on-layer function wiring section 33.

(Embodiment 4) FIG. 4 shows a fourth embodiment of the present invention.

This embodiment is similar to the third embodiment described above.
The present invention is applied to a multilayer wiring structure. In the present embodiment, the on-layer dummy wiring portion 35 shown in FIG. 3 is not provided on the uppermost interlayer insulating film 31. The on-layer function wiring portion 33 and the interlayer connection dummy wiring portion 34 are arranged adjacent to each other at least in some places. As described above, by omitting the on-layer dummy wiring portion 35, FIG.
As in the second embodiment shown in FIG.
Can be reduced, and the capacitance between wirings can be reduced.

(Fifth Embodiment) FIG. 5 shows a fifth embodiment of the present invention.

In the first embodiment and the like, the dummy wiring is P ⁺
The impurity diffusion layer was connected to the P well via the impurity diffusion layer, and the impurity diffusion layer and the well were of the same conductivity type. In this embodiment, the dummy wiring is connected to the P well 11 via the N ⁺ impurity diffusion layer 19b, and the impurity diffusion layer and the well have the opposite conductivity types. Therefore, the dummy wiring is connected to the P-well 11 via the diode. Even with such connection, the same effect as that of the first embodiment and the like can be obtained. Diode is RI
Depending on the polarity of the charge-up at the time of E, the connection is made in the forward or reverse direction. Note that even in the reverse connection, the potential of the wiring can normally be charged up to several tens of volts or more during RIE, so that the charge is transferred to the P well 1 by the reverse breakdown current.
It is possible to escape to 1.

(Embodiment 6) FIG. 6 shows a sixth embodiment of the present invention.

In the first embodiment and the like, the dummy wiring is
Although the well is connected via an impurity diffusion layer provided separately from the source and drain of the S transistor, in the present embodiment, the dummy wiring is connected via the impurity diffusion layer 15 constituting the source or drain of the MOS transistor. Connected to P well 11. As described above, by connecting the dummy wiring to the impurity diffusion layer forming the source or the drain, the occupied area can be reduced.

(Embodiment 7) FIG. 7 shows a seventh embodiment of the present invention.

In the first embodiment and the like, the dummy wiring is arranged near the functional wiring. In the present embodiment, at least one or more intermediate wirings 22 are arranged between the dummy wiring and the functional wiring, and the dummy wiring is arranged. And intermediate wiring 2 respectively
2 is disposed in the vicinity. When there are a plurality of intermediate wirings, adjacent intermediate wirings are arranged near each other. The term “intermediate wiring” as used herein may mean a wire used for actual circuit operation (for example, a wire connected to an element used for circuit operation) or a wire not used for actual circuit operation (for example, Electrically isolated).

The on-layer functional wiring portions 18 and 118 can be obtained by forming a wiring metal on the interlayer insulating film 16 and processing it by RIE as in the first embodiment. In the RIE process, the patterns of the on-layer dummy wiring portion 21 and the intermediate wiring 22 are formed. Even when the intermediate wiring 22 is formed between the dummy wiring and the functional wiring in this manner, the dummy wiring and the functional wiring are connected via the intermediate wiring 22 for most of the time of the RIE process. The potential of the gate 14 of the transistor and the potential of the well 11 can be maintained at the conductive potential. Therefore, a high electric field is not applied to the gate oxide film 13, and charging damage can be suppressed.

(Embodiment 8) FIG. 9 shows an eighth embodiment of the present invention. FIG. 7A is a diagram showing a cross-sectional configuration of the device structure as in the first to seventh embodiments, and FIG. 7B is a diagram schematically showing a planar arrangement pattern of dummy wirings. It is.

In the first to seventh embodiments, the on-layer dummy wiring portion 21 is formed only above the P-well region 11 (the well region where the MOS transistor having the thick gate insulating film 13 is formed). However, in this embodiment,
The on-layer dummy wiring portion 21 extends to a region above the N-well region 111 (a well region where a MOS transistor having a thin gate insulating film 13 is formed).

As described above, by filling the empty space above the N-well region 111 with the dummy wiring, a wiring pattern is formed in almost all regions on the wafer. Accordingly, the density of the wiring pattern can be made uniform, the variation in the wiring processing time in the wafer surface can be reduced, and the charging damage can be further reduced.

In the first to eighth embodiments described above, the transistor having a thick gate insulating film is an NMOS, and the well in which the NMOS transistor is formed is P-type.
Although the well has been described, the conductivity types of the transistor and the well may be opposite to those of the above embodiments. That is, a transistor having a thick gate insulating film is replaced with a PMOS transistor.
The well in which the PMOS transistor is formed may be an N well. Needless to say, the respective configurations described in the first to eighth embodiments may be combined with each other.

Next, the planar positional relationship between the functional wiring and the dummy wiring shown in the first to eighth embodiments, particularly, the functional wiring part 18 (33) on the layer and the dummy wiring part 21 (3
FIGS. 10 and 11 show the planar arrangement relationship with 5).
This will be described with reference to FIG.

FIG. 10A shows the on-layer functional wiring portion 18 (3
3) and the on-layer dummy wiring section 21 (35) are parallel, and the length of the on-layer dummy wiring section 21 (35) is shortened. By reducing the length of the on-layer dummy wiring section 21 (35) in this way, the capacitance between wirings formed by the on-layer dummy wiring section 21 (35) and the on-layer functional wiring section 18 (33) is reduced. can do.

FIG. 10B shows the function wiring portion 18 (3
3) and the on-layer dummy wiring portion 21 (35) are parallel, and the length of the on-layer dummy wiring portion 21 (35) is increased. By increasing the length of the on-layer dummy wiring section 21 (35) in this manner, the functional wiring and the dummy wiring can be connected with a higher probability until immediately before the end of RIE.

FIG. 10C shows the function wiring portion 18 (3
3) and short sides of the on-layer dummy wiring section 21 (35) are opposed to each other.
The inter-wiring capacitance formed by (35) and the on-layer functional wiring portion 18 (33) can be reduced.

FIG. 10D shows the on-layer functional wiring portion 18 (3
3) and one short side and the other long side of the on-layer dummy wiring portion 21 (35) are opposed to each other, and the on-layer dummy wiring portion 21 (35) and the on-layer functional wiring portion 18 (33) ) Can be reduced.

FIG. 11 shows a configuration example in which an intermediate wiring is provided between the on-layer functional wiring section 18 (33) and the on-layer dummy wiring section 21 (35). In this example, the intermediate wiring 22a used for actual circuit operation (for example, one connected to an element used for circuit operation) and the intermediate wiring 22b not used for actual circuit operation (for example, Separated).

Next, application examples of dummy wirings (application locations, etc.)
Will be described.

As the application places of the dummy wiring, for example,
Near the wiring connected to the input of the CMOS inverter, S
The vicinity of the word line of the RAM, the vicinity of the data line of the multiplier, and the like can be given. In particular, it is effective to arrange the wiring near a wiring such as a clock signal line, a word line, an address bus line, which is long (has a high antenna ratio) and in which a potential difference between a gate and a substrate is likely to occur in a plasma process such as RIE. It is a target.

FIG. 12 shows that a dummy wiring is arranged in a basic cell of an SRAM, and the basic cell is repeatedly used.
It constitutes an array. That is, the word line WL
, A basic cell is configured by arranging a dummy wiring DM in the vicinity of (FIG. 12 (a)), and this is repeatedly arranged to form an SRAM array (FIG. 12 (b)). As described above, when a circuit is configured by repeating basic cells, providing a dummy wiring for each basic cell or for each of a plurality of basic cells can greatly reduce the circuit design work.

(Embodiment 9) Next, a ninth embodiment of the present invention will be described with reference to FIG. In the present embodiment, the present invention is applied to an embedded wiring structure. Components that are substantially the same as or correspond to those of the first embodiment and the like illustrated in FIG. 1 are denoted by the same reference numerals, and detailed description thereof will be omitted (the same applies hereinafter).

FIG. 13A shows an interlayer insulating film 61 formed on a substrate on which a MOS transistor or the like is formed, and connection holes 62 and 162 for forming a wiring having a so-called dual damascene structure in the interlayer insulating film 61. And wiring grooves 63, 16
3 shows a state formed by the RIE process. At this time, the dummy connection hole 64 and the dummy wiring groove 65 are formed.
Are simultaneously formed by the RIE process.

Conventionally, charges are accumulated only in the gate 14 when the surfaces of the gates 14 and 114 are exposed by the RIE process, so that a large potential difference occurs between the gate 14 and the substrate (P well 11), and the gate insulation There is a problem that a high electric field stress is applied to the film 13. In the present embodiment, since the dummy connection holes 64 and the dummy wiring grooves 65 are also formed simultaneously in the RIE process, charges are supplied not only to the gate but also to the P ⁺ impurity diffusion layer 19 formed in the well, and the potential of the gate and the well Can be reduced. Therefore, the electric field applied to the gate insulating film 13 can be reduced, and charging damage can be suppressed.

After the RIE process is completed, a predetermined wiring metal is deposited on the entire surface, and the wiring metal is formed by RIE or CMP. In this manner, as shown in FIG. 13B, the wiring portion 6 embedded in the connection holes 62 and 162
6, 166 (hereinafter, referred to as a functional wiring portion in a hole) and wiring portions 67, 167 (hereinafter, referred to as a functional wiring portion in a groove) embedded in the wiring grooves 63, 163, and a dummy connection hole. A wiring portion 68 buried in 64 (hereinafter referred to as a dummy wiring portion in a hole) and a wiring portion 69 buried in a dummy wiring groove 65 (hereinafter referred to as a dummy wiring portion in a groove).
Is formed.

(Embodiment 10) Next, a tenth embodiment of the present invention will be described with reference to FIG. In the present embodiment, as in the ninth embodiment, the present invention is applied to a multilayer wiring having an embedded wiring structure.

FIG. 14A shows an example in which an interlayer insulating film 71 is formed on the lower structure formed by the process of FIG. 13, and a connection hole 72 for forming a wiring of a dual damascene structure is formed in the interlayer insulating film 71. 172 and wiring grooves 73 and 173
Are formed by the RIE process. At this time, the dummy connection holes 74 and the dummy wiring grooves 75
Are simultaneously formed by the RIE process.

Conventionally, when the surface of the lower wiring (surfaces of the functional wiring portions 67 and 167 in the groove) is exposed by the RIE process, charges are transferred through the lower wiring (the functional wiring portion 66 in the hole and the functional wiring portion 67 in the groove) to form a gate. 14 only. Therefore, there is a problem that a large potential difference occurs between the gate 14 and the substrate (P well 11), and a high electric field stress is applied to the gate insulating film 13. In the present embodiment, R
In the IE process, the dummy connection hole 74 and the dummy wiring groove 7 are formed.
5 is also formed at the same time, the charge is also supplied to the P ⁺ impurity diffusion layer 19 formed in the well through the lower wiring (the dummy wiring section 68 in the hole and the dummy wiring section 69 in the groove), and the potential of the gate and the potential of the well are supplied. Can be reduced. Therefore, the electric field applied to the gate insulating film 13 can be reduced, and charging damage can be suppressed.

After the RIE process is completed, a predetermined wiring metal is deposited on the entire surface, and the wiring metal is formed by RIE or CMP. In this way, as shown in FIG. 14B, the functional wiring portions 76 and 176 embedded in the connection holes 72 and 172 and the functional wiring portion 77 embedded in the wiring grooves 73 and 173 are formed. , 177 are formed, and a dummy wiring portion 78 buried in the dummy connection hole 74 and a dummy wiring portion 79 buried in the dummy wiring groove 75 are formed.

(Embodiment 11) Next, an eleventh embodiment of the present invention will be described with reference to FIG. In the present embodiment, as in the ninth embodiment and the like, the present invention is applied to a multilayer wiring having a buried wiring structure. Although the N well is not shown in FIG. 15, a MOS transistor having a thin gate insulating film is formed in the N well region as in the ninth embodiment.

In this embodiment, as shown in FIG. 15, a plurality of dummy wiring regions are provided in the same well. In order to reduce the charging damage of the gate insulating film,
It is preferable that the amount of charge received by the gate during RIE and the amount of charge received by the well be balanced in the same well.
However, there are cases where the number of connection holes on the gate is large and the amount of charge received by the gate is significantly different from the amount of charge received by the well. Therefore, in the same well 11, the total area of the connection holes on the gate 14 and the total area of the dummy connection holes on the well (on the P ⁺ diffusion layer 19) are made as equal as possible. For example, when the area of one connection hole on the gate 14 and the area of one dummy connection hole on the P ⁺ diffusion layer 19 are equal, the numbers of both may be equal.

In the ninth to eleventh embodiments, similarly to the eighth embodiment shown in FIG. 9, the in-groove dummy wiring portions 69 and 79 are connected to the P-well region 11 (of the gate insulating film 13). N well region 111 as well as above the well region where the thick MOS transistor is formed).
It may be extended to a region above a (well region where a MOS transistor having a thin gate insulating film 13 is formed).

As described above, by filling the empty space above the N well region with the dummy wiring, the area of the dummy wiring can be increased. This allows more plasma charge to be injected into the substrate,
The potential difference between the gate potential and the substrate potential can be further reduced, and charging damage can be further reduced.

In the ninth to eleventh embodiments (an example in which the present invention is applied to a buried wiring structure), a description has been given of a wiring having a dual damascene structure. Is also applicable.

In the ninth to eleventh embodiments,
According to the first embodiment and the like shown in FIG. 1, an example is shown in which an NMOS transistor is manufactured in a P well and a dummy wiring is connected to a P ⁺ diffusion layer, as shown in FIG. 5 or FIG. It is also possible to employ a simple configuration.

In the ninth to eleventh embodiments,
Unlike the first to eighth embodiments, it is not always necessary to provide a dummy wiring near the functional wiring. However, in the case where RIE is used when embedding the wiring metal, the first to eighth wirings may be used.
As in the first embodiment, a problem of charging damage during wiring processing may occur. Therefore, for the planar positional relationship between the functional wiring and the dummy wiring, for example, a configuration as shown in FIGS. 10 and 11 may be adopted.

Although various embodiments have been described above, the present invention is not limited to these embodiments, and various modifications can be made without departing from the spirit of the present invention.

[0093]

According to the present invention, the potential difference between the gate potential and the well potential can be reduced in a plasma process such as RIE. Therefore, charging damage in a plasma process such as RIE can be suppressed, and deterioration of the gate insulating film can be prevented.

Further, by selectively connecting the dummy wiring to the well in which the semiconductor element in which the thickness of the gate insulating film is larger than a predetermined thickness is formed, an extra dummy wiring (film of the gate insulating film) is formed. It is not necessary to provide a dummy wiring for protecting a semiconductor element having a thickness smaller than a predetermined thickness.
As a result, the degree of freedom in layout increases, and the chip size can be reduced.

[Brief description of the drawings]

FIG. 1 is a diagram showing a cross-sectional configuration of a first embodiment of the present invention.

FIG. 2 is a diagram showing a cross-sectional configuration of a second embodiment of the present invention.

FIG. 3 is a diagram showing a cross-sectional configuration of a third embodiment of the present invention.

FIG. 4 is a diagram showing a cross-sectional configuration of a fourth embodiment of the present invention.

FIG. 5 is a diagram showing a cross-sectional configuration of a fifth embodiment of the present invention.

FIG. 6 is a diagram showing a cross-sectional configuration of a sixth embodiment of the present invention.

FIG. 7 is a diagram showing a cross-sectional configuration of a seventh embodiment of the present invention.

FIG. 8 is a diagram schematically showing a relationship between a film thickness of a gate insulating film and a defect rate caused by dielectric breakdown or the like of the gate insulating film.

FIG. 9 is a view showing an eighth embodiment of the present invention.

FIG. 10 is a diagram illustrating a planar positional relationship between the functional wiring and the dummy wiring described in the first to sixth embodiments.

FIG. 11 is a diagram showing a planar positional relationship among a functional wiring, a dummy wiring, and an intermediate wiring shown in the seventh embodiment.

FIG. 12 is a diagram showing a configuration example when a dummy wiring is applied to an SRAM circuit;

FIG. 13 is a process sectional view showing an example of a manufacturing process according to a ninth embodiment of the present invention.

FIG. 14 is a process sectional view showing an example of a manufacturing process according to the tenth embodiment of the present invention.

FIG. 15 is a diagram showing a cross-sectional configuration of an eleventh embodiment of the present invention.

FIG. 16 is a diagram for explaining a problem of the related art.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 11 ... P well 12 ... Element isolation insulating film 13, 113 ... Gate insulating film 14, 114 ... Gate 15, 115 ... Source and drain (impurity diffusion layer) 16, 31, 61, 71 ... Interlayer insulating film 17, 32, 117 , 132 ... interlayer connection function wiring section (first function wiring section) 18, 33, 118, 133 ... layer function wiring section (second function wiring section) 19 ... P ⁺ impurity diffusion layers 19a, 19b ... N ⁺ Impurity diffusion layers 20, 34 ... Dummy wiring part (first dummy wiring part) between layers 21, 35 ... Dummy wiring part on layer (second dummy wiring part) 22a, 22b ... Intermediate wiring 62, 72, 162, 172 ... Connection holes 63, 73, 163, 173. Wiring grooves 64, 74. Dummy connection holes 65, 75 .. Dummy wiring grooves 66, 76, 166, 176. In-hole functional wiring portion (first functional wiring portion) 67. 7 7, 167, 177: In-groove functional wiring portion (second functional wiring portion) 68, 78 ... In-hole dummy wiring portion (first dummy wiring portion) 69, 79 ... In-groove dummy wiring portion (second dummy) Wiring section) 111 ... N well

Claims (6)

[Claims] A first semiconductor element having a MIS structure formed on a main surface of the semiconductor substrate and having a gate insulating film having a thickness larger than a predetermined thickness; and a gate insulating film formed on the main surface of the semiconductor substrate. A second semiconductor element having a MIS structure whose film thickness is smaller than a predetermined film thickness; at least one or more interlayer insulating films; a first functional wiring portion formed in a connection hole of the interlayer insulating film; A second functional wiring portion formed on the interlayer insulating film, provided at least in a functional wiring used for a circuit operation connected to a gate of the first semiconductor element, and in a region separated from the functional wiring; And a dummy wiring which is selectively connected to a well in which the first semiconductor element is formed and is not used for a circuit operation. 2. A first semiconductor element having a MIS structure formed on a main surface side of a semiconductor substrate and having a gate insulating film having a thickness larger than a predetermined film thickness, and a gate insulating film formed on a main surface side of the semiconductor substrate. A second semiconductor element having a MIS structure whose film thickness is smaller than a predetermined film thickness; at least one or more interlayer insulating films; a first functional wiring portion formed in a connection hole of the interlayer insulating film; A function wiring used for a circuit operation connected to at least a gate of the first semiconductor element, comprising a second function wiring portion embedded in a wiring groove of the interlayer insulating film, and a region separated from the function wiring And a dummy wiring which is selectively connected to a well in which the first semiconductor element is formed and which is not used for a circuit operation. 3. The semiconductor device according to claim 1, wherein the dummy wiring extends to a region above the well in which the second semiconductor element is formed. 4. A first semiconductor element having a MIS structure formed on a main surface of a semiconductor substrate and having a gate insulating film having a thickness larger than a predetermined thickness, and a gate insulating film formed on a main surface of the semiconductor substrate. A second semiconductor element having a MIS structure whose film thickness is smaller than a predetermined thickness, at least one or more interlayer insulating films, and at least a gate of the first semiconductor element through at least one or more interlayer insulating films. And a lower functional wiring portion which is connected to the first functional element and serves as a part of a functional wiring used for circuit operation, and a well in which the first semiconductor element is formed through the at least one or more interlayer insulating films. A step of forming a conductive film on a lower structure having a lower dummy wiring portion which is connected and becomes a part of a dummy wiring not used for a circuit operation; and selectively removing the conductive film by etching using plasma. This Forming an upper function wiring portion which becomes a part of the function wiring and is connected to the lower function wiring portion, and forms an upper dummy wiring portion which becomes a part of the dummy wiring and is connected to the lower dummy wiring portion And a method of manufacturing a semiconductor device. 5. A first semiconductor element having a MIS structure formed on a main surface side of a semiconductor substrate and having a gate insulating film thicker than a predetermined film thickness, and a gate insulating film formed on a main surface side of the semiconductor substrate. A second semiconductor element having a MIS structure whose film thickness is smaller than a predetermined thickness, at least one or more interlayer insulating films, and at least a gate of the first semiconductor element through at least one or more interlayer insulating films. And a lower functional wiring portion which is connected to the first functional element and serves as a part of a functional wiring used for circuit operation, and a well in which the first semiconductor element is formed through the at least one or more interlayer insulating films. A step of forming a conductive film on a lower structure having a lower dummy wiring portion connected to and serving as at least a part of a dummy wiring not used for a circuit operation; and etching the lower dummy wiring portion by using plasma. Forming an upper function wiring portion which becomes a part of the function wiring and is connected to the lower function wiring portion by selectively removing the conductive film including the upper portion. Production method. 6. A first semiconductor element having a MIS structure formed on a main surface side of a semiconductor substrate and having a gate insulating film having a thickness larger than a predetermined thickness, and a gate insulating film formed on a main surface side of the semiconductor substrate. Forming an interlayer insulating film on the main surface side of a semiconductor substrate on which a second semiconductor element having a MIS structure having a thickness smaller than a predetermined film thickness is formed; A connection hole and a wiring groove for forming a functional wiring connected to a gate of the first semiconductor element and used for a circuit operation are formed in the interlayer insulating film, and a well in which the first semiconductor element is formed is formed. Forming a dummy connection hole and a dummy wiring groove in the interlayer insulating film for forming a dummy wiring selectively connected and not used for a circuit operation; and forming the functional wiring in the connection hole and the wiring groove. Formation Rutomoni method of manufacturing a semiconductor device characterized by a step of forming the dummy wiring to the dummy connection hole and the dummy wiring groove.