HK1036544A - Picture-in-guide generator - Google Patents

Description

Picture-in-newspaper generator

This application claims priority from U.S. application No.60/072,428, filed on 26/1/1998, the disclosure of which is hereby incorporated by reference in its entirety.

The disclosures of the following patent applications are also incorporated herein by reference in their entirety: application No.08/475,395 filed on 7/6/1995; international application W096/07270; application No.60/053,330 filed on 21/7/1997; application No.60/061,119 filed on 6/10/1997; and application No.60/055,237 filed on 8/12/1997. The publication "CTC 140 Picture-IN-Picture System (CPIP) Technical Training Manual" ("The CTC140 Picture IN Picture System (CPIP) Technical Training Manual", Thomson Consumer Electronics, Inc. Indianapolis, IN) is also listed as a reference.

Electronic Program Guides (EPGs) provide television viewers with updateable television schedule information in the form of on-screen graphical displays. The EPG may provide information on the scheduling of present and future broadcast programs as well as provide summaries of the television program content of some specific programs.

One particularly convenient EPG format is a picture-in-guide (PIG) display. The PIG display includes a large graphical program guide and a real-time video image of the viewed television program displayed in a small window therein. Such PIG displays offer many options to the viewer. The viewer can continue to watch the television program he was watching when he previously entered the guide while viewing the television schedule information in the guide. Alternatively, when the viewer's cursor passes through a program in the guide, the program displayed in the PIG window may be switched to the corresponding selected channel in the guide. The viewer may also scroll through the PIG display looking for more information about the program he is currently watching, such as start/stop times or program summaries, while continuing to watch the program embedded in the PIG window.

Typically, the PIG EPG display is generated using an EPG generator that includes: a microprocessor, a Vertical Blanking Interval (VBI) decoder/slicer, an on-screen display generator, a digital-to-analog converter (DAC), synchronization (synch) circuitry, and a memory disposed on one chip, and a picture-in-picture (PIP) generator, a DAC, synchronization signal circuitry, and microprocessor interface circuitry disposed on another chip.

The PIP generator causes the two video signals to produce a large background picture and a small embedded picture, respectively. This small picture is produced by decimating a sub-video signal, for example, writing every third pixel in every third decimated line into the image memory. By scanning this large picture normally and using a fast switch to scan this small picture image when the scanner is to the PIP window area of the display monitor screen, a composite display is produced with a large picture background and an embedded small picture. This fast switch must therefore operate at the line scan frequency of the display monitor.

However, for PIG displays, it is not necessary to provide two real-time video images, because the main portion of the display includes textual and graphical information, e.g., a program guide, rather than real-time moving video images. PIP fast switches are relatively expensive. Also, separate chips for the EPG generator and the PIP generator require more components, and thus are more difficult to integrate into household appliances, such as a television receiver, a VCR, a satellite receiver, and the like.

It is therefore desirable to integrate the devices necessary to provide a PIG display in a single chip.

The invention provides a picture-in-picture generator having an output adapted to drive a display monitor and an input adapted to receive a television signal. The display generator feeds the drive signal to this output in synchronism with the display monitor. EPG information is extracted from the television signal and stored in a memory. The pixel size of the television signal is reduced and stored in a memory. The EPG data and the television signal are retrieved from the memory and stored in the display generator. EPG data and television signals are fed from a display generator to an output in a continuous data stream to produce a picture-in-picture display on a monitor. Preferably, the picture-in-picture generator is implemented on a single integrated circuit chip.

The best mode for carrying out the invention is illustrated in the accompanying drawings, in which:

FIG. 1 illustrates a program guide display in a Picture In Guide (PIG) format;

fig. 2 is a schematic diagram of a PIG generator according to an embodiment of the invention;

FIG. 3 is a diagram of a data structure within RAM according to one embodiment of the invention;

FIG. 4 is a diagram of YUV components of a standard color stripe video signal; and

figure 5 is a schematic diagram of an analog to digital conversion and clamping circuit according to one embodiment of the present invention.

In accordance with the present invention, a picture in Picture (PIG) generator is configured to produce a PIG display on a television screen or computer monitor. There are generally two display types available in television systems using PIG generators. The first type is a full screen display of real-time images of broadcast television programs. The second type, the PIG display, includes background graphics and a real-time video image in one of the small embedded windows.

Fig. 1 illustrates a PIG display 10 of an Electronic Program Guide (EPG) including a graphic portion 12 and a picture window 14. The picture window 14, hereinafter referred to as the PIG window, contains a television (picture) image of a full screen video display of a television program, but is reduced in size, typically to one third in both width and height, that is, 1/9 which is the full screen size. Another possible screen displayed by the PIG system is a full screen graphical display.

The graphics portion 12 of the PIG display 10 occupies a large portion of the screen. The graphical section typically includes several different colors of text, icons, and background graphics. The graphics may include a highlight of text or a partial area of the screen. In an EPG system, the viewer can typically browse through different guides without changing the television program displayed in the PIG window 14. In some EPG systems, when the viewer places cursor 16 over a different channel identifier 18 or program title 20 in the graphical section, the system automatically tunes the associated tuning circuit 50 to the selected channel and displays the program broadcast on that channel in the PIG window 14.

In accordance with a preferred embodiment of the present invention, the components necessary to form the PIG display 10 are all configured on a single chip for incorporation into a television receiver, VCR, stand-alone unit, or satellite receiving device, etc. By configuring all of the components on a single chip, the overall package size can be reduced, and the gate count and bus interface size of the chip can be reduced.

FIG. 2 is a schematic diagram of some of the components of a preferred embodiment of the present invention configured on a single chip 21. A microprocessor 22, a memory controller or Direct Memory Access (DMA) device 24, a Random Access Memory (RAM)26, a synchronous regeneration (synchronization signal) circuit 28, an analog-to-digital conversion (ADC) and clamp circuit 30, a PIG window generator 32, a display generator 34, and a digital-to-analog conversion (DAC) circuit 36.

Microprocessor 22 receives raw text data, such as EPG data, from a data source and writes it to RAM 26. For example, the EPG data may be embedded in the vertical blanking interval of a television signal received by the television tuner 50 and extracted by the VBI decoder/slicer 37. Preferably, the RAM 26 has a storage capacity of 4 mbit or more, and includes a data RAM 31 for storing text data and a Video RAM (VRAM)31 for storing video data, and a free area serving as a work area between the data RAM 31 and the VRAM33, as shown in fig. 3. Microprocessor 22 organizes the data storage within RAM 26 and may specify addresses for text data and video data. However, the microprocessor 22 is relatively slow compared to the video processing hardware, such as the PIG window generator 32 and the display generator 34. Thus, the microprocessor 22 typically only processes access data and text data, not video data. The microprocessor communicates bi-directionally with the DMA 24. The microprocessor 22 communicates with a DMA24 and accesses a RAM 26 via a data bus and an address bus.

Preferably, there is only one RAM. This RAM 26 is accessed by three different components, a microprocessor 22, a PIG window generator 32 and a display generator 34. This leaves the RAM highly accessible, as all three components may compete for access to the RAM at the same time. However, only one sample of as many bits (e.g., 8 bits for a 516 KX8bit RAM) may be accessed per access cycle. To address arbitration between components, a multiplexer is necessary. Accordingly, the microprocessor 22, the PIG window generator 32, and the display generator 34 each access the RAM through the DMA 24. The DMA24 is a multiplexing and arbitration circuit that allows these three components to share the RAM 26 by accessing them in sequence. The DMA24 includes some buffer memory for temporarily storing data input from out-of-order components between access cycles. The DMA24 stores the text data and video data in the RAM 26 at the correct addresses and then retrieves the correct data from the RAM based on the selected address if necessary.

As described above, RAM 26 preferably has a storage capacity of 4 mbit or more, with a high access load. One way to accommodate this high access load and speed up the transfer of data is to select a 256KX 16 bit RAM instead of a 512 KX8bit RAM so that the DMA24 can access more information per access cycle, i.e., 16 bits instead of 8 bits. The system receives a video signal from the tuning circuit 50. The horizontal and vertical (h-and v-) sync signals separated from the video signal are supplied to the sync signal circuit 28. The synchronization signal circuit includes a pixel clock 28. The pixel clock determines the x and y coordinates that each pixel displays on the screen. The y-coordinate corresponds to the screen scan line number and the x-coordinate corresponds to the pixel number in each scan line.

The video portion input from the tuner circuit 50 is converted into YUV analog video signals by a chrominance processor 52 within the television receiver. This is an intermediate signal conversion between the input video typically used in television systems and the RGB signals displayed on a Cathode Ray Tube (CRT) 62.

Fig. 4A, 4B and 4C illustrate YUV components 54, 56, 58, respectively, of a standard color stripe video signal. Component 54 is the luminance (Y) signal with horizontal sync pulse 55. Component 56 is the color signal (V). Component 58 is the trailing region of the chrominance signal (U) for video clamping. Each component of the signal is converted to digital form by ADC/clamp 30 (see figure 5 for details). The clamping portion of the ADC/clamp circuit 30 reduces distortion in the signal due to, for example, low frequency noise and dc jitter in the converted signal.

The PIG window generator 32 receives a digital YUV video signal corresponding to a full screen video image. The PIG window generator extracts video data, reduces the entire screen size, sends the video data to the DMA24, and stores the video data in the VRAM. To extract the video data, the PIG window generator 32 selects, in conjunction with the synchronization signal circuit 28, one scan line from, for example, every third scan line and one pixel from this scan line every third pixel (that is, 1/3) to send to the DMA24 for storage in the VRAM 33. Other decimation ratios are possible, such as 1/4, to form different sized PIG windows.

The correct address for storing the video data of the PIG window generator 32 in the VRAM33 is determined by the address translation circuit 40, which is preferably incorporated in the DMA 24. Using the synchronization signals from the synchronization signal circuit 28 and the pixel clock 38, the address mapping circuit 40 stores the video data corresponding to each pixel on the cathode ray tube at the correct address within the VRAM for later display access. This process is commonly referred to as "bit mapping".

The display generator 34 includes a graphics generator for formatting the text font, icon, color and highlighting, and background graphics for display on the PIG display 10. The graphics data is provided to the address mapping circuit 40 which, in cooperation with the DMA24, stores the video data at addresses within the VRAM33 corresponding to the coordinates of the pixels on the screen.

A case of generating the PIG display 10 (fig. 1) according to the present preferred embodiment will now be described. Microprocessor 22, in response to viewer command means 70, such as an infrared remote control, accesses data RAM 31 for a given PIG EPG display to read the appropriate text data for that display from the original text data. The microprocessor 22 configures the text data for display, along with the appropriate address for displaying the text, for transmission to the DMA24 for storage in the VRAM 33.

All of the video data used to form the PIG display 10, including the text and graphics data for the graphics portion 12 and the video image data for the PIG window 14, is stored in the VRAM33, as described above. The display generator 34 reads the VRAM content organized in advance in cooperation with the address mapping circuit 40 and the synchronizing signal circuit 28, and generates an image for display on the screen of the CRT 62. The data of each pixel to be displayed on the screen is stored in the VRAM33 at addresses corresponding to the x and Y coordinates of this pixel on the screen. The display generator 34 reads corresponding data from the VRAM33 for each pixel in turn as determined by the pixel clock 38 using the synchronization signal from the synchronization signal circuit 28. The synchronization signal is generated by the synchronization signal circuit 28 from the h and v synchronization signals in the input video.

Although it is preferable to store the information groups or frames of the entire screen in the VRAM33 in the form of bit maps at a time, it is also possible to store less than the entire screen at a time, that is, only a part of the screen, and the display processing is actually performed in units of pixel groups smaller than the entire screen.

The display generator 34 converts the digital YUV signal for each pixel and sequentially outputs the converted signal to the DAC circuit 36 in a continuous data stream to produce a picture-in-picture display similar to that shown in fig. 1 on the screen of the CRT 62. The DAC circuit converts the data into analog YUV video signals. The analog YUV video signal is then converted to an analog RGB signal by an RGB conversion circuit 60 in the television receiver and displayed on the screen of a CRT 62.

In another embodiment of the invention, the RAM 30 is located off-chip and is connected to the DMA24 by a data bus.

The tuning circuit 50, chrominance processor 52, RGB converter 60, CRT 62 and viewer command device 70 are all part of a television receiver. In other words, these components have a dual role in displaying both television signals, typically in full screen format, and also in poster format. Other components are unique to the newspaper picture format.

This design of the PIG circuit on a single chip 21 according to the invention provides more economical components, small size and low gate count. The present invention reduces the total gate count by requiring only a single gate array for each of microprocessor 22, synchronizing signal circuit 28, DAC circuit 36 and DMA24, rather than two gate arrays for each of these components configured on separate PIP and EPG panels as is the case for known television systems that produce PIG displays. It should also be noted that the display generator 34 feeds both the image information and the EPG information to the CRT 62 in a continuous data stream under the control of the pixel clock 38 and the synchronization signal circuit 28. Therefore, a video (i.e., moving picture) image can be generated in the EPG display without a high-speed switch.

The embodiments of the invention described are only preferred and illustrative embodiments of the inventive arrangements and the scope of the invention is not limited to such embodiments. Those skilled in the art can devise various other arrangements within the scope of the present invention, which are within the spirit of the present invention. For example, separate RAMs may be used to store EPG data and the reduced picture television signal. Furthermore, the invention can also be used in digital television transmission systems, in which case the ADC, DAC and VBI slicer can be omitted.

Claims (4)

1. A picture-in-newspaper generator comprising:

an output adapted to drive a display monitor;

a display generator for feeding drive signals to said output in synchronism with the display monitor;

an input adapted to receive television signals;

means, coupled to said input, for extracting EPG information from said television signal;

means for storing the EPG information in a memory;

means for scaling down the pixel size of said television signal;

means for storing the reduced pixel size television signal in a memory;

means for retrieving said EPG data and television signals from memory;

means for storing the retrieved EPG data and television signals in the display generator; and

means for feeding EPG data and television signals from said display generator to said output in a continuous data stream for producing a picture-in-guide display on said monitor.

2. The picture-in-picture generator of claim 1, implemented in a single integrated circuit die.

3. The picture-in-picture generator of claim 2, wherein said extracting means is a VBI decoder.

4. The picture-in-guide generator of claim 3, wherein the memory comprises one or more RAMs.