HK1055875B - Method and apparatus for simultaneous recording and displaying two different video programs - Google Patents

Description

Method and apparatus for simultaneously recording and displaying two different video programs

Background

Technical Field

The present invention relates to television, and more particularly, to a signal processing technique for simultaneously recording and displaying two different video programs.

Description of the background Art

Television viewers desire to record and view programs from two different video sources simultaneously, such as satellite television programs and standard terrestrial broadcast programs. However, different video sources produce video signals having different horizontal and vertical synchronization rates. Thus, two separate video decoder and display generation systems are required to enable viewing of one program while producing an output signal of another program that can be recorded and viewed in a picture-in-picture (PIP) display. Such a system requires the hardware of two television receivers. Thus, televisions with this capability are very expensive.

Accordingly, there is a need in the art for a television set having a video decoder system that is capable of displaying a main picture from a first video signal while producing a recordable signal from a second video signal and producing a PIP picture for use in monitoring the recordable signal.

Summary of The Invention

The disadvantages of the prior art are overcome by a method and apparatus for simultaneously recording and displaying video signals from two different video sources. The apparatus includes a primary channel processing circuit for a primary signal, a secondary channel processing circuit for a secondary signal, and a common circuit for processing the primary and secondary signals. The common circuitry includes a digital video variable length pipeline and a decoding pipeline that decodes primary and secondary digitally encoded (compressed) video signals.

The main channel processing circuit processes the main video signal to form a display of a main image. The secondary channel processing circuit processes a second video signal that, when selected for recording, also forms a PIP picture for display in combination with the primary picture. The secondary channel processing circuit also processes the primary video signal, which when selected for recording, also forms a PIP picture for display in combination with the primary picture. In this way, the PIP constitutes a recording monitor.

The primary decoded video signal or the secondary decoded video signal is also provided to a recording output to which a recorder may be connected to receive the selected first or second decoded video signal for recording.

During the decoding process, the primary channel processing circuit and the secondary channel processing circuit utilize a primary clock signal (the faster one) derived from the primary signal. During recording, the signals for external recording and the recording monitoring PIP are clocked by the main clock signal or by a secondary clock signal independent of the main clock signal.

When recording the main signal (and providing the PIP), an external recording is performed by driving a Digital Encoder (DENC) in Vslave mode with the Vmain signal from the main raster generator. When recording the secondary signal, the DENC receives a start reset signal to read in the secondary signal vertical rate parameter and generates a vertical synchronization signal by the DENC itself.

In PIP only mode (recording switch off), the secondary channel uses the main signal clock. In the recording mode, a primary signal clock or a secondary signal clock is used depending on whether the signal source being recorded is the same or different, respectively. In the recording mode, the video signal is sent to the image processor for capture and display, and passed to the DENC for recording. The captured image is then restored without further reformatting for display as a "record monitor" PIP image. The PIP picture is preferably slightly larger than a standard PIP picture, preferably identified as a recording monitoring PIP. Since the recorded image is reproduced according to the recording output timing, when the PIP is provided as an overlay on the main signal output, some images may need to be skipped or repeated.

In one form, because there is only one VCXO generated by the reference clock according to the video decoding process, the secondary signal uses a clock derived from the primary signal clock but different clocks as needed (e.g., 81MHz for a 60Hz primary signal and 27MHz for a 59.95MHz recording). The secondary signal requires a form of clock recovery because the studio clock for the video of the secondary signal may be slightly offset from the studio clock for the video of the first signal. If the secondary signal video is derived from an analog source, the buffer level of the captured image is used to indicate that the DENC clock is too fast or too slow. When the secondary signal is a digital signal, the local counter is sampled according to the arrival time of the clock reference carrying the transport packet. A comparison between the sampled clock and the transmitted clock reference is used to indicate whether the DENC clock is too fast or too slow. The secondary signal clock is generated using a PLL (phase locked loop) and a programmable frequency divider, wherein the time base is recovered as a reference using the main signal as the recovered time base. The PLL divider is changed as necessary to match the desired frequency of the generated clock and secondary signals.

Drawings

The teachings of the present invention can be more readily understood by considering the following detailed description in conjunction with the accompanying drawings, in which:

FIG. 1 is a block diagram of one form of a video processing system according to the principles of the present invention;

FIG. 1A is a block diagram of another form of a video processing system in accordance with the principles of the present invention;

FIG. 1B is a block diagram of another form of a video processing system in accordance with the principles of the present invention;

fig. 2 is a detailed block diagram of a video decoder device that may be used in the systems of fig. 1A, B in accordance with the principles of the present invention; and

FIG. 3 is a table of exemplary clock frequencies that may be processed and/or generated by the present invention, representing various final parameters; and

fig. 4 is a flow chart of an exemplary method in accordance with the principles of the invention.

To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures.

Detailed Description

Referring to fig. 1, a block diagram of a video processing system, generally designated 50, operable to receive, decode, record, and/or display video signals from various video sources is shown. In particular, system 50 is primarily concerned with decoding and/or processing a pair of video signals (video 1, video 2) coupled thereto. Each of the video signals may be an analog signal or a digital signal. Thus, the term "decoding" as used herein includes both processing/decoding in the case of analog signals and decompression/decoding in the case of digital (i.e., digitally encoded video signals).

In the case of digital signals, the system 50 uses one decoder for processing a pair of digital signals, or a pair of decoders, one for each signal. Furthermore, although the digital encoding format may be decoded, the present invention will be discussed in terms of signals encoded using the Motion Picture Experts Group (MPEG) standard. These signals may be provided by satellite television receivers, High Definition Television (HDTV) receivers, digital cable television systems, digital terrestrial television antennas, and the like. In the case of analog signals, any analog format, such as NTSC, PAL, SECAM or the like, may be decoded using system 50. Thus, while any analog format may be decoded, the present invention will be discussed in terms of signals encoded using the NTSC standard. These signals may be provided by television receivers, cable television systems, terrestrial television antennas, television components, and the like.

The system 50 includes a decoder device 100, a display 52 (e.g., a television, television monitor, etc.), and a recorder 58 (e.g., a Video Cassette Recorder (VCR), video cassette recorder (VTR), digital recorder, etc.). In the system 50, each of the above-identified elements, i.e., the decoder arrangement 100, the display 52, and the recorder 58, are separate elements and are connected to one another by patch cords or other suitable conductors/connectors. Decoder apparatus 100 decodes both video signals using common decoding circuitry and dual timing circuitry to produce a signal that is the main picture 54 (e.g., from video 1) and a signal for recording on recorder 58 and display in PIP picture 56 of main picture 54 on display 52. In this way, the system 50 simultaneously generates video signals for display and for recording and has the ability to monitor recordable signals in PIP pictures. By using a common circuit for processing both video signals, the decoder arrangement can be manufactured at a lower cost than prior art decoder arrangements. Also, the present invention utilizes separate clock recovery/generation circuits for generating clocks for the main video and the recording/PIP video, in addition to a common decoding circuit.

Referring to FIG. 1A, there is shown another form of video processing system in accordance with the principles of the present invention, generally designated by the numeral 50A, having the same operation and function as the video system 50 shown in FIG. 1, and described in detail below. The system 50A includes a decoder device 100, a display 52 (e.g., a television, television monitor, etc.), and a recorder 58. However, in system 50A, decoder device 100 and display 52 are integrated into one element 60, while recorder 58 is a separate element. The register 58 and the integrated component 60 are connected by a patch cord or other suitable lead/connector.

Referring to FIG. 1B, there is shown another form of video processing system in accordance with the principles of the present invention, generally designated by the numeral 50B, having the same operation and function as the video system 50 shown in FIG. 1, and described in detail below. The system 50B includes a decoder device 100, a display 52 (e.g., a television, television monitor, etc.), and a recorder 58. However, in system 50B, decoder device 100 and recorder 58 are integrated into one element 70, while display 52 is a separate element. The display 52 and the integrated component 70 are connected by a patch cord or other suitable lead/connector.

Referring now to fig. 2, a detailed block diagram of the decoder arrangement 100 shown in fig. 1A, B is shown. Decoder device 100 includes primary channel processing circuitry/logic 148, secondary channel processing circuitry/logic 150, and common circuitry/logic 152. The main channel processing circuitry/logic 148 is coupled to the main channel at port 102 such that the main channel processing circuitry/logic 148 receives a main channel or main signal, typically from a main tuner (not shown). Secondary channel processing circuit/logic 150 is coupled to the secondary channel at port 104 such that secondary channel processing circuit/logic 150 receives a secondary channel or secondary signal, typically from a secondary tuner (not shown). However, as described below, the secondary channel processing circuit/logic 150 may receive the primary signal as a "secondary channel" for processing when the primary signal is selected for recording and the secondary signal is not selected.

A main signal, or more generally main data, is provided to a main data input of a main channel memory buffer 106 as part of main channel processing circuitry/logic 148. The main signal may be a digital signal or an analog signal, and may include a video signal and/or an audio signal. It should be understood, however, that the present invention relates primarily to video signals and will therefore be discussed in terms of video only. In addition, the main (video) signal typically includes a channel previously determined by a main tuner (not shown) from a plurality of channels.

When the main signal is an analog signal, the main signal is provided to a FIFO (first in first out) memory or buffer 108. When the main signal is a digital signal, it is supplied to an MPEG video VLD (variable length decoder) pipeline 110, which decodes the variable length codes of the MPEG signal. The variable length decoded main signal is then provided to the MPEG video decoding pipeline 112. The MPEG video decoding pipeline 112 may operate to decode MPEG encoding of the variable length decoded main signal. In accordance with the MPEG principles, the MPEG video decoding pipeline 112 stores decoded MPEG frames of the main signal in the main channel storage buffer 106. The MPEG video decoding pipeline 112 performs motion compensation using some previously decoded MPEG frames of the main signal and performs the same operations in decoding the incoming MPEG main signal from the MPEG video VLD pipeline 110, so that there is a bi-directional arrow between the MPEG video decoding pipeline 112 and the main channel storage buffer 106. The decoded MPEG frames of the main signal are stored back in the correct order in the main channel storage buffer 106.

The secondary signal is provided to the PIP/record input of a secondary channel memory buffer 114 that is part of the secondary channel processing circuitry/logic 150. The secondary signal may be a digital signal or an analog signal and may include a video signal and/or an audio signal. It should be understood, however, that the present invention relates primarily to video signals and will therefore be discussed in terms of video only. In addition, the secondary (video) signal typically includes a channel previously determined by a secondary tuner (not shown) from a plurality of channels.

When the secondary signal is an analog signal, the secondary signal is provided to a FIFO (first in first out) memory or buffer 116. When the secondary signal is a digital signal, it is provided to an MPEG video VLD (variable length decoder) pipeline 110, which decodes the variable length codes of the MPEG signal. The variable length decoded sub-signal is then provided to the MPEG video decoding pipeline 112. The MPEG video decoding pipeline 112 may operate to decode MPEG encoding of the variable length decoded secondary signal. In accordance with the MPEG principles, the MPEG video decoding pipeline 112 stores the decoded MPEG frames of the secondary signal in the secondary channel memory buffer 114. The MPEG video decoding pipeline 112 performs motion compensation using some previously decoded MPEG frames of the sub-signal and performs the same operations in decoding the input MPEG sub-signal from the MPEG video VLD pipeline 110, so that there is a bi-directional arrow between the MPEG video decoding pipeline 112 and the sub-channel storage buffer 114. The decoded MPEG frames of the secondary signal are stored back in the correct order in the secondary channel memory buffer 114.

The MPEG video VLD pipeline 110 is part of the common circuitry/logic 152 and performs variable length decoding of the primary and secondary signals in an interleaved manner, thereby enabling one VLD decoder to perform variable length decoding of both video signals (i.e., the primary and secondary signals).

The MPEG video decoding pipeline 112 is also part of the common circuitry/logic 152 and performs MPEG video decoding of the primary and secondary signals. With interleaving, the MPEG video decoding pipeline 112 decodes both video signals and returns the decoded video frames to respective buffers 106 and 114. Because the MPEG video coding pipeline 112 is common to both video signals, both signals are coded using the faster of the two coding rates, i.e., a 60Hz coding rate is used in preference to a 59.94Hz coding rate. Of course, if the two video signals have the same coding rate, then the pipeline 112 uses the coding rates of the two signals. In the case of different decoding rates, the slower input video stream is processed faster than necessary. Thus, the decoding process for the slower stream is sometimes stopped, ensuring that a data underflow condition does not occur in the compressed data buffer (buffer 106 or 114).

The MPEG video decoding pipeline 112 connects a signal (e.g., video 1) that will form a main image to the main channel storage buffer 106 and connects a signal (e.g., video 2) that will form a PIP image and be recorded to the sub-channel storage buffer 114. Which signal is the main image and which signal is the PIP image is typically selected by the viewer via a remote control or other interface (not shown).

Buffer 106 and buffer 114 are coupled to respective first-in-first-out (FIFO) memories 108 and 116. The access (read and write) process of the two FIFO buffers 108 and 116 is controlled by a clock generator 122. Clock generator 122 generates a clock signal for each FIFO buffer 108 and 106 derived from the clock signal generated by reference clock generator 124. The clock signal generated by the reference clock generator 124 is locked to the main channel timing signal.

The output of the FIFO buffer 108 is provided to the input of a main channel frame converter 118, which is synchronized by a clock signal from a clock generator 122. The output of the FIFO memory buffer 116 is provided to the input of a PIP/record channel frame converter 134 which is synchronized by the clock signal from the clock generator 122. Frame converter 134 is referred to as a "PIP/record channel" frame converter because the secondary channel/signal is not always a channel/signal that is to be recorded and therefore not provided as a PIP. When the main channel/signal is selected for recording, then the main channel/signal is provided as a PIP.

The output of each converter 118 and 134 is coupled to a respective FIFO memory 120, 136. These FIFOs buffer the video frames of the respective signals, thereby ensuring that the frames are synchronized with the display timing signal. Access to FIFO 120 is controlled by a reference clock from the main channel synchronized with reference clock generator 124. Access to the FIFO 136 is controlled by a reference clock from the main channel synchronized with the reference clock generator 124 in the case of a main channel selected for recording or by a secondary clock from the secondary channel clock generator 132 in the case of a secondary channel/signal selected for recording. A second channel clock generator 132 is coupled to the second channel/signal.

The reference clock signal from the reference clock generator 124 is also coupled to the master grating generator 138. The main raster generator 138 generates horizontal (H) and vertical (V) synchronization signals that assist the display of a main image on a cathode ray tube or liquid crystal display, which are coupled to the display generator 126 for controlling the raster scanning of the pixel data. The pixel data input to the display generator 126 comes from the FIFO memory 120 (i.e., the primary channel/signal) and the FIFO memory 136 (i.e., the secondary channel/signal or the primary channel/signal, depending on which channel/signal is selected for recording).

In addition, the display generator 126 generates graphics on the screen that can be recalled from the graphics memory 128 and that control the insertion of the PIP picture into the main picture. The display, including on-screen graphics, PIP images and main images, is coupled through a display output port or output to a main digital-to-analog converter (DAC)130, which produces an analog display for viewing on a television screen.

The main grating generator 138 also provides the Vmain signal to the secondary channel controller 140. The secondary channel controller 140 may also be operable to output a Vmain signal to either the digital-NTSC encoder 142 or the secondary channel controller 140 by receiving a Vsecond signal from the microprocessor 144, a microcontroller, or the like, or to output a Vstart-up signal to the digital-NTSC encoder 142 in response to receiving the Vsecond signal from the microprocessor 144, depending on which channel/signal (i.e., primary channel/signal or secondary channel/signal) is selected for recording. In accordance with one aspect of the present invention, when the primary channel/signal is selected for recording (and thus provided as a recording monitor PIP), then the Vmain vertical sync signal is provided to digital-NTSC encoder 142 by secondary channel controller 140, and when the secondary channel/signal is selected for recording (and thus provided as a recording monitor PIP), then the Vsecond signal triggers the Vstart-up signal, causing digital-NTSC encoder 142 to generate the vertical sync signal based on the incoming/secondary clock and/or the secondary channel/signal.

The clock signal for the FIFO memory 136 is controlled by the switch 146 in response to the selection of the secondary channel/signal or the selection of the primary channel/signal for recording. In one aspect according to the invention, when a secondary channel/signal is selected for recording, the secondary channel/signal provided on port 104 is processed by secondary channel processing circuitry/logic 150 or/and common circuitry/logic 152 and provided to FIFO memory 136. The switch 146 is caused to select the secondary clock signal from the secondary channel clock generator 132, which is provided to the FIFO memory 136. The FIFO memory 136 receives frames formed by the secondary channel/signal from the PIP/record channel frame converter 134. The rate at which frames are transmitted from PIP/record frame converter 134 to FIFO memory 136 is controlled by digital-to-NTSC decoder 142, as shown by the dashed line between the two circuits/logic blocks. digital-NTSC decoder 142 is also synchronized by the secondary clock signal from secondary clock generator 132. The mark "record" between the FIFO memory 136 and the digital-NTSC decoder 142 is to be input to the digital-NTSC decoder 142. The label "PIP" indicates that the signal is to be input to display generator 126 and graphics memory 128 for output to main DAC 130 for display as a PIP. At the same time, the secondary signal from the FIFO memory 136 is provided to the display generator 126 and the graphics memory 128 and output to the display output through the main DAC 103 for display on a display (not shown).

In accordance with another aspect of the invention, when the primary channel/signal is selected for recording, the main processed signal from the primary channel memory buffer 106 is caused to be provided to the secondary channel memory buffer 114 and, through appropriate components, to the FIFO memory 136. The FIFO memories 136 are synchronized by the reference clock generator 124 from the main channel lock through the switch 146. At the same time, Vmain is provided to digital-NTSC decoder 142 via secondary channel controller 140 to provide vertical synchronization pulses for the primary channel/signal.

In addition, digital-NTSC decoder 142 receives the master clock signal from master clock generator 124. The main channel/signal from the FIFO memory 136 is also provided to the display generator 126 and graphics memory 128 for output on the display as a PIP.

In accordance with the principles described herein, reference is now made to FIG. 3. In fig. 3, a table of various exemplary clock frequencies generated by a primary channel reference clock generator and a secondary channel reference clock generator is shown to assist in video signal output when the video signal source and crystal reference clock have or do not have a slight difference. The respective clock frequencies are used by the respective elements in the manner described herein.

Operation of

Referring to fig. 4, there is shown a flow chart of one exemplary embodiment of the manner of operation of the present invention in accordance with the principles described herein. It should be understood at the outset that the order and/or sequence of the manner of operation illustrated in flowchart 160 may be varied. Moreover, all of the steps shown and/or described may or may not be required for operation thereof.

A primary channel or signal is received at block 162. In addition, a secondary channel or signal is received at block 164. Thereafter, the primary channel/signal and the secondary channel/signal are processed at block 166. The main channel is applied to the display as a main image for display using a main clock signal derived from the main channel/signal at block 168. At block 170, a channel/signal (either a primary channel/signal or a secondary channel/signal) is selected for recording. If the main channel is selected for recording, the main channel is provided as a PIP in the main picture at the recording output port or output using the main clock, block 172. If the secondary channel is selected for recording, the secondary channel is provided at the recording output port or output as a PIP in the main picture using a secondary clock independently derived from the main clock at block 174.

Although a number of embodiments have been described and shown that are included in the teachings of the present invention, those skilled in the art will be readily able to derive other different embodiments that are included in the teachings of the present invention.

Claims (14)

1. A method for viewing a first video signal and a second video signal to be recorded, comprising the steps of:

(a) decoding a first video signal using a first clock reference;

(b) coding a second video signal using the first clock signal;

(c) providing a first decoded video signal as a main image to a display using the first clock signal; and

(d) the second decoded video signal is provided to the recording output port and the display as a PIP in the main picture using the second clock signal.

2. The method of claim 1, wherein the steps of coding the first video signal and coding the second video signal are performed by a common video coder.

3. The method of claim 1, wherein the first and second video signals are digitally encoded video signals.

4. The method of claim 3, wherein the steps of decoding the first video signal and decoding the second video signal are performed by a common video decoder pipeline operable to decode video signals encoded in a Moving Picture Experts Group (MPEG) format.

5. The method of claim 1, wherein the second decoded video signal is provided to the display as a PIP in the main picture using the second clock when the second video signal is selected for recording, the method further comprising the steps of:

a second video signal is coded using the first clock signal.

6. The method of claim 5, wherein the steps of coding the first video signal and coding the second video signal are performed by a common video coder.

7. The method of claim 5, wherein the first and second video signals are digitally encoded video signals.

8. The method of claim 7, wherein the steps of decoding the first video signal and decoding the second video signal are performed by a common video decoder pipeline operable to decode video signals encoded in a Moving Picture Experts Group (MPEG) format.

9. An apparatus for monitoring a recording of a video signal, comprising:

a video decoder pipeline operable to decode the encoded first and second video signals;

a first channel processing circuit, coupled to the video decoder pipeline, for generating a main picture from the first decoded video signal for display using a first clock signal;

a second channel processing circuit, coupled to the video decoder pipeline, for generating a second decoded video signal;

a selection device for selecting the first video signal to record or selecting the second video signal to record; and

means for providing the second decoded video signal as a PIP in the main picture for display using the second clock signal when the second video signal is selected for recording and providing the first decoded video signal to the display as a PIP in the main picture for display using the first clock signal when the first video signal is selected for recording.

10. The apparatus of claim 9, further comprising: a reference clock generator operatively coupled to said first channel processing circuit and said second channel processing circuit and operable to generate said first clock signal; and

a second channel clock generator coupled to the means for providing and operable to provide a second clock to the second decoded video signal when the second video signal is selected for recording.

11. The apparatus of claim 9, further comprising a digital encoder for generating an analog signal for recording.

12. The apparatus of claim 11, wherein the digital encoder is operable to generate an internal vertical synchronization signal when the second video signal is selected for recording, and is otherwise operable to receive an externally generated vertical synchronization signal when the first video signal is selected for recording.

13. The apparatus of claim 12, further comprising a vertical synchronization signal generator operable to generate an externally generated vertical synchronization signal based on the first video signal.

14. The apparatus of claim 9, wherein the video decoder pipeline is operable to decode video signals encoded in a Moving Picture Experts Group (MPEG) format.