GB1494841A - Data communications system - Google Patents

Abstract

1494841 Data transmission; master and slave systems NCR CORP 14 April 1975 [24 April 1974] 15158/75 Heading H4P [Also in Division G4] A data handling system includes a central unit, a plurality of addressable terminals each of which may be active or inactive, and a communications adapter coupled to the central unit and arranged to tramsit messages to the terminals, the adapter including a counter arranged to address the terminals and recirculating storage means arranged to store bits provided by the central unit and representing the activity states of the terminals, the arrangement being such that a message is sent to an addressed terminal only if it is active. The system includes a central processor coupled to groups of terminals via respective adapters, each terminal including an input keyboard, a digit display, and a microprocessor arranged to operate ON or OFF-LINE from the central processor. Each terminal may include other devices, e.g. magnetic credit card readers, coin dispensers &c. Each adapter may be connected to up to 16 terminals each of which receives all messages transmitted and, on receiving a message addressed to it, responds with a message. All messages have a similar format including 8 sync bits, 4 address bits identifying a terminal, further address bits identifying a unit within a terminal, data bits, 2 function bits indicating the mode, and check bits including a cyclic redundancy check bit and a 1-bit module two count of the message number. The system is described in some detail in block diagram form and includes features to compare received address bits with stored address bits, and received check bits with generated check bits. Communication is in two modes, viz "polling" where the terminals are addressed in sequence and "exchange" where a selected terminal is addressed. During polling a counter produces the addresses of successive terminals, an activity bit at the output of a recirculating shift register being examined for each address. If the bit indicates an active terminal a message is sent and a timer is set. On receipt of a message a terminal responds. If the adapter recognizes a response before the timer times out and the message is correct all is well. If however the message is incorrect the adapter interrupts the central processor which normally instructs the adapter to repoll the terminal. A similar procedure occurs if no response is received before the timer times out. If after three attempts no valid response is received the control unit regards the terminal as inactive, resets the activity bits accordingly, and resets the address counter to restart the polling sequence. Data transmitted both from the adapter and the terminals is retained following transmission for possible re-transmission in the event that the first transmission is not received correctly. If for any address the activity bit indicates an inactive terminal, no message is sent and the address counter is incremented to address the next terminal. The procedure for an exchange message is generally similar except that the terminal addresses are derived directly from the central unit and the activity bits are not considered. Operation at the adapter and terminals are controlled by sequence counters stepping through sequences of states in response to clock signals and the status of the system. The clock signals are also used to control message transmission and reception, messages being transmitted serially in Manchester code.