DE102019126107A1 - MEMORY ARRANGEMENTS, METHODS FOR INITIATING A MEMORY, AND METHOD FOR USING A MEMORY - Google Patents

Abstract

According to one embodiment, a memory arrangement is described having a memory having a plurality of memory cells, wherein each memory cell has a material whose resistance can be changed, and wherein the memory is configured to store data based on a setting of the resistance of the material in the memory cells , and a memory control device, configured to carry out at least a first memory cell initiation process and a second memory cell initiation process, wherein a memory cell initiation process consists of a plurality of initiation operations, wherein for each initiation operation of a memory cell to which the memory cell initiation process is applied, a current pulse is supplied, wherein the first memory cell initiation process and the second memory cell initiation process differ in one or more electrical parameters, and set up a first To initiate part of the memory cells by means of the first memory cell initiation process and a second part of the memory cells by means of the second memory cell initiation process.

Description

Embodiments generally relate to memory arrangements, methods for initiating a memory, and methods for using a memory.

RRAM (resistive random access memory) memories consist of non-volatile memory cells, the resistance of which is initially very high-ohmic insulating after the processing of the wafer. So that these memory elements can be used, the memory cells all have to go through a formation process. The formation process firstly has a formation, after which the memory cells can be put into a low-resistance state, which typically encodes a 1, by a SET operation, and in a high-impedance state, which typically encodes a 0, by means of a RESET operation . The 0 as a high-resistance state is significantly lower-resistance than the initial state after wafer production.

The memory cells are then initiated. Depending on the intensity of the initiation, memory cells can then be written using so-called “soft” programming or require “hard” programming. However, the initiation of memory cells is associated with great effort and, in particular, an initiation that allows soft programming typically forms a significant part of the test time and test costs after the production of a memory chip.

Accordingly, efficient methods of initiating and utilizing a memory based on the change in resistance of a memory material, particularly an RRAM memory, are desirable.

According to one embodiment, a memory arrangement is provided having a memory having a plurality of memory cells, wherein each memory cell has a material whose resistance can be changed, and wherein the memory is configured to store data based on a setting of the resistance of the material in the memory cells , and a memory control device, configured to carry out at least a first memory cell initiation process and a second memory cell initiation process, wherein a memory cell initiation process consists of a plurality of initiation operations, wherein for each initiation operation of a memory cell to which the memory cell initiation process is applied, a current pulse is supplied, wherein the first memory cell initiation process and the second memory cell initiation process differ in one or more electrical parameters, and set up a first to initiate a part of the memory cells by means of the first memory cell initiation process and a second part of the memory cells by means of the second memory cell initiation process.

According to a further exemplary embodiment, a memory arrangement is provided having a memory having a plurality of memory cells, wherein each memory cell has a material whose resistance can be changed, and wherein the memory is set up to store data based on a setting of the resistance of the material in the memory cells is, and a memory control device, set up to carry out at least a first memory cell programming operation and a second memory cell programming operation, wherein in each memory cell programming operation of a memory cell to which the memory cell programming operation is applied, a current pulse is supplied, wherein the first Differentiate memory cell programming operation and the second memory cell programming operation in one or more electrical parameters, and set up, a first part of the memory cells by means of the first memory cell Programming operation and to program a second part of the memory cells by means of the second memory cell programming operation.

According to further exemplary embodiments, a method for initiating a memory and a method for programming a memory in accordance with the memory arrangements described above are provided.

The figures do not reflect the actual proportions but are intended to illustrate the principles of the various exemplary embodiments. Various exemplary embodiments are described below with reference to the following figures.

• 1 shows an electronic data processing device according to an embodiment.
• 2 shows an RRAM memory.
• 3 illustrates formation in an RRAM memory.
• 4th illustrates a formation process.
• 5 FIG. 10 shows a flow diagram illustrating a method for making and using a memory according to an embodiment.
• 6th shows a memory arrangement according to an embodiment.
• 7th Figure 12 is a flow diagram illustrating a method for initiating a memory.
• 8th shows a memory arrangement according to a further embodiment.
• 9 Figure 12 is a flow diagram illustrating a method of programming a memory.

The following detailed description refers to the accompanying figures, which show details and exemplary embodiments. These exemplary embodiments are described in such detail that the person skilled in the art can carry out the invention.

Other embodiments are also possible and the embodiments can be changed structurally, logically and electrically without departing from the subject matter of the invention. The various exemplary embodiments are not necessarily mutually exclusive, but rather various embodiments can be combined with one another, so that new embodiments arise. In the context of this description, the terms “connected”, “connected” and “coupled” are used to describe both a direct and an indirect connection, a direct or indirect connection and a direct or indirect coupling.

1 shows an electronic data processing device 100 according to an embodiment.

The electronic data processing device 100 can be a control unit or a microcontroller in a vehicle, for example an ECU (Electronic Control Unit) in a car. It can also be a security controller, a chip card IC (Integrated Circuit) of a chip card such as a smart card with any form factor, eg for a passport or for a SIM (Subscriber Identity Module), or an electronic data processing or communication device.

The electronic data processing device 100 has an (application) processor 101 and a memory array 102 on that by means of a (computer) bus 103 are connected to each other.

The storage arrangement 102 assigns a memory 105 and a memory controller 104 (typically referred to as a memory controller in English).

Depending on the design and function, the electronic data processing device can have further components such as input-output components, including communication components, e.g. for radio communication, and various interfaces, one or more further memories or one or more processors.

The processor 101 can run various software, such as an operating system 106 and an application (application) 107 that in one by the operating system 106 given environment. The application code and that of the application 107 processed data is in the memory 105 in a code memory area 108 or data storage area 109 saved. There can also be another memory area or another memory for the operating system 106 (or other software) are available, but this is not considered in the following for the sake of simplicity and is analogous to the memory areas 108 , 109 the application can be treated.

The memory controller 104 enables the processor (or other components) to access the memory 105 for reading stored data and writing (programming) data in the memory 105 .

The memory 105 is, according to one embodiment, an RRAM (resistive random access memory, also referred to as ReRAM) and accordingly has a large number of RRAM memory cells.

A typical RRAM memory cell has a memory material that can assume different resistances and is surrounded by two metallic electrodes. The switching or storage effect of RRAM is based on the movement of ions under the influence of an electric field or heat as well as the ability of the storage material to maintain the state of ion distribution. This leads to a measurable stored state of the memory cell resistance.

RRAM requires a lower voltage than conventional flash memories. It is bit changeable and is therefore suitable for use in both embedded and solid-state drives (SSDs). The RRAM cell structure offers high space efficiency and scalability. RRAM requires lower programming currents than phase change memory (PCRAM) or magnetoresistive memory (MRAM) with comparable data storage (retention) and service life. The following examples are described with reference to RRAM, but are generally applicable to memories that are based on a material whose resistance can be changed in several stages and whose memory properties vary depending on the resistance, for example also PCRAM (phase change RAM) and MRAM (magnetoresistive RAM).

2 shows an RRAM memory 200 .

The RRAM memory 200 has a plurality of memory cells 212 each of which is a storage element 202 and a transistor 210 has a plurality of word lines 208 , a variety of bit lines 206 and a variety of source lines 204 on.

Each of the storage elements 202 has a first electrode and a second electrode and may include a memory material disposed between the first electrode and the second electrode.

The RRAM memory 200 may further include a first supply connection for providing a first supply voltage and a second supply connection for providing a second supply voltage (both not shown).

In the RRAM memory 200 can use any word line 208 with at least one memory cell 212 from the multitude of storage cells 212 be connected. As in 2 shown, for example, each of the word lines 208 electrically conductive with at least one gate of the plurality of transistors 210 be connected (an example is shown in which each word line 208 connected to two gates, each gate being part of a transistor 210 is that part of a memory cell 212 the multitude of storage cells 212 is).

Any source line 204 can with at least one memory cell 212 from the multitude of storage cells 212 be coupled. As in 2 each of the source lines can be represented 204 electrically conductive with at least one source region of the plurality of transistors 210 be connected (an example is shown where each source line 204 connected to two source regions, each source region being part of a transistor 210 is that part of a memory cell 212 the multitude of storage cells 212 is.

Each transistor has a source region and a drain region, which can be formed, for example, as n + -doped regions in a p-doped substrate (or a p-well).

Every bit line 206 is with at least one memory cell 212 the multitude of storage cells 212 connected. As in 2 can be any of the bit lines 206 electrically conductive with at least one drain region of the plurality of transistors 210 be connected (an example is shown in which each bit line 206 connected to two drain regions, each drain region being part of a transistor 210 is that part of a memory cell 212 the multitude of storage cells 212 is).

In the RRAM memory 200 can each of the first electrodes of the plurality of memory elements 202 via a source line 204 the multitude of source lines 204 be connectable to the first supply connection. An electrically conductive contact from the first supply connection through one of the source lines 204 to the first electrode of each of the storage elements 202 can with one of the transistors 210 be established and / or interrupted. The source line 204 can be electrically connected to the source region of the transistor 210 be connected, and the drain region of the transistor 210 can be electrically connected to the first electrode of the memory element 202 the memory cell 212 be connected. The electrical conductivity between the source region and the drain region of the transistor 210 can be connected to the gate of the transistor 210 connected word line 208 to be controlled. In the in 2 The example shown can be the connection between, for example, the first electrode of the memory element 202 and the first supply connection (via the respective source line) by means of the to the gate of the respective transistor 210 connected word line can be controlled.

In the RRAM memory 200 can each of the second electrodes of the plurality of memory elements 202 via a bit line 206 the multitude of bit lines 206 connectable to the second supply connection, for example switchable or permanently connected in an electrically conductive manner. In the in 2 illustrated example, the second electrode of the memory element 202 electrically conductive with the bit line 206 be connected, which can be switchable or permanently electrically connected to the second supply connection.

Thus, each memory cell 212 the multitude of storage cells 212 by a combination of word line 208 and bit line 206 addressed to store or retrieve a bit.

RRAM is a type of RedOx (reduction-oxidation) memory. The nomenclature for switching between the memory states of a memory cell 202 is SET and RESET. In the case of bipolar RRAM, for example, the SET operation applies a positive voltage difference in order to put the memory cell into a low-resistance conductive state. The RESET operation applies a negative voltage difference in order to switch the cell from a low-resistance state to a high-resistance state.

The process of creating filaments within the RRAM material of a memory cell is known as “formation” and is one of the most important aspects when determining the switching behavior and the performance or quality of the memory cell.

3 illustrates a formation in an RRAM memory, for example in a memory cell 202 of the RRAM memory 200 out 2 .

In 3 is a memory cell in a first state 301 and in a second state 302 shown.

The first state illustrates the memory element in an initial state, ie before a formation was applied to the memory element (that is, for example, directly after its manufacture). Between the first electrode 303 (also called the lower electrode) and the second electrode 304 (also called the upper electrode) is the storage material 305 arranged. In this example, the storage material is a dielectric such as hafnium oxide or tantalum oxide.

The storage material 305 contains electrically conductive elements 306 , e.g. oxygen vacancies (VO), which can be viewed as positively charged elements. In the initial state 301 are few electrically conductive elements 306 present and most of the electrically conductive elements 306 are arranged in the vicinity of one of the electrodes, in the example in the vicinity of the first electrode 303 .

To form the memory cell 202 will have a higher voltage on the first electrode 303 and a low voltage to the second electrode 304 , i.e. the electrode that is further away from the electrically conductive elements 306 was created. Are the electrically conductive elements 305 closer to the second electrode 304 , can be used to form the memory cell 202 proceed in reverse, ie the polarity of the voltages can be chosen reversed.

By applying a first voltage to the first electrode 303 and a second voltage on the second electrode 304 , wherein the first voltage and the second voltage have a suitable polarity and a sufficiently large voltage difference, further electrically conductive elements 306 and are generated within the storage material 305 (re) arranged. In the example of 3 become the positively charged elements 306 towards the distant, negatively charged electrode 304 drawn. As a result, one or more electrically conductive filaments are formed, which ultimately become in the second state 302 through the storage material 202 extend and so an electrically conductive connection with low resistance between the electrodes 303 , 304 through the storage material 305 produce. Thus, the resistance of the memory cell between the two electrodes decreases 303 , 304 from high to low (e.g. from several mega-ohms in the initial state 301 down to the kilo-ohm range in the second state 302 ).

It is also possible that the electrically conductive filaments are not completely separated from the first electrode 303 to the second electrode 304 extend. The distance between the electrically conductive elements and the counter electrode 304 is however smaller in the second distance (and thus the electrical resistance smaller) than in the initial state 301 .

Typical formation voltages, ie voltages applied during formation, can be a word line voltage of approximately 1V, a bitline voltage of approximately 3V and a source line voltage of approximately 0V (i.e. a voltage difference of approximately 3V). In the example of 3 would apply the positive bit line voltage to the first electrode 303 and the source line voltage of 0V to the second electrode 304 be created.

Once one or more filaments are formed, cover the two electrodes 303 , 304 electrically connect, a current limitation can intervene and stop the further growth of the conductive filaments.

The magnitudes of the formation voltages and their polarity may depend on a configuration of the memory cell, such as an area, a thickness and a material of the memory material and one for the electrodes 303 , 304 used material that is the same material or different materials for the two electrodes 303 , 304 can be.

After the formation is complete, the storage element 202 put into at least two different states to which different time values, eg logical values, eg "0" or "1", can be assigned. In an RRAM memory arrangement, the two different states are typically referred to as the SET state and RESET state. Switching from a SET state to the RESET state and vice versa can be achieved by building up one or more filaments analogously to the formation as with reference to FIG 3 described or by the degradation of the filaments. Conductive filaments can be broken down again, for example, by changing the polarity of the electrodes 303 , 304 applied voltages is reversed. After such a breakdown there are typically still many electrically conductive elements 306 present (more than before Formation), but they no longer form a conductive filament.

The formation as it is in 3 is typically only the first step in a formation process. The overall formation process carried out is decisive for the properties of the memory cell and is divided into two phases:

1. (a) Formation: A pass, for example as with reference to 3 described, in which the memory cell becomes low-resistance due to an electrical breakdown (for the first time).
2. (b) Initiation: Several cycles (e.g. 20 to 60 cycles) in which a cell is initiated by special bias voltages and algorithms to switch between the SET state and the RESET state as well as possible.

4th illustrates a formation process.

The starting point are the non-conductive memory cells 401 after their manufacture.

In 402 a “breakthrough” is created, ie the memory cells 101 be like referring to 3 described formed so that they are conductive.

The conductive memory cells 403 are then initiated in 404, ie they are repeatedly switched back and forth between their conductive state and their non-conductive state, for example between 10 and 100 times. This is done using a special initiation operation.

The initiated cells 405 can then be personalized in 406, for example programmed with customer-specific data. The result is personalized memory cells 409.

In the initiation phase 404 (or (b) in the list above) an initiation process is carried out for each memory cell, which has several passes. Each “pass”, also referred to as “(initiation) operation”, can involve the building up of a conductive filament (or several conductive filaments) as with reference to 3 and vice versa have the degradation of the (or the) conductive filament (or the conductive filaments), i.e. have a switch between SET state and RESET state and back again.

The number of initiation runs in the initiation phase (b) for a memory cell determines how well the memory cell can be programmed in later operation: the more intensively the memory cell is initiated, the more gently (softly) the memory cell can be reprogrammed later. A more intensive or extensive initiation can be understood to mean that it has a higher number of initiation runs (e.g. more frequent reprogramming) and / or takes place with current pulses of higher voltage, power and / or length. An extensively initiated memory cell can thus be programmed later using so-called “soft programming”, which damages the memory element less severely than “hard programming” and can therefore be carried out significantly more often before the memory cell fails.

For a less intensely initiated memory cell, hard programming must be used for programming, in which, compared to soft programming, a higher voltage and / or a higher current and / or a longer current pulse is typically used. This puts a correspondingly greater strain on the memory cell.

The number of runs in phase (b), in particular for an initiation that allows soft programming or an initiation that requires hard programming, depends on the exact memory technology and can be determined more precisely experimentally.

The formation process, in particular the initiation, can be carried out by appropriate activation of the memory control device 104 at the factory where the electronic data processing device 100 or at least the memory array 102 was produced, carried out or carried out in the "field", ie after delivery, at the customer or user site.

Depending on the situation, the memory control device is activated accordingly, for example by executing a corresponding program on the processor or by making contact (e.g. with needles) in the factory.

The memory controller 104 can support various initiation processes (e.g. initiation algorithms), including various initiation voltages, current pulses, initiation powers, etc., in order to enable both intensive initiation for subsequent soft-programming of memory cells and non-intensive initiation for subsequent hard-programming of memory cells .

A typical procedure for an RRAM memory 105 is that the entire memory is formed and initiated in a data-capable manner. However, in many applications 107 (eg on chip cards or in embedded systems) typically only a relatively small part of the memory 105 (often <10%) used for data. That causes numerous initiation cycles for the data capability However, considerable additional test times and test costs, which are largely unnecessary, since the code content (i.e. information that specifies program instructions) is only rarely changed and can be changed by hard programming if necessary.

According to various embodiments, therefore, during the initiation between code memory area 108 and the data storage area 109 differentiated.

For example, the memory 105 (eg a memory chip) initially only formed and initiated for code (ie for hard programming). Only with the definition of the application 107 that should be loaded into memory will be the amount of more dynamic data and accordingly the data area 109 certainly. The data area 109 is then initiated additionally (for example by means of further runs), ie an extended initiation of the data area 109 carried out.

To the different initiated memory areas 108 , 109 to program accordingly, the memory control device 104 support both hard programming and soft programming of memory cells, including various programming voltages, programming pulses, programming services, etc.

It should be noted that memory cells that allow soft programming (i.e. that have been initiated for soft programming) can also be programmed by means of hard programming, because, for example, a memory area is to be used by a different application than initially intended. Such changes can result from the user's change requests for other applications, but also from updates to the operating system or the application software.

This more aggressive programming can be desirable for memory cells that store almost static memory contents such as code, even if the memory cells have been initiated for non-static data, since these memory cells are only rarely reprogrammed. The advantage of using hard programming on memory cells compared to soft programming is greater robustness against aging effects and a lower number of incorrectly read bits, i.e. generally longer data storage.

According to one embodiment, it is therefore provided to apply the hard programming to memory cells which store (at least almost) static memory contents, since with such memory cells the greater stress caused by the hard programming can be accepted. This can be done regardless of how the memory cells were initiated. For example, was the complete memory 105 initiated for data storage (that is, for soft programming), the memory control device can nevertheless use hard programming for storing in the code memory area.

The reverse is true for the data storage area 109 (ie the area of memory cells for data storage), which store non-static data and typically requires several thousand reprogramming, provided according to one embodiment to use soft programming. Correspondingly, an initiation phase (b) with many repetitions (runs) is used for these memory cells.

With non-static data are meant, for example, memory contents that are more frequent than approx. 1000 times during the lifetime of the memory 105 (or the electronic device 100 ) can be reprogrammed.

It should be noted that with Flash and EEPROM (Electrically Erasable Programmable Read-Only Memory) memories, typically no distinction is made between code memory areas and data memory areas within a memory module. To distinguish between code and data, the memory areas are physically controlled or processed differently in order to meet the requirement for different cycle frequencies.

5 shows a flow chart 500 FIG. 12 illustrating a method of making and using memory in accordance with an embodiment.

In 501 the memory, e.g. a memory chip, is manufactured. This includes common semiconductor manufacturing processes.

In 502 the memory is built into an electronic data processing device, for example as a memory 105 of the electronic device 100 . This can also be done together with 501, for example several components of the electronic device can be manufactured on the same chip and accordingly together.

In 503 will how with reference to 3 described the memory 105 completely formed. This is done as part of testing the memory in the factory.

In 504 become all memory cells of the memory 105 for hard programming, ie not very intense, initiated. This is also done when testing the memory in the factory.

At this point in time, the memory chip can be delivered and the following steps can be carried out "in the field", i.e. after delivery to the customer or to the user. Alternatively, the following steps can be performed as part of testing at the factory.

In 505 it is determined how the memory requirement of the application 107 for which the electronic data processing device is intended.

In 506 accordingly becomes a code memory area 108 and a data storage area 109 defined for the memory.

A code memory area can be understood as a memory area that at least for the most part stores code, i.e. program instructions, while a data memory area can be understood as a memory area that at least for the most part stores user data that is processed (and changed) by the application. The definition in the code memory area and data memory area takes place, for example, in such a way that the memory areas consist of larger blocks of connected memory cells.

In 507 becomes the data area 109 additionally initiated (e.g. by means of further initiation runs), ie an extended initiation of the data area 109 carried out (which can be done in different ways).

One possibility is the loader, ie a routine of the operating system 106 who have favourited the application 107 into memory 105 loads to notify the information about how the memory is in code memory area 108 and data storage area 109 is divided.

In this case the loader routine can initiate the data area additionally 109 perform so that the application 107 or the other components of the operating system do not require such an initiation function.

Alternatively or additionally, the application initiates 107 when it is first called (ie when it is executed for the first time) or when new data areas are created (i.e. new parts of the data area 109 ) the corresponding memory cells themselves. Such initializations then cause the application to be used for the first time 107 an additional expenditure of time, which, however, has a positive effect on the application's actual data requirements 107 is matched.

It should be noted that over the life of the memory 105 (eg of the chip life cycle) a reallocation of data storage area 109 to code storage area 108 or vice versa may be necessary. This type of memory usage can be changed, for example, by deleting applications 107 , Updates of the operating system or similar are triggered. In the storage room 105 However, the data-formed memory cells (ie memory cells initiated for soft programming) can also be used again at any time as part of the code memory area 108 can be used. In this case, the memory controller can use hard programming for these memory cells as described above. This can be avoided in particular that the operating system 106 , which controls the memory control device accordingly, the previous assignment of memory cells to memory areas 108 , 109 must save (mapping effort), otherwise it would have to remember all the data areas that have ever been defined.

In summary, according to various embodiments, memory arrangements and methods are provided as shown in FIGS 6th to 9 are shown.

6th Figure 3 shows a memory array 600 according to one embodiment.

The storage arrangement 600 assigns a memory 601 with a plurality of memory cells 602 on, with each memory cell 602 comprises a material whose resistance can be changed, and wherein the memory 601 for storing data based on an adjustment of the resistance of the material in the memory cells 602 is set up.

The storage arrangement 600 further comprises a memory controller 603 that is configured to perform at least one first memory cell initiation process 604 and a second memory cell initiation process 605 , wherein a memory cell initiation process 604 , 605 consists of a plurality of initiation operations, a current pulse being supplied at each initiation operation to a memory cell to which the memory cell initiation process is applied.

The first memory cell initiation process 604 and the second memory cell initiation process 605 differ in one or more electrical parameters.

For example, the first memory cell initiation process and the second memory cell initiation process differ in the voltage used for the current pulse, the power used for the current pulse, the rising edge of the current pulse, the time Distance between successive current pulses and / or the length of the current pulse.

The memory controller 603 is set up a first part of the memory cells 602 by means of the first memory cell initiation process 604 and a second part of the memory cells 602 by means of the second memory cell initiation process 605 to initiate.

An initiation process can be understood as an initiation that has a positive effect on a property of a memory cell that is initiated therewith with regard to the memory properties of the memory cell. The memory properties on which the initiation has a positive effect are, for example, one or more of the cycle stability, the programming speed and / or the service life of data stored in the memory cell (i.e. the data storage of the memory cell).

In other words, according to various exemplary embodiments, not all memory cells of a memory are initiated with the same intensity, but rather a first part is initiated less intensively and a second part is initiated more intensively. Since the initiation requires a large amount of test time, the test time and ultimately the production costs of the memory can be reduced as a result.

In particular, unnecessary test times for the initiation of memory cells can be avoided in that the initiation is carried out in an application-specific manner or even by the respective application that uses the memory itself. Since data storage areas for an application are typically significantly smaller than the storage areas for code (and other static data), in a typical case approx. 90% fewer initiation cycles are required for the memory in the test phase.

7th shows a flow chart 700 illustrating a method for initiating a memory.

The method is used to initiate a memory having a plurality of memory cells, each memory cell having a material whose resistance can be changed, and wherein the memory stores data based on a setting of the resistance of the material in the memory cells.

In 701 a first part of the memory cells is initiated by means of a first memory cell initiation process.

In 702 a second part of the memory cells is initiated by means of a second memory cell initiation process.

It should be noted that 701 and 702 do not necessarily have to be carried out in the order shown but also at least parts of 702 before or parallel to 701 .

A memory cell initiation process (ie the first memory cell initiation process and the second memory cell initiation process) consists of a plurality of initiation operations, with each initiation operation of a memory cell to which the memory cell initiation process being applied being supplied with a current pulse and with the first memory cell initiation process being applied. The initiation process and the second memory cell initiation process differ in one or more electrical parameters.

8th Figure 3 shows a memory array 800 according to a further embodiment.

The storage arrangement 800 assigns a memory 801 with a plurality of memory cells 802 on, with each memory cell 802 comprises a material whose resistance can be changed, and wherein the memory 801 for storing data based on an adjustment of the resistance of the material in the memory cells 802 is set up.

The storage arrangement 800 further comprises a memory controller 803 which is set up to carry out at least a first memory cell programming operation and a second memory cell programming operation.

In each memory cell programming operation, a memory cell to which the memory cell programming operation is applied is supplied with a current pulse, the first memory cell programming operation and the second memory cell programming operation differing in one or more electrical parameters.

For example, the first memory cell programming operation and the second memory cell programming operation differ in the voltage used for the current pulse, the power used for the current pulse, the rising edge of the current pulse, the time interval between successive current pulses and / or the length of the current pulse.

The memory controller 803 is set up a first part of the memory cells 802 by means of the first memory cell programming operation 803 and a second part of the memory cells 802 by means of the second memory cell programming operation 804 to program.

In other words, according to various exemplary embodiments, not all memory cells of a memory are programmed with the same intensity, but rather a first part is programmed less intensively and a second part is programmed more intensively. The less intensive programming (ie the first memory cell programming operation, for example soft programming) strains the memory cells less, for example, than the intensive programming (ie the second memory cell programming operation, for example hard programming). Less intensive programming is only suitable, for example, for memory cells that have been initiated accordingly, or intensive programming can be desirable if long data retention is desired.

Programming a memory or a memory cell can be understood to mean the storage of information in the memory or the memory cell. A memory cell is programmed, for example, by storing a bit in the memory cell.

It should be noted that different exemplary embodiments can be combined, in particular the exemplary embodiments of FIG 6th and 8th (or 7 and 9). This means that two parts of memory cells can be initiated differently and these parts can then be programmed differently accordingly. The first part and the second part of the embodiment of FIG 6th (respectively 7) and the first part and the second part of the embodiment of FIG 8th (or 9) do not, however, need to be the same parts, ie the division of the memory into parts can be different in the different embodiments.

9 shows a flow chart 900 illustrating a method of programming a memory.

The method is used to program a memory that has a plurality of memory cells, each memory cell having a material whose resistance can be changed, and wherein the memory stores data based on a setting of the resistance of the material in the memory cells.

In 901 a first part of the memory cells is programmed by means of a first memory cell programming operation.

In 902 a second part of the memory cells is programmed by means of a second memory cell programming operation.

It should be noted that 901 and 902 do not necessarily have to be carried out in the order shown but also at least parts of 902 before or parallel to 901 .

In each memory cell programming operation, a memory cell to which the memory cell programming operation is applied is supplied with a current pulse. The first memory cell programming operation and the second memory cell programming operation differ in one or more electrical parameters.

Example of the difference between initiation for soft programming and initiation for hard programming (to reduce test time, as with reference to the 6th and 7th ): The initialization of the data memory (i.e. a data storage area) can, for example, comprise a formation and 60 initiation passes (each switching back and forth between SET state and RESET state), while the initialization of the code memory (i.e. a code storage area), for example however, has one formation and 25 initiation passes.

• - SET 1,6V, RESET -1,6V, diverse Pulse von 100ns bis 300ns Länge
• - Stromlimit 280µA

The soft programming is carried out, for example, according to:

• - SET 1.6V, RESET -1.6V, various pulses from 100ns to 300ns length
• - Current limit 280µA

• - SET 2V, RESET -2V, diverse Pulse von 300ns bis 500ns Länge
• - Stromlimit 320µA

The hard programming is done, for example, according to:

• - SET 2V, RESET -2V, various pulses from 300ns to 500ns length
• - Current limit 320µA

• SET = Folge von mehreren Spannungspulsen, bis die Zelle genügend niederohmig ist.
• RESET = Folge von mehreren Spannungspulsen, bis die Zelle genügend hochohmig ist.

At RRAM, the following always applies:

• SET = sequence of several voltage pulses until the cell has a sufficiently low resistance.
• RESET = sequence of several voltage pulses until the cell has a sufficiently high resistance.

The initiation runs for the intensive initiation (initiation for the soft programming) can differ from the initiation runs for the less intensive initiation (initiation for the hard programming) analogously to the soft programming and the hard programming with the above example values in the used Differentiate between voltages, pulse lengths and current limits.

As explained above, soft programming and hard programming lead to different cell properties.

Soft programming according to the example values above leads to an expected data retention of two years (at a certain temperature) and 100,000 programming repetitions are permissible.

Hard programming according to the example values above leads to an expected data retention of ten years (at a certain temperature) and 500 programming repetitions are permissible.

Various exemplary embodiments are specified below.

Embodiment 1 is a memory arrangement having a memory, having a plurality of memory cells, wherein each memory cell has a material whose resistance can be changed, and wherein the memory is configured to store data based on a setting of the resistance of the material in the memory cells, and a memory control device configured to carry out at least a first memory cell initiation process and a second memory cell initiation process, a memory cell initiation process consisting of a plurality of initiation operations, a current pulse being supplied with each initiation operation of a memory cell to which the memory cell initiation process is applied , wherein the first memory cell initiation process and the second memory cell initiation process differ in one or more electrical parameters, and configured, a first part of the memory cells by means of the first memory cell initiation process and to initiate a second part of the memory cells by means of the second memory cell initiation process.

Exemplary embodiment 2 is a memory arrangement in accordance with exemplary embodiment 1, the memory cells being RRAM cells, MRAM cells or PCRAM cells.

Embodiment 3 is a memory arrangement in accordance with embodiment 1 or 2, the memory control device having a receiver which is set up to receive information about the assignment of memory cells of the memory to the first part of the memory cells and the second part of the memory cells.

Embodiment 4 is a memory arrangement in accordance with one of the embodiments 1 to 3, the memory control device being set up to apply a formation to the memory cells of the memory before applying a memory cell initiation process.

Embodiment 5 is a memory arrangement in accordance with one of the embodiments 1 to 4, wherein the first memory cell initiation process is part of the second memory cell initiation process.

Embodiment 6 is a memory arrangement in accordance with one of the embodiments 1 to 5, wherein the second memory cell initiation process is a more intensive memory cell initiation process than the first memory cell initiation process.

Embodiment 7 is an electronic data processing device having a memory arrangement according to one of the embodiments 1 to 6, the electronic data processing device furthermore having a processor which is set up to execute an application, the first part of the memory cells being a code storage area for the application and the second Part of the memory cells are a data memory area for the application.

Embodiment 8 is an electronic data processing device according to embodiment 7, wherein the processor is set up to control the memory control device in such a way that it initiates the first part of the memory cells by means of the first memory cell initiation process and the second part of the memory cells by means of the second memory cell initiation process.

Embodiment 9 is an electronic data processing device according to embodiment 8, the processor being set up to determine information about the assignment of memory cells of the memory to the first part of the memory cells and the second part of the memory cells and to control the memory control device based on the information.

Embodiment 10 is an electronic data processing device according to embodiment 8 or 9, the application having instructions that cause the processor to control the memory control device in such a way that it uses the first memory cell to store the first part of the memory cells. Initiation process and the second part of the memory cells initiated by means of the second memory cell initiation process.

Embodiment 11 is an electronic data processing device according to embodiment 8 or 9, wherein the processor is set up to execute a loading routine which causes the application to be loaded into the memory and which causes the processor to control the memory control device in such a way that it initiates the first part of the memory cells by means of the first memory cell initiation process and the second part of the memory cells by means of the second memory cell initiation process.

Embodiment 12 is a method of initiating a memory having a plurality of memory cells, each memory cell having a material whose resistance is changeable, and wherein the memory stores data based on an adjustment of the resistance of the material in the memory cells, the method comprises: initiating a first part of the memory cells by means of a first memory cell initiation process and initiating a second part of the memory cells by means of a second memory cell initiation process, wherein a memory cell initiation process consists of several initiation operations, with each initiation operation of a memory cell to which the memory cell Initiation process is applied, a current pulse is supplied and wherein the first memory cell initiation process and the second memory cell initiation process differ in one or more electrical parameters.

Embodiment 13 is a method in accordance with embodiment 12, further comprising the identification of the first part of the memory cells and the second part of the memory cells based on a memory requirement of an application that is provided for using the memory.

Embodiment 14 is a method according to embodiment 13, a code memory area and a data memory area being defined for the application based on the memory requirement of the application and the first part of the memory cells being selected according to the code memory area and the second part of memory cells being selected accordingly the data storage area is selected.

Embodiment 15 is a method in accordance with one of the embodiments 12 to 14, the memory cells being RRAM cells, MRAM cells or PCRAM cells.

Embodiment 16 is a method according to one of the embodiments 12 to 15, comprising receiving information about the assignment of memory cells of the memory to the first part of the memory cells and the second part of the memory cells.

Embodiment 17 is a method according to any one of Embodiments 12 to 16, comprising applying a formation to the memory cells of the memory prior to applying a memory cell initiation process.

Embodiment 18 is a method according to any one of Embodiments 12 to 17, wherein the first memory cell initiation process is part of the second memory cell initiation process.

Embodiment 19 is a method according to any one of Embodiments 12 to 18, wherein the second memory cell initiation process is a more intensive memory cell initiation process than the first memory cell initiation process.

Embodiment 20 is a memory arrangement having a memory, having a plurality of memory cells, wherein each memory cell has a material whose resistance can be changed, and wherein the memory is configured to store data based on a setting of the resistance of the material in the memory cells, and a memory control device, configured to carry out at least a first memory cell programming operation and a second memory cell programming operation, a current pulse being supplied in each memory cell programming operation of a memory cell to which the memory cell programming operation is applied, the first memory cell programming operation being different and distinguish the second memory cell programming operation in one or more electrical parameters, and set up a first portion of the memory cells by means of the first memory cell programming operation and a two to program th part of the memory cells by means of the second memory cell programming operation.

Embodiment 21 is a memory arrangement in accordance with embodiment 20, the memory cells being RRAM cells, MRAM cells or PCRAM cells.

Embodiment 22 is a memory arrangement in accordance with embodiment 20, wherein the memory control device has a receiver which is set up to receive information about the assignment of memory cells of the memory to the first part of the memory cells and the second part of the memory cells.

Embodiment 23 is a memory arrangement in accordance with one of the embodiments 20 to 22, wherein the second memory cell programming operation is a more intensive memory cell programming operation than the first memory cell programming operation.

Embodiment 24 is an electronic data processing device having a memory arrangement according to one of the embodiments 20 to 23, wherein the electronic The data processing device furthermore has a processor which is set up to execute an application, the first part of the memory cells being a code memory area for the application and the second part of the memory cells being a data memory area for the application.

Embodiment 25 is an electronic data processing device according to embodiment 24, wherein the processor is set up to control the memory control device in such a way that it programs the first part of the memory cells by means of the first memory cell programming operation and the second part of the memory cells by means of the second memory cell programming operation.

Embodiment 26 is an electronic data processing device according to embodiment 25, wherein the processor is set up to determine information about the assignment of memory cells of the memory to the first part of the memory cells and the second part of the memory cells and to control the memory control device based on the information.

Embodiment 27 is a method of programming a memory having a plurality of memory cells, each memory cell comprising a material whose resistance is changeable, and wherein the memory stores data based on a setting of the resistance of the material in the memory cells, the method comprises: programming a first part of the memory cells by means of a first memory cell programming operation and programming a second part of the memory cells by means of a second memory cell programming operation, a current pulse being supplied in each memory cell programming operation of a memory cell to which the memory cell programming operation is applied and wherein the first memory cell programming operation and the second memory cell programming operation differ in one or more electrical parameters.

Embodiment 28 is a method according to Embodiment 27, further comprising identifying the first part of the memory cells and the second part of the memory cells based on an initiation of the memory cells.

Embodiment 29 is a method in accordance with embodiment 27 or 28, further comprising the identification of the first part of the memory cells and the second part of the memory cells based on a desired data storage of the memory cells.

Embodiment 30 is a method in accordance with one of the embodiments 27 to 29, the memory cells being RRAM cells, MRAM cells or PCRAM cells.

Embodiment 31 is a method in accordance with one of the embodiments 27 to 30, comprising receiving information about the assignment of memory cells of the memory to the first part of the memory cells and the second part of the memory cells.

Embodiment 32 is a method according to any one of Embodiments 27 to 31, wherein the second memory cell programming operation is a more intensive memory cell programming operation than the first memory cell programming operation.

According to a further exemplary embodiment, an arrangement with a memory and a memory training / programming device is provided which is set up to initiate and / or program memory cells of the memory by means of different operations and / or processes (for example more intensive or less intensive). This can be generated depending on whether a respective memory cell is intended for storing static information (e.g. code) or non-static information (e.g. application data).

Although the invention has been shown and described primarily with reference to particular embodiments, it should be understood by those skilled in the art that numerous changes in design and details can be made therein without departing from the spirit and scope of the invention, as defined by the following claims. The scope of the invention is, therefore, determined by the appended claims, and it is intended that all changes which come within the literal meaning or range of equivalency of the claims be embraced.

List of reference symbols

100

Data processing device

101

processor

102

Storage arrangement

103

bus

104

Storage controller

105

Storage

106

operating system

107

application

108

Code storage area

109

Data storage area

200

RRAM memory

202

Storage elements

204

Source lines

206

Bit lines

208

Word lines

210

Transistors

212

Storage cells

301, 302

conditions

303, 304

Electrodes

305

Storage material

306

conductive elements

401

non-conductive memory cells

402

Breakthrough generation

403

conductive memory cells

404

initiation

405

initiated cells

406

personalization

407

personalized memory cells

500

Flowchart

501-507

Process steps

600

Storage arrangement

601

Storage

602

Storage cells

603

Storage controller

604, 605

Memory cell initiation processes

700

Flowchart

701, 702

Process steps

800

Storage arrangement

801

Storage

802

Storage cells

803

Storage controller

804, 805

Memory cell programming operations

900

Flowchart

901, 902

Process steps

Claims (24)

A memory arrangement having a memory having a plurality of memory cells, each memory cell having a material whose resistance can be changed, and wherein the memory is configured to store data based on a setting of the resistance of the material in the memory cells; and a memory control device set up for Carrying out at least a first memory cell initiation process and a second memory cell initiation process, wherein a memory cell initiation process consists of a plurality of initiation operations, a current pulse being supplied for each initiation operation of a memory cell to which the memory cell initiation process is applied, wherein the first memory cell initiation process and the second memory cell initiation process differ in one or more electrical parameters, and configured to initiate a first part of the memory cells by means of the first memory cell initiation process and a second part of the memory cells by means of the second memory cell initiation process. Storage arrangement according to Claim 1 wherein the memory cells are RRAM cells, MRAM cells or PCRAM cells. Storage arrangement according to Claim 1 or 2 wherein the memory control device has a receiver which is set up to receive information about the assignment of memory cells of the memory to the first part of the memory cells and the second part of the memory cells. Memory arrangement according to one of the Claims 1 to 3 wherein the memory control device is set up to apply a formation to the memory cells of the memory before applying a memory cell initiation process. Memory arrangement according to one of the Claims 1 to 4th wherein the first memory cell initiation process is part of the second memory cell initiation process. Memory arrangement according to one of the Claims 1 to 5 wherein the second memory cell initiation process is a more intensive memory cell initiation process than the first memory cell initiation process. Electronic data processing device having a memory arrangement according to one of the Claims 1 to 6th , wherein the electronic data processing device further has a processor which is set up to execute an application, the first part of the memory cells being a code memory area for the application and the second part of the memory cells being a data memory area for the application. Electronic data processing device according to Claim 7 , wherein the processor is set up to control the memory control device in such a way that it initiates the first part of the memory cells by means of the first memory cell initiation process and the second part of the memory cells by means of the second memory cell initiation process. Electronic data processing device according to Claim 8 wherein the processor is set up to determine information about the assignment of memory cells of the memory to the first part of the memory cells and the second part of the memory cells and to control the memory control device based on the information. Electronic data processing device according to Claim 8 or 9 , wherein the application has instructions that cause the processor to control the memory control device in such a way that it initiates the first part of the memory cells by means of the first memory cell initiation process and the second part of the memory cells by means of the second memory cell initiation process. Electronic data processing device according to Claim 8 or 9 , wherein the processor is set up to execute a load routine which causes the application to be loaded into the memory and which causes the processor to control the memory control device in such a way that it transfers the first part of the memory cells by means of the first memory cell Initiation process and the second part of the memory cells initiated by means of the second memory cell initiation process. A method of initiating a memory having a plurality of memory cells, each memory cell comprising a material whose resistance is changeable, and wherein the memory stores data based on an adjustment of the resistance of the material in the memory cells, the method comprising: Initiating a first portion of the memory cells by means of a first memory cell initiation process; Initiating a second portion of the memory cells by means of a second memory cell initiation process; wherein a memory cell initiation process consists of several initiation operations, wherein a current pulse is supplied at each initiation operation of a memory cell to which the memory cell initiation process is applied, and wherein the first memory cell initiation process and the second memory cell initiation process differ in one or more electrical parameters. Procedure according to Claim 12 , further comprising identifying the first part of the memory cells and the second part of the memory cells based on a memory requirement of an application that is provided for using the memory. Procedure according to Claim 13 , with a code memory area and a data memory area being determined for the application based on the memory requirement of the application and the first part of the memory cells being selected in accordance with the code memory area and the second part of memory cells being selected in accordance with the data memory area. Having memory arrangement a memory having a plurality of memory cells, each memory cell having a material whose resistance can be changed, and wherein the memory is configured to store data based on a setting of the resistance of the material in the memory cells; and a memory control device set up for Carrying out at least a first memory cell programming operation and a second memory cell programming operation, a current pulse being supplied in each memory cell programming operation of a memory cell to which the memory cell programming operation is applied, wherein the first memory cell programming operation and the second memory cell programming operation differ in one or more electrical parameters, and configured to program a first part of the memory cells by means of the first memory cell programming operation and a second part of the memory cells by means of the second memory cell programming operation. Storage arrangement according to Claim 15 wherein the memory cells are RRAM cells, MRAM cells or PCRAM cells. Storage arrangement according to Claim 15 wherein the memory control device has a receiver which is set up to receive information about the assignment of memory cells of the memory to the first part of the memory cells and the second part of the memory cells. Memory arrangement according to one of the Claims 15 to 17th wherein the second memory cell programming operation is a more intensive memory cell programming operation than the first memory cell programming operation. Electronic data processing device having a memory arrangement according to one of the Claims 15 to 18th , wherein the electronic data processing device furthermore has a processor which is set up, an application execute, the first part of the memory cells being a code memory area for the application and the second part of the memory cells being a data memory area for the application. Electronic data processing device according to Claim 19 , wherein the processor is set up to control the memory control device in such a way that it programs the first part of the memory cells by means of the first memory cell programming operation and the second part of the memory cells by means of the second memory cell programming operation. Electronic data processing device according to Claim 20 wherein the processor is set up to determine information about the assignment of memory cells of the memory to the first part of the memory cells and the second part of the memory cells and to control the memory control device based on the information. A method of programming a memory having a plurality of memory cells, each memory cell comprising a material whose resistance is changeable, and wherein the memory stores data based on a setting of the resistance of the material in the memory cells, the method comprising: Programming a first portion of the memory cells using a first memory cell programming operation; Programming a second portion of the memory cells using a second memory cell programming operation; wherein each memory cell programming operation of a memory cell to which the memory cell programming operation is applied is supplied with a current pulse, and wherein the first memory cell programming operation and the second memory cell programming operation differ in one or more electrical parameters. Procedure according to Claim 22 , further comprising identifying the first portion of the memory cells and the second portion of the memory cells based on an initiation of the memory cells. Procedure according to Claim 22 or 23 , further comprising identifying the first part of the memory cells and the second part of the memory cells based on a desired data storage of the memory cells.

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