DE102006040238A1 - Transistor arrangement for selecting one memory cell from multiple memory cells in substrate, has memory cell, and one wordline forms in one wordline trench of multiple gate electrodes at side panel of active areas of two adjacent set - Google Patents

Abstract

The transistor arrangement has memory cell (110,111), where each memory cell of a transistor (140,141) is connected by a memory element (120,121) with a bit line (130) and is addressable by selecting two word lines (160,161) and the bit line. The one wordline forms in one wordline trench of multiple gate electrodes at a side panel of active areas of two adjacent set of transistor cells in wordline direction. INDEPENDENT CALIMS are also included for the following: (1) a vertical transistor arrangement in a substrate (2) a method for manufacturing an arrangement of vertical transistor cells in a substrate (3) a method for the operation of a double gate transistor (4) a method for the operation of two adjacent double gate transistor in an arrangement of double gate transistors.

Description

The The invention relates to a transistor, a memory cell arrangement and a method of manufacturing and operating a memory element with at least one memory cell, in particular a resistive switching, for example, a phase change memory cell, and a memory element.

conventional Memory elements, in particular semiconductor memory elements, can be subdivided into a first group of so-called functional memory elements, For example, PLAs, PALs, etc. and a second group of so-called Table storage elements, for example ROM elements, such as PROMs, EPROMs, EEPROMs, flash memory, etc. There is also a third group so-called RAM elements, such as DRAMs and SRAMs.

In younger Time are so-called resistive or resistively switching memory elements become known, for example, so-called phase change memory (PCMs) or bridge conductor memory (conducting bridge = CB) memory or magnetoresistive memory (MRAM) or resistive RAM (RRAM).

In a resistive or resistive switching memory cell may be active or active switching material, which is usually between two corresponding electrodes, i. an anode and a Cathode is positioned, between a nem conductive and a less conductive state switched by a suitable switching process become. The conductive state can be a logical 1 and less conductive state can be assigned a logical 0, or vice versa, which corresponds to a logical arrangement of a bit.

For phase change memory (PCRAMs), for example, a suitable chalcogenide mixture, e.g. Ge-Sb-Te (GST) or an IN-SB-TE mixture as a switching active Material to be used, which is between two corresponding electrodes is positioned. This switching active, so for example the chalgonide Material can be between an amorphous and a crystalline state be switched, the amorphous state comparatively low is conductive and to which a logical 0 can be assigned, and the crystalline state of the comparatively well-conductive state is, to which a logical 1 can be assigned accordingly. in the Following this material is referred to as a switching active material.

Around a change from the amorphous, so the comparatively weak conductive state of the switching active material, to the crystalline, So bring about the comparatively well-conductive state, must the material will be heated. For this purpose, a heated Current pulse passed through the material, which is the switching active material on his Crystallization temperature also heated and thus the resistance reduced. In this way, the memory cell in a first logical state are set. Conversely, the switching active Material by applying a relatively high current to the cell are heated, causing a melting of the switching active material and by subsequent quenching For example, the material can be transformed into an amorphous, i. a relatively weak one be brought to a conductive state, the second logical state can be assigned so that the first logical state is reset becomes.

Various proposals have been made for PCRAM cells, for example from SJ Ahn, "Highly Manufacturable High Density Phase Change Memory of 64MB and Beyond", IEDM 2004 , and H. Horii et al. "A novel cell technology using N-doped Spectral Films for Phase Change RAM", VLSI, 2003 , such as YN Hwang et al. "Phase-change RAM based on 0.24 μm CMOS technologies", VLSI, 2003 , or S. Lai et al "OUM - a 180 nm nonvolatile memory cell element technology for stand-alone and embedded applications", IEDM 2001 , or from YH Ha et al "An edge contact cell type cell for phase change RAM featuring very low power consumption", VLSI, 2003 ,

Out cost reasons a small cell size is necessary the high density of memory cells in a memory element allows.

One Disadvantage of the proposed memory cells is the use of planar array transistors or transistors with a source / drain contact in the same horizontal plane, for example FinFETs. Such Construction prevents geometric shrinkage of the cell under a size of 6F2, because the size of a Cell the area includes that for the transistor for selecting the Cell needed becomes.

The US 2005/0001257 A1 discloses a DRAM memory cell having a vertical transistor cell formed in a substrate and having a lower source / drain region connected to a common connection plate. Upper source / drain regions of the transistor cell have a contact connected to a storage capacity. The arrangement of the transistor cells is formed by word line trenches, wherein the word lines in the trenches form gate electrodes of the transistor, and by shallow trench isolation (STI), which run perpendicular to the word line trenches. A disadvantage of this structure is the need to accommodate two electrically isolated word line spacers in a wordline trench.

It Thus, it is an object of this invention to provide a new design of a selection transistor for a To propose memory element with a multiplicity of memory cells, in particular phase change memory cells, and a corresponding Method for manufacturing the transistors, the problems mentioned above be avoided.

To In a first aspect of the invention, an arrangement becomes vertical Transistors in a substrate for selecting one of a plurality proposed by memory cells, each memory cell one Transistor cell over a memory element connects to a bit line and over two Word lines and the bit line is addressable, the arrangement the vertical transistors is determined by a variety of Word line trenches and a plurality of vertically crossing isolation trenches in the Substrate. In the direction of the isolation trenches, the word line trenches separate the Transistor cells from each other, and in the direction of the word line trenches separate the isolation trenches the Transis torzellen from each other, wherein a word line trench a Word line and wherein a first word line in a first Wordline trench a plurality of gate electrodes on a sidewall more active Areas of a first and a second adjacent row of transistor cells in the word line direction, and wherein a second word line in a neighboring word line trench, a plurality of gate electrodes on the opposite side Sidewall of the active areas of the second and third row of transistor cells in the word line direction forms.

A other embodiment The invention relates to an arrangement of vertical transistors in a substrate for selection one of a plurality of memory cells, each memory cell one Transistor over connects a memory element to a bit line and by selecting the Bit line and two word lines is addressable, the Arrangement of the vertical transistors is determined by a variety of word line trenches and a plurality of vertically crossing isolation trenches in the Substrate. The word line trenches Separate the transistor cells in the direction of the isolation trenches from each other, and the isolation trenches the transistor cells separate in the direction of the word line trenches, wherein a wordline trench is a series of gate electrodes of a row receiving adjacent transistor cells in the word-line direction, wherein the gate electrodes are electrically coupled to a gate line are over that Word line trench is positioned, and wherein a first row of gate electrodes in a first word line trench a plurality of gate electrodes on a first sidewall of active regions first and a second, adjacent row of transistor cells forms in Wortlei direction and wherein a second row of gate electrodes in one adjacent wordline trench a plurality of gate electrodes on the other side wall of the active areas of the second and one third row of transistor cells in the word line direction forms.

Furthermore, the invention proposes a method for producing an arrangement of vertical transistor cells in a substrate, comprising the following method steps:
Forming a conductive layer within the substrate, the conductive layer being covered by a less conductive and at least partially oppositely doped substrate layer;
Forming a plurality of parallel isolation trenches extending along a first direction and filling the isolation trenches with an insulating material;
Forming a plurality of parallel wordline trenches extending along a second, perpendicular to the first direction, thus forming columns of substrate material emerging from the substrate and serving as active regions of transistor cells;
Forming a layer of gate dielectric in a wordline trench and then filling with a conductive material such that gate electrodes are formed on a sidewall of a first and a second adjacent row of active regions in the wordline direction, thus forming a wordline;
Forming a layer of gate dielectric in at least one second adjacent wordline trench and then filling with a conductive material thus forming gate electrodes on an opposite sidewall of the first row of active areas and on a sidewall of a third, adjacent row of active areas in the wordline direction and thus forms a second word line.

Furthermore, a method for producing an arrangement of vertical transistor cells in a substrate is proposed according to the invention, which method comprises the following method steps:
Forming a plurality of parallel isolation trenches extending in a first direction and filling the isolation trenches with an insulating material;
Forming a plurality of parallel wordline trenches extending in a second direction perpendicular to the first direction and thus forming columns of substrate material emerging from the conductive layer in the substrate and serving as active regions of transistor cells;
Producing a layer of gate dielectric in a first word line trench and subsequently filling it with a conductive material such that gate electrodes are formed thereon on a sidewall of a first and a second adjacent row of active regions in the word line direction form a wordline;
Forming a layer of gate dielectric in at least a second, adjacent wordline trench and then filling with a conductive material such that gate electrodes are formed on an opposite sidewall of the first row of active areas and on a sidewall of a third, adjacent row of active areas in the wordline direction; so that thus a second adjacent word line is formed.

Farther a method for operating a double-gate transistor is proposed, wherein the transistor has an active region, a first gate electrode, which is arranged on a first side wall of the active area and a second gate electrode disposed on the opposite side wall of the active region is arranged, wherein the first gate electrode to coupled to a first word line and the second gate electrode a second word line is coupled, and wherein the transistor may have a first state, which by a first to open the Transistor to both word lines applied voltage is determined and a second state for lowering the conductivity of the transistor by at least an order of magnitude by a third voltage applied to the first word line and a fourth to the second word line applied voltage is defined.

As well A method for operating a first and a second, adjacent double gate transistor in an array of dual gate transistors, wherein the first dual gate transistor is a first to a first word line coupled gate electrode and a second to a second word line has coupled gate electrode, and the second double-gate transistor a first gate electrode coupled to a third word line and a second gate electrode connected to the second word line is coupled so that the first and the second transistor to the have the second word line coupled gate electrode in common, while opening of the first transistor, a positive gate voltage to the first and second word line is applied and earth potential or a negative voltage to the third word line for closing the second transistor is created.

In a further embodiment will further be an arrangement of transistors in a substrate to choose one proposed from a plurality of memory cells, wherein each memory cell each have a transistor via a respective memory element coupled to a bitline and by selecting a pair of wordlines and a bit line extending perpendicular thereto is addressable, wherein the transistor arrangement is formed by a plurality of word line trenches is that form strips of substrate material that act as active transistor regions serve, with the strips separated by sections of insulating trenches so that the wordline trenches the transistor cells in a first direction and the sections the isolation trenches separate the transistor cells in the direction of the wordline trenches, wherein a wordline trenches receives a word line, and wherein a first word line of a Pair of word lines connect a plurality of gate electrodes to one another Sidewall of active areas of a series of transistor cells in word line direction, and the other word line of the pair a plurality of gate electrodes on the opposite side wall of the active areas of the row of transistor cells in the word line direction forms, and wherein the transistors at every other point of intersection of a pair of word lines are placed with a bit line, wherein the transistors in adjacent rows are offset by one bit line are arranged so that the transistors arranged like a checkerboard are.

in the The invention will be explained in more detail with reference to drawings.

1 shows a schematic circuit of an arrangement of memory cells;

2 shows a schematic plan view of an arrangement of a layout of double-gate transistor cells;

3a . 3b show a schematic cross section of a memory cell;

4 shows a schematic cross section of a memory cell at a first production time;

5a . 5b show schematic sectional views of a modification of a memory cell;

6 shows a schematic cross section of the modification of the memory cell at a manufacturing time;

7 shows a schematic diagram of an alternative embodiment of the invention;

8th shows a plan view of the alternative layout of the double gate transistor cells;

9a . 9b represent a schematic sectional view of the alternative embodiment.

1 shows a schematic circuit of an arrangement of memory cells, exemplified by a first and an identical second memory cell, surrounded by the dashed lines 110 respectively. 111 ,

Each memory cell has a resistive switching element 120 . 121 on which one with a bit line 130 and the drain of a selection transistor 140 respectively. 141 connected is. The selection transistors 140 . 141 are each coupled with their source to a source potential, namely to the source line 150 , wherein the source potential may be the ground potential, corresponding to the source line 150 a grounding line can be. In this arrangement of memory cells, all of the selection transistors have their source connected to a single source line 150 coupled, which is a plate in this embodiment. In this way, a memory cell connects a transistor to a bit line via a resistive switching memory element.

The selection transistors 140 . 141 are - as shown - double-gate transistors, wherein each of the gates of one transistor is connected to another word line, that is, the first gate - on the left side of the transistor 140 - is galvanic to a first word line 160 coupled and the second gate - on the right side of the transistor 140 - is with a second word line 161 galvanically connected. To match the transistor 140 by fully applying a suitable gate voltage to both gates, the gate voltage must be applied to two word lines, namely the word lines 160 and 161 be created.

The selection transistors 140 . 141 are vertical transistors, where "vertical" describes that taking the surface of the wafer as a horizontal reference plane, a substantial portion of the current flow is vertical, or in other words, the drain is located substantially above the body region in which the conductive channel is formed , which in turn is disposed substantially above the source of the transistor.

Furthermore, the opposite gates of two adjacent transistors are connected to the same bit line 130 connected to the same word line, ie, the gate on the right side of the transistor 140 and the gate on the left side of the transistor 141 are at the word line 161 coupled. So if the transistor 140 by applying a suitable gate voltage to the word lines 160 and 161 is opened, the gate voltage at the same time to a gate of the transistor 141 created.

In a preferred embodiment the transistors are complete depleted, that is, the depletion zones passing through the left and right gate electrode are overlapping in the active transistor area. At complete depleted N-type double-gate transistors is to turn one positive voltage over the threshold voltage to apply to both gate electrodes. If the potential of only one gate electrode is pulled up, i.e. one Gate voltage over the threshold voltage of the double gate transistor only to a gate electrode is applied, then the transistor is called a so-called backgate controlled transistor, that is, the effective threshold voltage depends on of the voltage applied to the other gate electrode, so that the threshold voltage with the increased voltage of the backgate electrode decreases. In this way, the threshold voltage of a transistor through Applying a ground potential or a negative voltage to a Gate electrode to be raised so that the transistor is not completely in the conductive state is switched, resulting in a significantly lower current flow. If a voltage well below the threshold voltage, which may be ground potential or a negative voltage to both Gate electrodes is applied, the transistor is turned off, what to a negligible Current flow leads.

When writing a cell, ie, setting or resetting a cell by passing a comparatively high current pulse through the volume of the resistive switching material, the voltage of the two corresponding word lines must be increased to turn on the selection transistor. Accordingly, for writing the first cell 110 the voltage of the word lines 160 and 161 be raised to the selection transistor 140 turn on and the bit line voltage 130 must be increased to an appropriate voltage so that a current pulse through the resistive switching element 120 flows.

According to the voltage applied to the word lines 160 and 161 is applied, a voltage is also applied to a gate of the selection transistor of the adjacent cell. Nevertheless, since the voltage of the opposite gate of the adjacent memory cell is kept low, ie at ground or even lower potential, the current flow through the selection transistor of the adjacent memory cell is below the threshold for writing the cell, so that the current flowing through these cells flows, leaving the state unchanged.

The worst case for reading a memory cell is if the selected cell has a high resistance, whereas the adjacent memory cells connected to the same bitline are in a low conductivity state. In order to minimize the current flow through the adjacent memory cells in this case, the selection transistors are designed to that when reading a cell, the selection transistors of the adjacent memory cells operate in a range below the threshold, so that the resistance of a transistor can be increased by one or two orders of magnitude, the signal distance is large enough for reliable detection.

A further property of the described memory cells with two gate electrodes, those with two electrically independent Word lines are connected, that is two different voltages applied to the two gate electrodes of a selection transistor can be.

The two memory cells in 1 are representative of a plurality of memory cells connected to a bit line to form a series of memory cells. A plurality of these rows may be integrated into a single memory element having a plurality of bitlines and wordlines, wherein a memory cell may be selected by selecting two corresponding wordlines and a corresponding bitline.

2 is a schematic plan view of a section of an arrangement of memory cells 200 comprising dual gate selection transistors. The volume resistive switching material are not shown because they are hidden by the bit lines. Likewise, insulating material, in which, for example, the bit lines are embedded, only partially shown. Furthermore, the source plate on which the structures are formed, as well as the metallization layers are omitted above the bit line.

A first and a second bit line 210 . 220 , which are the topmost elements in this supervision, are exemplified. A plurality of identical bit lines are arranged adjacent and parallel to them. As will be explained in more detail in the following description, the bit lines are arranged above the surface of the original wafer.

reference numeral 230 and 240 denotes a first and a second word line, which are exemplary of a plurality of parallel word lines. The wordlines 230 . 240 are below the bitlines 210 . 220 placed and at least partially below the surface plane of the original wafer so that the wordlines are buried below the surface plane of the original wafer.

The side surfaces of the word lines are of a layer of insulating oxide 250 which forms the gate oxide of the selection transistors. Thus, each word line forms a plurality of gate electrodes of the selection transistors. The active regions of the transistors, namely the source, drain and the body of the selection transistors, are as indicated by arrow 260 shown - arranged below the bit lines and between a pair of word lines. The areas between the bit lines and also between the word lines, indicated by the arrow 270 , are filled with an insulating material and thus form a shallow trench isolation (STI).

Although the drawing is not to scale, the numeral indicates 260 the periodicity of the bit lines 210 and 220 and the wordlines 230 and 240 as 2F, where F denotes the minimum feature size determined by conventional manufacturing methods. Accordingly, the cell size is 4F2.

The Invention is in this case based on a phase change memory cell explains however, it is not limited to phase change memory cells, but rather can for All resistive switching 1TnR memories are used the same Cell architecture, i.e., cells whose bit line directly is connected to the memory element, and in which the transistor source connected to a common (earth) potential.

It should be noted that an arrangement, as in 2 can be achieved by two different structures, namely by means of a first embodiment having a buried word line, or by means of a second structure having a conventional word line. Both embodiments will be described in more detail below.

3a represents a cross section through two memory cells 300 , where the direction of the cut line is parallel to a bit line.

The The following description refers to an N-type transistor. Although not described here, the transistor can also be called T-type transistor formed with adapted doping and corresponding voltages be.

In a wafer 310 is a plate 320 of N + doped semiconductor material connected to ground potential and serves as ground or ground line. In the following description will be the surface of this plate 320 used as the horizontal reference plane, as it is included in each drawing.

In the drawing are two active areas 330a and 330b two corresponding selection transistors shown. The drain 360a . 360b N + doped SI - of a selection transistor is at the top of an active region 330a . 330b arranged. At the un The lower end of the active region, the source region of the selection transistor is formed, which is part of or directly to the plate 320 connected is. Between the N + doped source and the drain region 360 , the transistor body is arranged. The material of the bodys is doped P-type.

The two gate electrodes 340a and 340b form the double gate electrode on the two sidewalls of the active area 230a so that this transistor is a double gate transistor. Every gate electrode 340a . 340b is through a gate oxide layer 350a . 350b opposite the active area 330a electrically isolated.

The gate electrode 340a is further one of two gate electrodes of a - not shown - adjacent transistor on the left side of the drawing and thus is the gate electrode on the right side wall of the corresponding active region. Likewise, the gate electrode 340 one of two gate electrodes of a transistor, which is the active area 330b includes, wherein the gate electrode on the right side of the active region 330b not shown in the drawing. Accordingly, each gate electrode serves as a gate electrode for two adjacent transistors, with the corresponding memory cells connected to a single bit line 390 are connected. As mentioned above, the gate electrodes are galvanically connected to one another on a side wall of the active regions of the transistors, in particular, the interconnected gate electrodes form a word line on a sidewall of the active regions. That is, the gate electrode 340a in 3a is connected to the adjacent gate electrodes, which are arranged in front of and behind the plane of the paper, so that these gate electrodes form a word line, which runs into the plane of the paper. In the same way is the gate electrode 340b on the opposite side of the active area 330a is placed, with the adjacent gate electrodes - not shown - connected, which are placed in front of and behind the plane of the paper, and thus form another running into the paper plane word line.

Accordingly, for driving the transistor cell, which is the active region 330a comprises applying a gate voltage to two word lines, namely to those word lines which comprise the gate electrodes on the opposite sidewalls of the active area 330a form.

Every drain 360a . 360b is to a bottom electrode contact 370a . 370b coupled to a memory cell, wherein the ground electron contact is again placed on the drain and to a volume of switching active material 380a . 380b is coupled. Each volume of switching active material 380a . 380b is again to a bit line 390 coupled, which is placed on the volume of the switching active material.

Corresponding to the direction of the cutting line in the drawing, both volumes of switching active material 380a . 380b directly to a single bit line 390 coupled. These volumes illustrate a variety of volume switching active materials connected directly to a single bit line.

3b shows a cross section through a structure with a section line perpendicular to a bit line, ie in the direction of a word line.

As described above, a body region of an active region is 330a a selection transistor on the plate 320a placed and galvanically connected to this, which serves as a source plate electrode. The upper end of the body area of the active area 330a of the selection transistor is connected to a drain 360a connected, which in turn to a bottom electrode 370a coupled, in turn, with a volume switching active material 380a connected is.

In this view, as indicated by the dashed line and reference numerals 340 indicated, a first gate electrode and thus arranged a first word line in front of the paper plane of the drawing voltage and a second gate electrode, in other words a second word line, is arranged behind the plane of the paper, so that the two gates thus a double gate electrode for the active area 330a form.

A shallow trench isolation (STI) 350 runs in an isolation trench parallel to the bit line 390 thus isolating active areas of transistors of memory cells which are connected to different bit lines.

In this embodiment, the isolation trench does not reach into the source plate electrode 320 such that body regions of adjacent transistors in a lower region of the active regions are electrically connected to one another. Accordingly, during operation of the transistors, charge carriers can migrate from one active region into adjacent active regions, thus avoiding an accumulation of charge carriers in an active region and thus avoiding the effects of a "floating body" transistor.

In an alternative embodiment, the extension of the STI into the source plate electrode 320 extend, so that thereby individual columns of Si from the source plate electrode 320 protrude.

The in the 3a . 3b As shown and described structure thus describes a vertical double-gate transistor, wherein vertically the direction of current flow from the source plate electrode through the transistor body part 330a . 330b and the drain 360a . 360b to the bottom electrode 370a . 370b be writing- which with a volume of switching active material 380a . 380b which in turn is connected to bit lines 390 ( 390a / 390b ) is coupled.

The gate electrodes 340a . 340b thus form a dual gate electrode for each select transistor on the sidewalls of an active area 330a . 330b , with the advantages described above. The gate electrodes 340a . 340b are formed as strips and form the word lines perpendicular to the bit lines 390 run. Since each word line can be independently coupled to a voltage, the two gates on the sidewalls of the active region of a selection transistor can be independently supplied with voltages.

4 shows a cross section through a structure during the production of the selection transistors on a silicon wafer. The direction of the section line is parallel to a bit line and thus equal to the in 3a , The reference numerals are correspondingly the same for elements in those 3a ,

The fabrication of the illustrated structure begins at the surface of a silicon wafer 310 , wherein the plane of the original surface of the wafer by arrow 311 is specified.

Starting from a lightly doped substrate, the wafer receives an N + implant to form an N + doped layer, which serves as a source plate electrode 320 serves, with the N + is to implement deep into the wafer material, ie in the Si of the wafer. This can be achieved either by high energy implantation which transports the N + deep into the Si, or alternatively by implanting and epitaxially growing P-type doped silicon on the surface such that the N + implanted layer is covered by a Si deposition.

alternative For example, the conductive layer may also be part of the original substrate. For this may be a P-type epitaxial layer on an N + type substrate wafer be deposited.

The Source plate electrode is used to connect the source of a transistor to a suitable source voltage, accordingly, a suitable Source voltage applied to the source plate electrode, for example Ground or ground potential.

On the surface of the wafer can - as indicated by reference numeral 314 - an oxide and a nitrite intermediate layer and an optional hard mask layer are deposited in a conventional manner, which serve as a protective and as a stenciling agent.

In a next step, an isolation trench for shallow trench isolation (STI) is etched. In this drawing, the isolation trench is not shown because it is parallel to the paper plane and in front of and behind the plane of the paper. How out 3b visible and by reference numerals 350a is indicated, the depth of the STI trench is at least half the channel length of the transistor and may extend into the N + doped source plate electrode. Subsequently, this trench is filled with a conventional material which is suitable for shallow trench isolation, for example an oxide such as SiO 2.

In a subsequent step, word line trenches for word lines are etched into the Si and isolation trenches by a conventional lithographic etching process. The width of a trench is indicated by reference numerals 312 specified. Since the wordline trenches are perpendicular to the isolation trenches, these trenches intersect the isolation trenches that are filled with an oxide such that upon etching of the wafer material, the STI material is also etched. The etching process may be terminated before reaching the source plate electrode or the word line trench may extend into the source plate electrode 320 extend. In this way, the wordline trenches form strips in the substrate material that act as active areas 330a and 330b serve the transistors. These strips are separated by remaining pieces of the isolation trenches in transistor cells. The word lines thus separate the transistor cells in a first direction and the remaining pieces of the isolation trenches separate the transistor cells in the direction of the word line trenches.

to Improvement of functionality the one on the opposite sidewalls the active regions positioned gate electrodes can be the active Areas further diminished become. Another effect of narrowing the active areas is that more space for the gate oxide layer and the gate electrodes are provided. A Victim oxidation can optionally be used to create a thin oxide layer carried out the active areas in subsequent process steps protects and from damage from edges of the Si surface protects.

If the etching of the word line trenches before reaching the source plate electrode 320 is finished, the bottom of the trench is vertically implanted N + +, whereby an optional sacrificial sidewall interlayer can be used, so that the bottom of the trench galvanically to the source plate electrode 320 is coupled.

In this production state can other implants done, for example, for creating and Adjust the NP transitions in the transistor.

following the sacrificial oxide layer is removed and the sidewalls of the Word line trenches are oxidized, that is, a thin one Layer of electrically insulating oxide is applied to a thin layer of gate oxide in the wordline trenches.

Then the material becomes the gates 340a . 340b , which is the material of the word lines, deposited and filled the trenches. In order to ensure a good conductivity of the word line, this material is preferably a metal, for example tungsten. However, if the processing of metal to fill the wordline trenches proves too complex or too expensive, polysilicon may also be used as the wordline material.

Subsequently, will the material of the gate electrodes, which is the word line material is planarized with respect to the nitrite intermediate layer, wherein a conventional one Method is used, for example, a conventional chemical mechanical polishing process (CMP).

Thereafter, the gate electrode material is withdrawn so that the height of the word line, which is also the height of the gate electrodes of the selection transistor, is as shown in the drawing, namely that the surface of the word line is below the original surface of the wafer, as by arrow 311 shown.

following An auxiliary implantation may be performed to drain the drain To dope transistor.

After the electrode or word line material has been withdrawn to a height as shown in the drawing, the word lines and the gate electrodes, respectively 340a and 340b covered with an electrically insulating oxide cap as indicated by reference numeral 313 indicated.

In subsequent process steps - their effects are not in 4 are shown - are the nitrite and oxide interlayer 314 removed to the surface of the active area 330a . 330b expose. For doping the upper portion of an active area 330a respectively. 330b An optional N + auxiliary implantation may be performed. Furthermore, to increase the contact area of the active area 330a respectively. 330b of the transistor, a further layer of silicon can be deposited by means of selective epitaxial growth.

Subsequently, in a conventional manner for contacting a volume of phase change material above the active region 330a respectively. 330b the bottom electrode contact are formed. Likewise, the volume of phase change material and the accompaniments can be formed by means of conventional process steps.

In this way, the word line is through gate electrodes 340a and 340b is formed below the surface of the original wafer and buried with it. Likewise, the source plate electrode 320 , the active areas 330a respectively. 330b and the gate electrodes forming the word lines below the surface 311 of the original wafer.

In the case, that a word line with a good conductivity is desired and if the Creating a buried metal word line as too complex or is too expensive, a second structure is provided, the one Dual gate memory cell with a conventional word line stick structure suggests how described below.

5a and 5b show a structure similar to that of the 3a and 3b having the exception of the conventional word line layer structure.

5a shows a cross section through a memory cell, wherein the cutting line is parallel to a bit line. On a silicon wafer 510 serves an N + doped silicon layer as a source plate electrode 520 on which are formed vertical transistors which are a P-type doped body region 530a respectively. 530b and an N-type doped drain 560a . 560b exhibit.

gate oxide layers 550a . 550b isolate gate electrodes 540a . 540b from the active areas 530a . 530b and the source plate electrode 520 as well as the drainage area 560a . 560b , The gate electrodes 540a and 540b form for the transistor with the active area 530a a double gate electrode.

In this embodiment, the material is the gate electrodes 540a . 540b Polysilicon (poly Si). This has the advantage that when forming the gate electrodes, the polysilicon is less expensive to process, especially when filling a trench.

However, it is insufficient, a word line from the gate electrodes and, accordingly, from the material of the gate electrodes 540a and 540b , which in this case is polysilicon, since the conductivity of polysilicon is significantly less than the conductivity of metal, and because good word line conductivity is necessary to connect a plurality of gate electrodes.

In order to improve the conductivity of the word lines in this embodiment, a gate line 570a . 570b of highly conductive material, such as a metal on the polysilicon gate electrodes 540a and 540b educated. This layer 570a . 570b is above the surface - indicated by arrow 511 Of the original wafer, so that in this embodiment the word line is not buried beneath the surface of the wafer. Since in this view the gate electrodes run into the plane of the paper, the gate line is 570a respectively. 570b in electrically insulating material 580a . 580b embedded to electrically isolate them from surrounding elements, for example from the bottom electrode contacts 590a . 590b , The bottom electrodes 590a . 590b each contact a volume of phase change material 5100A . 5100B at the bottom, which in turn directly with a bit line 5110 connected is.

5b shows the structure of a memory cell and an associated selection transistor in a sectional view through the memory cell and perpendicular to a bit line and thus perpendicular to the view as in 5a , How to 5a described, exists on the silicon wafer 510 a layer of N + doped silicon 520 which serves as a source plate electrode. A column of weakly P-type doped silicon, which is the body of the active area 530a a selection transistor extends from the source plate electrode 520 , An N + doped drain 560a is placed on the body of the transistor and couples to the bottom electrode 590a a memory cell containing a volume of phase change material or switching active material 5100A and in turn to a bit line 5110 couples.

The dashed line of the gate electrodes 540a . 540b is intended to show that in this view one gate electrode is in front and the other gate electrode is behind the plane of the paper. An isolation trench for a shallow trench isolation (STI) 5120 separates the active area 530 electrically from the surrounding elements, in particular from the drains of the adjacent selection transistors.

In this embodiment, it should be noted that the shallow trench isolation 5120 down to the source plate electrode 520 extends or reaches and thus the active area 530 of the illustrated selection transistor is separated from the active region of an adjacent transistor. In a variant of this structure, not shown, the depth of the trench of the STI extends at least to below the drain region of the transistor, but may be in front of the source plate electrode 520 so that the STI does not separate the active regions of adjacent transistors.

6 FIG. 12 shows a sectional view with a cut line parallel to a bit line through a transistor at a processing time just before the gate line is etched, the transistor having a double gate electrode and a conventional word line. FIG. As above 4 described production begins with an undoped or weak P-type doped wafer 610 , where the plane of the original surface of the wafer by the arrow 611 is specified.

As well as too 4 described and carried out by performing the same process steps, the wafer in this embodiment, an N + doped layer, which serves as a source plate.

As described above, on the surface of the wafer, in the conventional manner, as the protective and stenciling agent, an oxide layer may be designated by reference numerals 614 - And a nitrite layer and an optional hard mask layer, which are not shown, are deposited.

In a subsequent process step, isolation trenches for a shallow trench isolation (STI) are etched between the active regions of adjacent transistors by means of conventional lithography and etching methods. These trenches are not shown in the drawing, as they are parallel to the bit lines and in front of or behind the plane of the paper of the drawing. As above with respect to 5 mentioned, the depth of the trench for the STI must reach at least to below the drain of the transistor and can before the source plate electrode 620 end or extend into this. The trenches for the STI are then filled by a conventional method and with a suitable insulating material, which is typically an oxide such as SiO.

Thereafter, word line trenches running perpendicular to the isolation trenches and perpendicular to the bit lines are formed by conventional lithography and etching techniques. Since these trenches are perpendicular to the isolation trenches, the silicon of the wafer and the oxide of the STI must be etched. In the drawing, the word line trenches run into the plane of the paper. Their width is indicated by reference numerals 612 specified. The depth of the wordline trenches can either extend into the source plate electrode 620 extend or may end before.

In this way, ie, by etching the iso trenches and the wordline trenches running perpendicularly to them, pillars of silicon have been created that act as active areas 630a . 630b serve to be formed selection transistors.

As well As previously described, after forming the active regions, the Silicon of the columns optionally by isotropic etching diminished and the nitrite and optional oxide interlayers can be removed become. Thereafter, optionally a sacrifiable oxide layer can be created which serves as protection during subsequent processing steps and which is to be removed before the gate oxide for the transistor is produced or deposited.

In the event that the wordline trenches do not extend into the source plate electrode, the bottom of the wordline trenches N + is implanted to galvanize the bottom of a wordline trench with the sourceplate electrode 620 optionally, a sidewall spacer (not shown) can be formed to ensure that only the floor is implanted.

Farther can further implantations take place at this time of production, around the PN junctions of the Transistors to create or adjust.

Before the gate oxide layer is produced, remove the optional sacrificial oxide layer, if prepared. Subsequently, a layer of electrically insulating material, typically an oxide, such as SiO, is formed on the sidewalls of the active region so as to form a layer of insulating material, called the gate oxide layer 650a . 650b serves.

After the gate oxide layer has been formed, the remainder of the wordline trenches is filled with polysilicon around the gate electrodes 640a and 640b to build. In this drawing, the gate electrodes form 640a and 640b a dual gate electrode for the active area 630a , The deposited gate electrode material may optionally be planarized by conventional planarization processes such as chemical mechanical polishing (CMP) with respect to the nitrite blanket layer.

In contrast to the processing as described in the process steps for the production of the buried metal word line, the nitrite intermediate layer is removed, so that the thick oxide layer 614 remains on the surface of the chip. Subsequently, the layers for the gate line are deposited. That is, an optional layer of polysilicon 660 a metal layer 670 for forming the word line and a layer of insulating silicon nitrite (SiN) 680 are applied in this order on the surface of the chip by conventional deposition techniques.

Subsequently, this stack of layers is processed by conventional lithography and etching processes to form a gate line. That is, the three layers are formed into conductors that are placed on the gate electrodes and thus form conventional metal word lines that are on the gate electrodes 640a and 640b placed and electrically connected to these.

During and after the three layers have been formed into conductors, suitable intermediate layers and sidewall spacers of oxide and / or silicon nitride are formed around the sidewalls of the conductors opposite the active regions 630a . 630b and electrically isolate the bottom electrodes formed on the active regions.

In subsequent process steps become the active areas 630a and 630b connected to volumes of, for example, phase change material, which in turn are connected to a bit line. Accordingly, there may be auxiliary implantations to dope the active regions with N + and the contact area of the active regions may be broadened by selective epitaxial growth of silicon. At this time, the contact resistance can be reduced by means of a salicidation process. Regions or spaces between the various functional elements that have been formed so far are now filled with a filling dielectric, which is typically an insulating oxide such as silicon oxide SiO 2. This layer is then planarized.

Subsequently and using contact lithography, a selective etching is performed, wherein the etching selective to the gate electrodes covering silicon nitrite or the gate ladder is to expose the surface of the active areas.

A Follow-up implantation can be performed to increase the conductivity between the active areas and the ground electrodes to be formed improve.

Subsequently, under Use of conventional Process steps formed bottom electrodes on the active areas become. Subsequently become volumes of phase change material or other suitable switching active material formed and connected at one end to the bottom electrodes. On the volume of switching active material become accompaniments educated.

7 shows a schematic circuit 700 an alternative embodiment of the above described an arrangement of memory cells is exemplified by the memory cell simulation 710 . 711 . 712 . 713 . 714 , The memory cells are identical to the cell 710 and have a volume of resistive switching material 720 and a dual gate selection transistor 740 on. As shown, all of the selection transistors are connected to a common source line, which is formed as a source plate electrode and which may be connected to ground or ground potential. The drain of each selection transistor is coupled to a volume of switching active material, which in turn is coupled to a bit line, such that each memory cell connects a transistor to a bit line through a resistive switching memory element.

The Selection transistors are dual-gate transistors. Every gate electrode a transistor is coupled to another word line. Accordingly is to open a selection transistor, a gate voltage to two - adjacent - word lines to apply.

The memory cells are arranged such that the drains of the selection transistors of adjacent memory cells in the direction of the word lines 760 to 764 whose gate electrodes are respectively coupled to the same word line are coupled to different bit lines, the next cell being coupled to the next but one bit line.

Likewise are in the direction of the bit lines 730 . 731 adjacent memory cells connected to the same bitline are coupled to different wordlines. Such are, for example 710 and 712 both with the bit line 730 and are adjacent to each other in the direction of the bit line. The gate electrodes of the selection transistor of the cell 710 are to the wordlines 760 respectively. 761 coupled and the gate electrodes of the selection transistor of the cell 712 are to the wordlines 762 respectively. 763 coupled. In this way, memory cells coupled to the same bitlines are coupled to different wordlines and, in other words, cells coupled to the same wordline are coupled to different bitlines.

consequently For example, a memory cell may be selected by selecting a bit line and a bit line Pair of word lines selected However, unlike the embodiment described above in the Choose a memory cell by applying a voltage to the bit line and the corresponding word lines, the gate voltage of an adjacent one Memory cell in the bit line direction remains untouched. Accordingly have to in this embodiment the transistors are not considered completely depleted transistors be educated.

The Memory cells and thus the corresponding transistor cells are placed at the intersections of word line pairs with bit lines, wherein the cells are arranged like a checkerboard. That is, in the word line direction are the cells of every second intersection of a pair of Word lines and a bit line placed and each one intersection offset to the adjacent row of cells, so that In the bit line direction, the cells are also placed at every second intersection are.

8th Fig. 10 is a plan view showing a modification of the above-described embodiment, showing an arrangement of memory cells 800 that has dual gate transistors and bulk switching active material. Similar to the embodiment described above, a first and a second bit line are 810 respectively. 820 the topmost elements in this view, which exemplarily show a plurality of parallel bitlines and which are placed above the surface of the original wafer. A first and a second wordline 830 respectively. 840 illustrate a plurality of parallel wordlines buried beneath the bitlines and at least partially buried beneath the surface plane of the original wafer, and thus below the surface plane. Each wordline forms a plurality of gate electrodes facing the active regions through a layer of gate dielectric 850 is isolated, which may be an oxide such as silica.

Areas between the bit lines and also between the word lines - referenced by reference numerals 870 - are filled with an insulating material, which forms a shallow trench isolation (STI). reference numeral 860 denotes the placement - circled in the drawing - of the active areas of transistors placed under the bitlines and between the wordlines.

In this embodiment the active areas are offset from one another. Compared with the previously described embodiment is surrounded every second transistor omitted, either in bit line or in word line direction.

This arrangement has the advantage that each transistor, and accordingly each memory cell comprising a transistor, can be selected by applying a suitable voltage to a bit line and two word lines, the voltage applied to the word lines leaving the transistor adjacent in the bit line direction untouched, ie , the gate voltage applied to the word lines has no influence on a gate electrode of an adjacent transistor. Consequently, in selecting a transistor, the conductivity of the adjacent transistor remains unaffected and accordingly, the transistors need not be completely depleted transistors.

The list of reference numerals 880 arrows indicate the periodicity of bit lines in word lines, each being 2 F, although the drawing is not drawn to scale. Accordingly, the cell size of a memory cell is about 8F2.

9a shows a cross section through a memory cell comprising a transistor, wherein the direction of the cutting line is in the direction of a bit line.

Similar to the arrangement in 3 exist in the wafer 910 a source plate 920 made of N + doped semiconductor material, wherein the source plate may be coupled, for example, to ground or ground potential and thus serves as ground or ground electrode. A transistor body 930 of lightly P-type doped silicon is at its lower end to the source plate electrode 920 and at its opposite end, which is the drain 960 of the transistor, to a bottom electrode 970 coupled, which in turn to a volume resistive switching material 980 is coupled. The volume of resistive switching material is in turn connected to a bit line 990 coupled. word lines 940a . 940b are on opposite sidewalls of the transistor body 930 arranged and thus form the gate electrodes of the transistor and are opposite the Transistorbody by a gate dielectric 950a respectively. 950b electrically isolated from this.

As in 7 As shown, the gate electrodes abut shallow trench isolation insulating material 9100 , In contrast to the first embodiment, adjacent cells in the bit line direction have no common or shared gate electrode. Instead, adjacent transistors in the bit line direction have a pair of gate electrodes formed by a pair of parallel word lines, not shown in this view.

9b shows a cross section through the structure in the word line direction, ie perpendicular to the section line as in 9a , A transistor body 930 formed of lightly P doped semiconductor material, a selection transistor, is formed on and electrically coupled to an N + -type source plate electrode formed in the substrate 910 is formed of the wafer. The bottom of the body 930 thus forms the source of the transistor. The upper end of the transistor body 930 , indicated by numeral 960 , N + is doped and forms the drain of the transistor, which is connected to a bottom electrode 970 coupled, in turn, with a volume resistive switching material 980 connected is. The volume of resistively switching material is a bit line 990 connected. The insulating material of a shallow trench isolation 9100 is between two opposite sidewalls of a transistor body 930 places and thus separates this transistor body from a transistor body adjacent in the word line direction.

In this view, the word lines forming the gate electrodes are placed in front of and behind the plane of the paper. The dashed line 940 intended to indicate the placement of the gate electrodes in front of and behind the plane of the paper.

As shown in the drawing, the extension of the transistor body is 930 in the direction of the cutting line considerably larger than in the bit line direction and also larger than shown in the first embodiment. In this way, a transistor body can be achieved with a cross section larger in the current flow direction, in which view the current flow is vertical. This is advantageous in particular for resistively switching memory cells, because a large current is necessary for changing the resistance in the volume of the resistively switching memory cell. Thus, in the exemplary embodiment illustrated, the extension of the transistor in the word-line direction may be up to 3F.

The described alternative embodiment the arrangement of vertical transistors can be achieved by means of one of the two for the first embodiment However, using the masks to create the Transistors and to subsequently create the memory elements so to change are that every other cell is left out to an offset Arrangement of memory cells like to reach on a chessboard.

Claims (42)

Arrangement of transistors ( 140 . 141 ) in a substrate for selecting one of a plurality of memory cells ( 110 . 111 ), each memory cell ( 110 . 111 ) a transistor ( 140 . 141 ) via a memory element ( 120 . 121 ) with a bit line ( 130 ) and by selecting two word lines ( 160 . 161 ) and the bit line ( 130 ), wherein the array of transistors is formed by a plurality of word line trenches forming strips of substrate material and serving as active regions ( 330a . 330b ) of transistors ( 140 . 141 ), wherein the strips are separated by sections of isolation trenches, so that the word line trenches separate transistor cells in a first direction and the sections of the isolation trenches separate the transistor cells in the direction of the word lines (FIG. 160 . 161 . 162 . 340 ), wherein a word line trench is a word line ( 340 ) and a first word line ( 340 ) in a first word line trench a plurality of gate electrodes on a sidewall of active regions ( 330a . 330b ) of a first and a second, adjacent row of transistor cells in the word line direction, and wherein a second word line in an adjacent word line trench, a plurality of gate electrodes on the opposite side wall of the active regions ( 330a . 330b ) of the second and third rows of transistor cells in the word line direction. Arrangement according to claim 1, wherein the surface of the substrate is a reference plane ( 311 ) and wherein each body of a transistor ( 140 . 141 ) vertically above the source and the drain ( 360a . 360b ) is arranged vertically above the body of the transistor. Arrangement according to one of the preceding claims, wherein the word lines ( 160 . 161 . 340a . 340b ) below the surface plane of the original wafer ( 310 ), in which the transistor arrangement is formed, is buried. Arrangement according to claim 2, wherein a layer is doped within the substrate with a dopant and a conductive layer ( 320 ) and the vertical transistors with their source / drain ( 360a . 360b ) with the conductive layer ( 320 ) are connected. Arrangement according to claim 4, wherein the conductive layer ( 320 ) is connected to earth / ground potential and forms a source plate electrode. Arrangement according to one of the preceding claims, wherein each transistor ( 140 ) is designed so that a considerable current flow in a transistor cell ( 140 ) is achieved in a second series of transistor cells only if a gate voltage is simultaneously applied to the first and second word lines ( 160 . 161 ) is applied to the transistor ( 140 ). Arrangement according to one of the preceding claims, wherein the material of the word lines ( 160 . 161 ) is a metal. Arrangement according to one of the preceding claims, wherein the memory cells ( 110 . 111 ) Are phase change memory cells and the memory elements are corresponding volume resistively switching material. Arrangement according to one of the preceding claims, wherein the memory cells are phase change memory cells and the memory elements accordingly Are volumes of phase change material. Arrangement according to one of the preceding claims, wherein the vertical extent of the isolation trenches is chosen so that body areas adjacent transistor cells completely isolated from each other are. Arrangement according to one of the preceding claims, wherein the vertical extent of the isolation trenches is smaller than the height of the body a transistor cell, so that a charge carrier flow between body areas adjacent transistor cells possible is. Arrangement of Vertical Transistors in a Substrate ( 510 ) for selecting one of a plurality of memory cells ( 110 . 111 ), each memory cell ( 110 . 111 ) a transistor via a memory element ( 120 . 121 ) to a bit line ( 5110 ) and by selecting two word lines ( 540a . 540b ) and the bit line ( 5110 ), and wherein the array of vertical transistors is formed by a plurality of word line trenches which form strips of substrate material which act as active regions ( 530a . 530b ) of transistors, the strips being separated by sections of isolation trenches so that the word line trenches separate transistor cells in a first direction and the portions of the isolation trenches isolate the transistor cells from one another in the direction of the word line trenches, wherein a word line trench forms a row of gate electrodes ( 540a . 540b ) receives a series of adjacent transistor cells in the word-line direction, the gate electrodes ( 540a . 540b ) with a gate line ( 570a . 570b electrically connected, which is placed above the word line trench, wherein a first series of gate electrodes ( 540a ) in a first word line trench a plurality of gate electrodes on a sidewall of active regions ( 530a ) in a first and a second, adjacent row of transistor cells in the word-line direction, and wherein a second row of gate electrodes ( 540b ) in a neighboring word line trench, a plurality of gate electrodes on the opposite side wall of the active regions ( 530a ) of the second and third rows of transistor cells in the word line direction. Transistor arrangement according to claim 12, wherein the material of the gate electrodes ( 540a . 540b ) Is polysilicon and the material of the gate lines ( 570a . 570b ) contains a metal. A transistor arrangement according to claim 13, wherein said Material of the gate line contains or is tungsten. Arrangement according to one of the preceding claims 12-14, wherein the gate electrodes ( 540a . 540b ) below the surface level ( 511 ) of the original wafer in which the transistor arrangement is formed. Arrangement according to one of the preceding claims 12-15, wherein a layer within the substrate ( 510 ) is doped with a dopant to form a conductive layer ( 520 ) and wherein the sources or drains of the vertical transistors with the conductive layer ( 520 ) are connected. Arrangement according to claim 16, wherein the conductive layer ( 520 ) is connected to ground / ground potential and thus forms a source plate electrode. Arrangement according to one of the preceding claims 12-17, wherein each transistor is designed such that a considerable current flow in a transistor cell of a second series of transistor cells is only achieved, if at the same time a gate voltage to the first and second word line ( 570a . 570b ) is created. Arrangement according to one of the preceding claims 12-18, wherein the memory cell is a phase change memory cell and the memory element Accordingly, a volume of phase change material. Arrangement according to one of the preceding claims 12-19, wherein the vertical extent of the isolation trenches is selected such that active areas ( 530a . 530b ) of adjacent transistor cells are completely isolated from each other. Arrangement according to one of the preceding claims 12-19, wherein the vertical extent of the isolation trenches is less than the vertical extent of the active area of a transistor cell and, accordingly, a carrier flow between active areas ( 530a . 530b ) of adjacent transistor cells. Method for producing a vertical transistor cell arrangement in a substrate, comprising the following method steps: producing a conductive layer ( 320 ) within the substrate ( 310 ), wherein the conductive layer is covered by a less conductive and at least partially oppositely doped substrate layer; Forming a plurality of parallel isolation trenches along a first direction and filling the isolation trenches with an insulating material; Forming a plurality of parallel wordline trenches along a second direction perpendicular to the first direction such that active areas of transistor cells are formed as columns of substrate material; Generating a layer of gate dielectric ( 350a ) in a first word line trench and then filled with egg nem conductive material for forming gate electrodes ( 340a . 340b ) on a side wall of a first ( 330a ) and a second, adjacent row of active regions in the word-line direction to form a wordline; Generating a layer of gate dielectric ( 350b ) in at least one second adjacent word line trench and subsequently filling with a conductive material for forming gate electrodes ( 340b ) on an opposite side wall of the first row of active areas and on a side wall of a third, adjacent row of active areas ( 330b ) in the word line direction for forming a second, adjacent word line. The method of claim 22, wherein the conductive material comprising the gate electrodes ( 340a . 340b ) is a metal. Method according to one of the preceding claims 22-23, wherein the word line trenches extend into the conductive layer ( 320 ). Method according to one of the preceding claims 22-24, wherein the depth of the isolation trenches is selected such that it extends to at least the drain regions of the active regions ( 330a . 330b ) and allows galvanic connection between adjacent active regions in the word line direction. Method for producing an array of vertical transistor cells in a substrate ( 510 ), comprising the following method steps: producing a conductive layer ( 520 ) within the substrate ( 510 ), the conductive layer ( 520 ) is covered by a less conductive substrate layer; Forming a plurality of parallel isolation trenches along a first direction and filling the isolation trenches with an insulating material ( 5120 ); Forming a plurality of parallel wordline trenches along a second direction perpendicular to the first direction so as to form pillars of substrate material extending from the substrate (12); 510 ) and as active areas ( 530a . 530b ) of transistor cells serve; Generating a layer of gate dielectric ( 550a ) in a first word line trench and then filling the word line trench with a gate electrode material, so that gate electrodes ( 540a ) are formed on a side wall of a first and a second, adjacent row of active regions in the word line direction, so that the gate electrodes ( 540a ) form a wordline; Generating a layer of gate dielectric ( 550b ) in at least one second, adjacent Wortlei trench and subsequent filling with a conductive material for forming gate electrodes ( 540b ) on an opposite sidewall of the first row of active regions and on a sidewall of a third, adjacent row of active regions in the wordline direction, such that a second adjacent wordline is formed; Formation of gate leaders ( 570a . 570b ) on the gate electrode material, wherein the gate conductors are coupled to the gate electrodes and above the original surface plane (FIG. 511 ) of the substrate is placed. The method of claim 26, wherein the material of the gate electrodes ( 540a . 540b ) Polysilicon and the material of the gate lines ( 570a . 570b ) is a metal. Method according to one of the preceding claims 26-27, wherein the word line trenches extend into the conductive layer ( 520 ). A method according to any one of the preceding claims 26-28, wherein the depth of the isolation trenches is chosen to be at least half the length of a conductive channel in an active region ( 530a . 530b ) and a galvanic connection between adjacent active areas ( 530a . 530b ) is maintained in the word line direction. Method for operating a double-gate transistor, wherein the transistor is an active region ( 330a . 530a ), a first gate electrode ( 340a . 540a ) located on a first side wall of the active area ( 330a . 330b ) is arranged and a second gate electrode ( 330b . 530b ) located on the opposite side wall of the active area ( 330a . 530a ), wherein the first gate electrode ( 340a ) coupled to a first word line and the second gate electrode ( 340b ) is coupled to a second word line, and wherein the transistor may have a first state determined by a first voltage applied to both word lines to open the transistor, and a second state used to lower the conductivity of the transistor by at least one order of magnitude is defined by a third voltage applied to the first word line and a fourth voltage applied to the second word line. Method for operating a first and a second adjacent double-gate transistor ( 140 . 141 ) in an array of dual gate transistors, the first dual gate transistor ( 140 ) a first to a first word line ( 160 ) coupled gate electrode and a second to a second word line ( 161 ) has a coupled gate electrode, and the second double-gate transistor ( 141 ) a first to a third word line ( 162 ) has a coupled gate electrode and a second gate electrode connected to the second word line ( 161 ), such that the first and the second transistor ( 140 . 141 ) to the second word line ( 161 ) have in common coupled gate electrode, wherein when opening the first transistor ( 140 ) a positive gate voltage to the first and second word line ( 160 . 161 ) and earth potential or a negative voltage to the third word line ( 162 ) for closing the second transistor ( 141 ) is created. Arrangement of transistors in a substrate for selecting one of a multiplicity of memory cells ( 980 ), each memory cell each having a transistor via a respective memory element ( 980 ) to a bit line ( 990 ) and by selecting a pair of word lines ( 940a . 940b ) and a bit line extending perpendicularly thereto ( 990 ), wherein the transistor arrangement is formed by a multiplicity of word line trenches which form strips of substrate material which are used as active transistor regions ( 930 ), wherein the strips are separated by sections of isolation trenches so that the word line trenches separate the transistor cells in a first direction and the sections of the isolation trenches separate the transistor cells in the direction of the word line trenches, wherein a word line trench forms a word line ( 940a . 940b ), and wherein a first word line ( 940a ) of a couple ( 940a . 940b ) of word lines a plurality of gate electrodes ( 940a ) on a sidewall of active areas ( 930 ) forms a row of transistor cells in the word line direction, and the other word line ( 940b ) of the pair a plurality of gate electrodes ( 940b ) on the opposite side wall of the active areas ( 930 ) of the series of transistor cells in the word-line direction, and wherein the transistors at each second intersection of a pair of word lines ( 940a . 940b ) with a bit line ( 990 ), wherein the transistors in adjacent rows are arranged offset around a bit line, so that the transistors are arranged like a checkerboard. Arrangement according to claim 32, wherein the surface of the Substrate forms a reference plane, wherein each body of a transistor vertically above the source and the drain vertically over the body of the transistor are arranged. Arrangement according to claim 32, wherein the word lines ( 940a . 940b ) are buried below the surface of the original wafer in which the transistor array is formed. Arrangement according to claim 33, wherein within the substrate ( 910 ) a layer is doped with a dopant to a conductive layer ( 920 ) and wherein the sources or drains of the transistors are connected to the conductive layer. Arrangement according to claim 35, wherein the conductive layer ( 920 ) is connected to ground potential or ground potential and thus forms a ground electrode. Arrangement according to one of the preceding claims 32-36, wherein each transistor is designed such that a remarkable current flow in a transistor cell in a second row of transistor cells is only achieved when a gate voltage to the first and second word line ( 940a . 940b ) is applied to turn on the transistor. Arrangement according to one of the preceding claims 32-37, wherein the material of the word lines ( 940a . 940b ) is a metal. Arrangement according to one of the preceding claims 32-38, wherein the memory cell is a resistive switching memory cell and the Memory element accordingly a volume resistive switching Material is. Arrangement according to claim 39, wherein the memory cell a phase change memory cell and the memory element accordingly is a volume of phase change material. Arrangement according to one of the preceding claims 32-40, wherein the vertical extent of the isolation trenches is chosen so that these are the body areas adjacent transistor cells completely isolated from each other. Arrangement according to one of the preceding claims 32-40, wherein the vertical extent of the isolation trenches less than the vertical Extension of the body of a transistor cell is, so a charge carrier flow between body region of adjacent transistor cells is possible.