DE10139431C2 - Method for forming isolation trenches between active areas in the manufacture of a semiconductor integrated circuit - Google Patents

Description

The invention relates to a method for forming iso lation trenches between active areas in manufacturing of integrated semiconductor circuits, in particular DRAM Semiconductor memories, with the aim of the contact resistance to reduce between storage capacitor and selection transistor gladly. A method according to the preamble of claim 1 known from US-A-5177576. Another procedure is in in US-A-5953607.

With electronic integrated circuits (ICs) the degree of integration or the packing density, that's the approach Number of functional elements per unit area, always larger. Because of the constant and ongoing demand for halble storage with more and more storage capacity, so increase the degree of integration, the great regularity of the design and the considerable range of applications are the DRAMs (Dynamic Random Access Memory, dynamic memory with choice free access) to the pacemaker for microelectronics Service. The 256 Mb DRAM with structure widths of 0.25 µm is already standard, the 1 Gb DRAM within reach.

The ones that appear with the advancing miniaturization However, problems arise in physical, technological shear and circuit technology always a lot ger.

An outstanding element of the overall process for the manufacturer position of 256 Mb DRAMS in 0.25 µm technology is next to the already extremely fine structures, the three-dimensional Integration of the memory cells using trench memory probes capacitors (trench capacitors). The storage capacitors are perpendicular to the substrate surface in the substrate etched deep trenches ("Deep Trench", DT) educated.  

Above and next to the deep trenches for the storage condenser Ren are spread on the substrate surface using planar technology fen-shaped selection transistors. The electric one Connection of a selection transistor to the corresponding memory The capacitor is made by overlapping the active one Area of the selection transistor with the storage capacitor. The connection area of the active area becomes "Buried Strap" (BS) called.

Under trench isolation or STI or shallow trench isolation one understands the lateral isolation of neighboring Transisto and other active areas due to relatively shallow trenches, etched into the monocrystalline silicon of the substrate and with insulating material. The ditch is there at between the active areas with the desired field Oxide thickness etched anisotropically into the substrate. To a short thermal oxidation is followed by a conformal oxide deposition to fill up these isolation trenches.

In the case of the DRAMs mentioned, not only is the mutual lateral isolation of the strip-shaped active regions for the selection transistors in STI technology also carried out with elongated, strip-shaped isolation structures, but it is also used to separate the successive strips in the longitudinal direction of the MOS selection transistors within the individual Strips short, rectangular, flat isolation trenches are formed, which are filled with SiO ₂ . These isolation trenches are located between two storage capacitors and adjoin them. They also connect the two lateral isolation trenches that lie next to the active areas for the selection transistors.

To prevent the active areas of the MOS selection transistors with the buried strap connection areas, yes consist of a conductive material such as polysilicon until in the insulation area between two storage capacitors sufficient and deteriorate the insulation or by bridging  of the isolation trench, he must do so called head-to-head distance of the individual active areas in a strip so that the un avoidable errors in the position of the lithography processes ven areas do not protrude into the isolation area.

However, this now has the disadvantage that the active areas or the buried strap connection area of the selection transistors not over the entire cross section of the storage capacitor enough, but for the reasons mentioned about a certain technology-dependent measure of the edge of the storage condenser tors back, which in turn is located in an isolation area and the next storage capacitor directly with it whose selection transistor is opposite. In other words is the cross section for the passage of current from storage con capacitor to the active area of the selection transistor is not so big as it could theoretically be. The cross section however, directly affects the contact resistance between Storage capacitor and selection transistor that as low as should be possible.

A varying position error also changes the cross-section of the spit covered by the connection area cherkondensators and thus the connection resistance with which Result of undesirable fluctuating electrical properties of the system storage capacitor selection transistor.

The object of the invention is therefore to create a method with which the contact resistance between storage probes sator and selection transistor by maximizing the overlap between the active area of the selection transistor and the Cross section of the storage capacitor constant and closed can be reliably reduced to the lowest possible level can.

This object is achieved with the in claim 1 described method solved. Advantageous configurations  of the inventive method are in the subclaim cited.

In the present invention is characterized by a particularly critical direction, the longitudinal direction of the strips with the active areas for the selection transistors themselves technology step adjusting the active area to the Edge of the storage capacitor performed without the risk there is that the active area in the isolation area between the storage capacitors or the isolati even bridged. The technology step leading to the "semi-self-aligned buried strap" (SSBS) of the active Ge leads leads consists in that in the first structuring part for the active area the shallow isolation trench between the deep trenches of the storage capacitors with one in the critical strip length direction self-aligning Process is generated. The self-alignment is through the Characteristics of the applied HDP process (HDP: High Den sity plasma) for oxide deposition Is liert that on the narrow substrate areas between the deep trenches for the storage capacitors that are in the process stage with a thin layer of silicon are covered with nitride and are higher than the polysili zium surface in the storage capacitor trenches, the sputter Component of the plasma deposition is set so that this narrow nitride web between the storage condensate oxide does not grow higher than in the adjacent, recessed storage capacitor areas. The sputtering process is known to attack more non-horizontal areas, such as the flanks of the oxide over the nitride webs, on than on hori zonal areas, so that it is possible by adjusting the Sputtering component the growth of a "cone" over the to prevent narrow nitride bars.

Then the one covered with relatively little oxide Expose nitride in the narrow webs, for example through reactive ion etching of the HDP oxide up to the upper edge of the  Nitrids, whereupon both the nitride on the later Isola tion trench as well as the substrate silicon in this trench can be selectively etched away.

With this procedure, the polysilicon remains in the deep trenches of the storage capacitors in the direction the strip of the active areas of the selection transistors stand completely, that means it stays exactly to the edge of the storage capacitor. This polysilicon forms but at the same time the buried strap of the active area, so that the overlap between the cross section of the storage probe sators with the active area to the edge of the storage con range and the active area is the cross section of the Storage capacitor accordingly to the greatest extent possible covers. The contact resistance between the selection transistor and The storage capacitor thus has the smallest possible value.

By self-aligning the process to the original Chen edge of the storage capacitor changes the Kon clock area between storage capacitor and selection transistor also not by position errors and the like, so that the over resistance to the selection transistor has a constant value has.

An embodiment of the invention will follow hand of the drawing explained in more detail. Show it:

Figure 1 is a schematic plan view of the arrangement of storage capacitors and selection transistors in a DRAM. and the

Fig. 2 to 11 steps of a method with which self-adjustment of the active region of a selection transistor in the region of the overlap with a storage capacitor in the longitudinal direction is possible.

Fig. 1 of the drawing shows schematically and greatly simplified a supervision of the arrangement of storage capacitors and selection transistors in DRAMs. In this plan view, the drawing plane corresponds to the substrate surface or is parallel to it. The storage capacitors 1 are formed in deep trenches perpendicular to the plane of the drawing or the upper surface of the substrate, so that the storage capacitors 1 can practically be seen in cross section in the plan view of FIG. 1.

Two adjacent storage capacitors 1 are shown. Each storage capacitor 1 is followed by the active region 2 of a selection transistor, which also partially overlaps the storage capacitor 1 . The active areas 2 of the selection transistors represent strip-shaped images. The active areas are separated within a strip between two adjacent storage capacitors 1 by a flat isolation trench 3 in the substrate into the areas for the individual selection transistors.

The electrical connection between the storage capacitor 1 and the active region 2 of the associated selection transistor is made by the overlap 4 of the active region 2 with the storage capacitor 1 .

Conventionally, the overlap 4 between the active area 2 and the storage capacitor 1 is smaller than the storage capacitor 1 is wide in the longitudinal direction of the stripes for the active areas. The active region 2 ends in each case in a head 5 which, as shown in solid lines in FIG. 1, lies somewhere on the storage capacitor 1 . The mi nimal head-to-head distance between two opposite active areas and thus the extent of the overlap 4 is limited by the process window of the lithography process for the separation of the individual selection transistors and the positional errors between the structures for the storage capacitor 1 and the active area 2nd In other words, the head-to-head distance between the ends or heads 5 of the active areas for the selection transistors is determined by the lithography processes for the storage capacitors 1 , the selection transistors and the isolation trench 3 in between and cannot be reduced arbitrarily without that the Ge driving exists that one of the heads 5 comes to lie in an undesired area such as the isolation trench 3 and the yield in the DRAM production is drastically reduced by short circuits and the like.

On the other hand, the extent of the overlap 4 between the active region 2 and the cross section of the storage capacitor 1 also determines the electrical properties of the storage capacitor selection transistor system, that is to say in particular the contact resistance of the storage capacitor 1 to the selection transistor. From this point of view, the overlap should be as large as possible and always have the same area.

Referring to Figs. 2 to 11, a method will now be described, with the self-alignment of the active region 2 of the strip from the active regions is possible select transistor in the region of overlap the storage capacitor 4 with 1 in the longitudinal direction. Figs. 2 to 11 each show a section through the semiconductor substrate perpendicular to the substrate surface (and hence perpendicular to the plane of Fig. 1), in each case in figure part I, the viewing direction perpendicular to the word line of the DRAM memory cell is located and in figure part II parallel to the word line.

Fig. 2 shows the starting situation is. In the silicon substrate 10, deep trenches 12 are etched which are to just un ter filled with polysilicon, the substrate surface fourteenth On the trench walls, the polysilicon 14 is separated from the silicon of the substrate 10 by a thin dielectric, for example an SiO ₂ layer 16 . The SiO ₂ layer 16 ends well below the substrate surface.

A nitride layer 18 (Si ₃ N ₄ ) is applied to the surface of the silicon substrate 10 outside the trenches 12 . The nitride layer, here designated 18 ', also covers the thin web 10 ' made of the monocrystalline silicon of the substrate 10 between the two closely spaced trenches 12 .

The polysilicon 14 in the trenches 12 is not covered; the surface of the polysilicon 14 is lower than the surface of the nitride layer 18 , 18 ', so that an edge is formed at the edge of the trenches 12 .

In the drawings, the different dopings in the individual areas of the silicon substrate 10 are not particularly shown.

As shown in FIG. 3, an oxide 20 is now applied to the surface of this structure by means of a special plasma deposition which has an adjustable backsputter component, namely a high-density plasma deposition (HDP process). The HDP process is carried out so that the sputtering component is relatively large, so that due to the increased sputtering of flanks on the nitride 18 'of the thin webs 10 ' between the trenches 12 of adjacent storage capacitors, no cone grows, but the HDP oxide 20 on this narrow nitride strip 18 ′ has essentially the same height as on the polysilicon 14 of the trenches 12 .

It is important that the webs 10 'protrude beyond the surface of the polysilicon 14 in the trenches 12 , so that when the oxide 20 is deposited on the polysilicon 14 and the nitride 18 ' of the web 10 ', flanks result which sputter more strongly are like the horizontal surfaces over the poly silicon 14th It can thus be achieved that less oxide 20 lies above the nitride 18 'on the web 10 ' (this area is highlighted in FIG. 3 by a circle) than over the nitride 18 in the other areas of the substrate 10 .

On the remaining areas of the substrate surface, which are essentially formed by relatively large-area horizontal surfaces, a considerably thicker oxide grows on this topology-dependent, non-conformal deposition because of the lower backsputter rate than over the trenches 12 and the nitride 18 'of the web 10 '.

As shown in FIG. 4, the next step is anisotropic RIE etching back (reactive ion etching) of the HDP oxide 20 up to the upper edge of the nitride 18 'on the narrow webs 10 ' between the trenches 12 . The surface of the nitride forms the defined end point of the etching process. Oxide 20 remains above nitride 18 on the other areas of substrate 10 .

Fig. 5 This is followed by a selective nitride etch, the nitride 18 'on the web 10' is completely removed between the trenches 12th The nitride layer 18 in the other areas next to and outside the trenches 12 is not etched away, since it is protected by the HDP oxide 20 which has remained during RIE etching back. This step is in turn followed by a selective silicon etching, with which the silicon in the web 10 'between two trenches 12 for later isolation of the active regions of the selection transistors is etched away to the target depth of the isolation trench 22 thus formed. The isolation trench 22 of FIGS. 5 to 11 otherwise corresponds to the isolation trench 3 of FIG. 1 in a side view.

Fig. 6 Around the dielectric (SiO ₂ ) 16 at the edge of the trenches 12 with the polysilicon 14 in the so-called collar area (collar area), in which it was exposed by the silicon etching step of FIG. 5 from the isolation trench 22 , the steps followed protect, the isolation trenches 22 are filled up to above the height of the dielectric 16 with a material 24 such as photoresist (resist) or an ARC coating (anti-reflective coating). For this purpose, the photoresist or the ARC is brought on and etched back to the extent or to such a depth that the surface of the photoresist or ARC material 24 in the isolation trench 22 lies above the upper end of the dielectric 16 .

Fig. 7 In the next step, both the HDP oxide 20 from the substrate surface and the photoresist or ACR material 24 are removed from the shallow isolation trenches 22 .

Fig. 8 on the substrate surface, an oxide hard mask 26 and then an ARC material and / or a photoresist 28 is brought up. The oxide hard mask 26 is deposited in such a way that an essentially flat surface is obtained, which at most is slightly dented with the polysilicon 14 in the region of the trenches 12 . The photoresist 28 is then structured to form the stripe structure for the active areas.

Fig. 9 There is an etching to open the oxide hard mask outside the strip with the active areas up to the top silicon edge and the removal of the photoresist 28th

Fig. 10 and Fig. 11 there is an etching with the hard mask as a mask to the target depth of the lateral isolation trenches 30 which run parallel to the strips of the active areas and electrically separate these strips from each other, and the removal of the hard mask.

As described, accordingly, as shown in dashed lines in FIG. 1, by the self-adjusting steps of applying an oxide in the region of the later isolation trench 3 in the particularly critical direction, the longitudinal direction of the strips with the active regions 2 has a smaller thickness than on the rest of the substrate surface, and the etching away of the oxide and of the selective nitride etching in the area of the isolation trench 3, the active region 2 is guided to the edge of the cross section of the storage capacitor 1 , without the risk that the head 5 of the active areas protrudes into the isolation area between the storage capacitors and the active areas or even bridges the isolation area. The essential point for the self-adjustment is that the process for the oxide deposition is carried out in such a way that less oxide grows on the narrow nitride webs between the storage capacitors, depending on the topology and not conforming, than in the other substrate areas.

Then the one covered with relatively little oxide Expose nitride in the narrow webs, for example through reactive ion etching of the HDP oxide up to the upper edge of the Nitrids, whereupon both the nitride on the later Isola tion trench as well as the substrate silicon in this trench can be selectively etched away.

With this procedure, the polysilicon remains completely in the deep trenches of the storage capacitors. This polysilicon, which is denoted in FIG. 11 by 14 ', however, simultaneously forms the buried strap of the active area, so that the overlap of the storage capacitor with the active area extends to the edge of the storage capacitor and the active area is the cross section of the storage device covers the largest possible extent. The transition resistance between the selection transistor and the storage capacitor thus has the smallest possible value. Due to the self-adjustment of the buried strap technology, the value of the contact resistance is always the same.

LIST OF REFERENCE NUMBERS

1

storage capacitor

2

active area for selection transistor

3

isolation trench

4

Overlap (between

1

and

2

)

5

Head (of active area)

10

Silicon substrate

10

'Bridge (between two trenches

12

)

12

Trench for storage capacitor

14

Polysilicon in the trench

12

14

'' Polysilicon (buried strap)

16

Dielectric (SiO ₂

-Layer)

18

nitride

18

'' Nitride layer on the narrow webs between two storage capacitors

20

HDP oxide

22

Isolation trench (corresponds to

3

)

24

Material (in the isolation trench

22

)

26

oxide hard

28

Photoresist / ARC material

30

lateral isolation trenches
I, II areas (in the semiconductor substrate)

Claims (2)

1. A method for forming isolation trenches ( 3 ) between active areas ( 2 ) in the manufacture of an integrated semiconductor circuit, in which in a semiconductor substrate ( 10 ) for the mutual isolation of the active areas ( 2 ) shallow isolation trenches ( 3 ) are etched , which are filled with an oxide, the flat isolation trenches ( 3 ) adjoining deep trenches ( 12 ) filled with polysilicon ( 14 ), which form storage capacitors ( 1 ), on a silicon surface of the semiconductor substrate ( 10 , 10 ') there is a silicon nitride layer ( 18 , 18 ') everywhere and in the deep trenches ( 12 ) the surface of the polysilicon ( 14 ) is lower than the surface of the silicon nitride layer ( 18 , 18 '), characterized in that an oxide ( 20 ) is applied to the surface of the semiconductor substrate ( 10 ) and the polysilicon ( 14 ) in the deep trenches ( 12 ) by means of plasma deposition with backsputtering, which i in the plasma deposition, the sputtering component is set in order on the silicon nitride layer ( 18 '), which forms narrow webs ( 10 ') between the deep trenches ( 12 ), the oxide ( 20 ) does not grow substantially higher than in the adjacent ones Regions of the deep trenches ( 12 ) with the polysilicon filling, the oxide ( 20 ) thus applied being etched back on the narrow webs ( 18 ') until the surface of the silicon nitride layer ( 18 ') is exposed, and the silicon nitride layer ( 18 ' ), the surface of which is exposed, is selectively removed. 2. The method according to claim 1, characterized in that the plasma deposition is a high-density plasma deposition is.