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CN205609515U - Reliability testing structure - Google Patents

Reliability testing structure Download PDF

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Publication number
CN205609515U
CN205609515U CN201620467514.2U CN201620467514U CN205609515U CN 205609515 U CN205609515 U CN 205609515U CN 201620467514 U CN201620467514 U CN 201620467514U CN 205609515 U CN205609515 U CN 205609515U
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conductive
active area
reliability testing
barrier layer
testing structure
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夏禹
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Tianjin Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Tianjin Corp
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Abstract

本实用新型提供了一种可靠性测试结构,包括:设置有有源区和隔离结构的衬底,需覆盖于隔离结构上的阻挡层,形成于有源区的两端的导电插塞以及与导电插塞点连接的导电层,其中所述有源区、导电插塞及导电层形成串联的结构。当对本实用新型中可靠性测试结构的串联的结构进行电阻测试时,根据检测出的电阻值的大小即可判断出所述有源区与导电插塞的连接状况,从而确认在有源区上是否残留有阻挡层。同时使用本实用新型提供的可靠性测试结构,也可对阻挡层的形成过程进行异常监控。

The utility model provides a reliability testing structure, comprising: a substrate provided with an active area and an isolation structure, a barrier layer to be covered on the isolation structure, conductive plugs formed at both ends of the active area, and a conductive The conductive layer connected by the plug point, wherein the active region, the conductive plug and the conductive layer form a serial structure. When the resistance test is carried out on the series connection structure of the reliability test structure in the utility model, the connection status between the active area and the conductive plug can be judged according to the detected resistance value, thereby confirming that the active area is connected to the conductive plug. Is there any barrier layer remaining. At the same time, the reliability test structure provided by the utility model can also be used to monitor the abnormality of the formation process of the barrier layer.

Description

可靠性测试结构Reliability Test Structure

技术领域technical field

本实用新型涉及半导体制造技术领域,特别涉及一种可靠性测试结构。The utility model relates to the technical field of semiconductor manufacturing, in particular to a reliability testing structure.

背景技术Background technique

在集成电路的制造工艺中,需在器件的部分区域形成金属硅化物,比如有源区与导电插塞连接的位置需要形成金属硅化物以降低接触电阻,提高导电性能。但是,器件的部分区域是不能形成金属硅化物的,如高阻多晶硅、隔离结构等区域。因此在制作金属硅化物之前,应在无需形成金属硅化物的区域形成阻挡层,利用阻挡层不会与金属发生反应的特性,防止在无需形成金属硅化物的区域形成金属硅化物。在形成阻挡层的过程中,需用用到较厚的光刻胶,这就导致同在线间距较小的情况下,于线条的底部位置极易发生由于光刻胶残留而导致的阻挡层残留的问题。若有源区上残留有阻挡层,则后续形成的导电插塞将无法与有源区接触,从而影响器件的性能。In the manufacturing process of integrated circuits, metal silicide needs to be formed in some areas of the device, such as the position where the active region is connected to the conductive plug. Metal silicide needs to be formed to reduce contact resistance and improve conductivity. However, metal silicide cannot be formed in some areas of the device, such as areas such as high-resistance polysilicon and isolation structures. Therefore, before making the metal silicide, a barrier layer should be formed in the area where the metal silicide does not need to be formed, and the barrier layer will not react with the metal to prevent the formation of the metal silicide in the area where the metal silicide is not required to be formed. In the process of forming the barrier layer, a thicker photoresist is required, which leads to the occurrence of barrier layer residue at the bottom of the line due to photoresist residue when the line spacing is small The problem. If the barrier layer remains on the active region, the subsequently formed conductive plug will not be able to contact the active region, thereby affecting the performance of the device.

实践中发现,在严格控制光刻的制程条件下,可基本防止线条的底部发生光刻胶残留。而当光刻的制程条件发生轻微的偏差,甚至是在设备参数或工艺参数的正常范围内波动时,也有可能于线条底部之间的位置出现光刻残留。随着器件尺寸的不断缩小,在需使用较厚的光刻胶的制程中,光刻胶残留以及薄膜残留的问题也越发严重。而根据传统的缺陷检测方法,越来越无法满足需求。例如,利用晶圆检测设备对晶圆进行检测,由于受到晶圆检测设备的检测精度的限制,导致所述检测设备会出现漏检或对于较小的缺陷无法检测的问题。It has been found in practice that under strict control of photolithography process conditions, photoresist residue at the bottom of the lines can be basically prevented. And when the process conditions of lithography deviate slightly, or even fluctuate within the normal range of equipment parameters or process parameters, lithography residues may appear between the bottoms of the lines. As the size of devices continues to shrink, the problems of photoresist residue and film residue are becoming more and more serious in the process of using thicker photoresist. According to the traditional defect detection method, it is increasingly unable to meet the demand. For example, wafer inspection equipment is used to inspect wafers. Due to the limitation of the inspection accuracy of the wafer inspection equipment, the inspection equipment may miss inspection or fail to detect small defects.

实用新型内容Utility model content

本实用新型的目的在于提供一种可靠性测试结构,通过所述可靠性测试结构可有效的检测出于有源区上是否残留有阻挡层,并可对阻挡层的形成过程进行异常监控。The purpose of the present invention is to provide a reliability testing structure, through which the reliability testing structure can effectively detect whether there is a barrier layer left on the active area, and can monitor the abnormality of the formation process of the barrier layer.

在本实用新型提供的可靠性测试结构,包括:衬底、阻挡层、至少两个导电插塞以及导电层,所述衬底中形成有至少一个有源区和位于每个所述有源区周边的隔离结构,所述阻挡层形成于所述隔离结构上,每个所述有源区的两端各形成有至少一个所述导电插塞,所述导电层形成于所述导电插塞的上方,位于同一有源区两端上导电插塞分别与两个不同的导电层连接,以使所述有源区、导电插塞及导电层形成串联的结构。The reliability test structure provided in the utility model includes: a substrate, a barrier layer, at least two conductive plugs and a conductive layer, at least one active region is formed in the substrate and each of the active regions A surrounding isolation structure, the barrier layer is formed on the isolation structure, at least one conductive plug is formed at both ends of each active region, and the conductive layer is formed on the conductive plug Above, the conductive plugs located at both ends of the same active region are respectively connected to two different conductive layers, so that the active region, the conductive plugs and the conductive layer form a serial structure.

可选的,在所述可靠性测试结构中,所述衬底中形成有一个有源区,所述有源区的两端上各形成有一个导电插塞。Optionally, in the reliability test structure, an active region is formed in the substrate, and a conductive plug is formed at both ends of the active region.

可选的,在所述可靠性测试结构中,所述衬底中形成有多个有源区,每个所述有源区的两端上各形成有一个导电插塞,相邻的两个有源区上的四个导电插塞中,位于不同有源区上的两个导电插塞连接于同一导电层上。Optionally, in the reliability test structure, a plurality of active regions are formed in the substrate, and a conductive plug is formed at both ends of each active region, and two adjacent Among the four conductive plugs on the active area, two conductive plugs located on different active areas are connected to the same conductive layer.

可选的,在所述可靠性测试结构中,多个所述有源区以迂回的方式排列成一蛇形结构。Optionally, in the reliability test structure, a plurality of the active regions are arranged in a meandering manner to form a serpentine structure.

可选的,在所述可靠性测试结构中,所述蛇形结构具有多个不同的迂回间距。Optionally, in the reliability testing structure, the serpentine structure has multiple different detour pitches.

可选的,在所述可靠性测试结构中,所述迂回间距为根据最小设计尺寸成倍增长。Optionally, in the reliability test structure, the detour distance is multiplied according to the minimum design size.

可选的,在所述可靠性测试结构中,多个所述有源区排列成L形、U形、M型或W形。Optionally, in the reliability test structure, a plurality of the active regions are arranged in an L-shape, U-shape, M-shape or W-shape.

可选的,在所述可靠性测试结构中,所述有源区的形状为条形。Optionally, in the reliability test structure, the shape of the active region is a stripe.

可选的,在所述可靠性测试结构中,所述有源区的宽度大于等于最小设计尺寸。Optionally, in the reliability test structure, the width of the active region is greater than or equal to the minimum design dimension.

可选的,在所述可靠性测试结构中,所述导电插塞与所述隔离结构的间距大于等于最小设计尺寸。Optionally, in the reliability test structure, the distance between the conductive plug and the isolation structure is greater than or equal to a minimum design dimension.

与现有技术相比,本实用新型提供的可靠性测试结构中,所述有源区、导电插塞及导电层形成串联的链状结构,当对该可靠性测试结构进行电阻测试时,于所述链状结构的首末两端施加电压或电流,然后根据检测出的对应的电流值或电压值,即可获得该链状结构的电阻值,根据检测出的电阻值的大小,可判断出所述有源区与导电插塞的连接状况,从而可进一步推断于所述有源区上是否残留有阻挡层。因此,使用本实用新型提供的可靠性测试结构,可对阻挡层的形成过程进行异常监控。Compared with the prior art, in the reliability test structure provided by the utility model, the active region, the conductive plug and the conductive layer form a chain structure connected in series, and when the resistance test is performed on the reliability test structure, the A voltage or current is applied to the first and last ends of the chain structure, and then the resistance value of the chain structure can be obtained according to the detected corresponding current value or voltage value, and it can be judged according to the detected resistance value The connection status between the active area and the conductive plug can be obtained, so that it can be further inferred whether there is a barrier layer left on the active area. Therefore, by using the reliability test structure provided by the utility model, the abnormality monitoring of the formation process of the barrier layer can be carried out.

附图说明Description of drawings

图1A为本实用新型实施例一的可靠性测试结构的俯视图;Fig. 1A is a top view of the reliability testing structure of Embodiment 1 of the present utility model;

图1B为本实用新型实施例一的可靠性测试结构的剖面图;Fig. 1B is a cross-sectional view of the reliability testing structure of Embodiment 1 of the present utility model;

图2A为本实用新型实施例二的可靠性测试结构的俯视图;Fig. 2A is a top view of the reliability testing structure of the second embodiment of the utility model;

图2B为本实用新型实施例二的可靠性测试结构沿AA’方向的剖面图;Fig. 2B is a sectional view of the reliability testing structure of the utility model embodiment 2 along the direction AA';

图3A至图3C为形成本实用新型实施例一的可靠性测试结构过程中的剖面结构示意图。3A to 3C are schematic cross-sectional structural diagrams during the process of forming the reliability testing structure of Embodiment 1 of the present invention.

具体实施方式detailed description

如背景技术所述,在光刻工艺过程中,常常由于光刻胶残留而影响所形成的器件的性能,同时,随着器件尺寸的不断缩小,传统的缺陷检测方法也越来越无法满足需求。为此,本实用新型提供一种可靠性测试结构,以解决缺陷的检出率不灵敏的问题,进一步的,也可用于光刻工艺过程中的异常监控。As mentioned in the background art, during the photolithography process, the performance of the formed device is often affected by the residual photoresist. At the same time, as the size of the device continues to shrink, the traditional defect detection method is increasingly unable to meet the demand. . For this reason, the utility model provides a reliability testing structure to solve the problem of insensitive defect detection rate, and further, it can also be used for abnormal monitoring in the photolithography process.

本实用新型提供的一种可靠性测试结构,用于检测阻挡层形成过程中的光刻胶残留情况,包括:衬底、阻挡层、至少两个导电插塞以及导电层,所述衬底中形成有至少一个有源区和位于每个所述有源区周边的隔离结构,所述阻挡层形成于所述隔离结构上,每个所述有源区的两端各形成有至少一个所述导电插塞,所述导电层形成于所述导电插塞的上方,位于同一有源区两端上导电插塞分别与两个不同的导电层连接,以使所述有源区、导电插塞及导电层形成串联的结构。A reliability testing structure provided by the utility model is used to detect photoresist residues in the formation process of the barrier layer, including: a substrate, a barrier layer, at least two conductive plugs and a conductive layer. At least one active region and an isolation structure located around each active region are formed, the barrier layer is formed on the isolation structure, and at least one of the active regions is formed on both ends of each active region. Conductive plugs, the conductive layer is formed above the conductive plugs, and the conductive plugs located at both ends of the same active region are respectively connected to two different conductive layers, so that the active region, the conductive plugs And the conductive layer forms a series structure.

本实用新型提供的可靠性测试结构中,所述有源区、导电插塞及导电层为串联的结构,当对该可靠性测试结构进行电阻测试时,于所述串联的结构的首末两端施加电压或电流,然后根据检测出的对应的电流值或电压值,即可获得该串联的结构的电阻值,依所到的电阻值进而可判断所述有源区与导电插塞的连接状况,从而可判断于所述有源区上是否残留有阻挡层,进而可推断出于光刻工艺过程中,是否存在有光刻胶残留的问题。即,使用本实用新型提供的可靠性测试结构,可以对阻挡层的形成过程进行异常监控。In the reliability test structure provided by the utility model, the active region, the conductive plug and the conductive layer are connected in series, and when the resistance test is performed on the reliability test structure, the Apply a voltage or current to the end, and then according to the detected corresponding current value or voltage value, the resistance value of the series structure can be obtained, and then the connection between the active region and the conductive plug can be judged according to the obtained resistance value Therefore, it can be judged whether there is a barrier layer left on the active region, and then it can be deduced whether there is a problem of photoresist residue during the photolithography process. That is, by using the reliability test structure provided by the present invention, the abnormality monitoring of the formation process of the barrier layer can be carried out.

在使用本实用新型提供的可靠性测试结构进行检测时,可根据实际可靠性测试结构的尺寸和具体工艺设置一规格电阻,然后将检测出的电阻值与规格电阻进行比对,若检测出的电阻值小于所述规格电阻,则该串联结构中的导电插塞与有源区之间的接触无异常,于有源区上没有残留有阻挡层;若检测出的电阻值大于所述规格电阻,则该串联结构中存在至少一个导电插塞与有源区的连接异常的问题,从而导致电阻增大。When using the reliability test structure provided by the utility model to detect, a standard resistance can be set according to the size and specific process of the actual reliability test structure, and then the detected resistance value is compared with the standard resistance, if the detected If the resistance value is less than the specified resistance, the contact between the conductive plug and the active area in the series structure is normal, and there is no barrier layer left on the active area; if the detected resistance value is greater than the specified resistance , then there is a problem of abnormal connection between at least one conductive plug and the active region in the series structure, which leads to an increase in resistance.

以下结合附图和具体实施例对本实用新型提出的可靠性测试结构作进一步详细说明。根据下面说明和权利要求书,本实用新型的优点和特征将更清楚。需说明的是,附图均采用非常简化的形式且均使用非精准的比例,仅用以方便、明晰地辅助说明本实用新型实施例的目的。The reliability test structure proposed by the utility model will be described in further detail below in conjunction with the accompanying drawings and specific embodiments. According to the following description and claims, the advantages and features of the utility model will be more clear. It should be noted that all the drawings are in very simplified form and use inaccurate scales, which are only used to facilitate and clearly illustrate the purpose of the embodiment of the present utility model.

实施例一Embodiment one

图1A为本实用新型实施例一的可靠性测试结构的俯视图,图1B为图1A所示的本实用新型实施例一的可靠性测试结构的剖面图。如图1A及图1B所示,本实施例提供的可靠性测试结构包括:衬底、阻挡层120、至少两个导电插塞130以及导电层140,所述衬底中形成有一个有源区111和位于所述有源区111周边的隔离结构112,所述阻挡层120形成于所述隔离结构112上,所述有源区111的两端各形成有一个所述导电插塞130,所述导电层140形成于所述导电插塞130的上方,所述有源区111中的两个导电插塞130分别与两个不同的导电层140连接,使所述有源区111、导电插塞130及导电层140形成串联的结构。FIG. 1A is a top view of the reliability testing structure of the first embodiment of the utility model, and FIG. 1B is a cross-sectional view of the reliability testing structure of the first embodiment of the utility model shown in FIG. 1A . As shown in Figure 1A and Figure 1B, the reliability test structure provided by this embodiment includes: a substrate, a barrier layer 120, at least two conductive plugs 130 and a conductive layer 140, an active region is formed in the substrate 111 and an isolation structure 112 located around the active region 111, the barrier layer 120 is formed on the isolation structure 112, and one conductive plug 130 is formed at both ends of the active region 111, so The conductive layer 140 is formed above the conductive plugs 130, and the two conductive plugs 130 in the active region 111 are respectively connected to two different conductive layers 140, so that the active region 111, the conductive plugs The plug 130 and the conductive layer 140 form a series structure.

本实施例中,所述有源区111和位于有源区111两端的两个导电插塞130以及分别与两个导电插塞130连接的两个导电层140共同形成一串联的结构,于所述两个导电层140上施加电压或电流以进行测试。然后即可根据测试结果判断所述有源区111与导电插塞130的连接状况,进而可推断出所述阻挡层120于形成过程中的光刻胶残留的情况。In this embodiment, the active region 111, the two conductive plugs 130 located at both ends of the active region 111, and the two conductive layers 140 respectively connected to the two conductive plugs 130 jointly form a series structure. A voltage or current is applied to the two conductive layers 140 for testing. Then, the connection status between the active region 111 and the conductive plug 130 can be judged according to the test results, and then the remaining photoresist during the formation process of the barrier layer 120 can be deduced.

本实施例中,所述衬底中形成有一个有源区111,其中,所述有源区111的形状为条形,其横截面可以为矩形。所述隔离结构112环绕所述有源区111,其横截面为矩形环状。所述有源区111的宽度D大于等于最小设计尺寸,所述导电插塞130与所述隔离结构112的最小间距S大于等于最小设计尺寸。由于当所述有源区111的宽度D及所述导电插塞130与隔离结构112的间距S越小时,则对后续形成阻挡层120的工艺要求就越高,因此,若所述可靠性测试结构的设计尺寸均采用最小设计尺寸,则可使得在制程能力要求的范围内,提高对形成阻挡层的异常监控的灵敏度。从而在形成阻挡层时,即使工艺过程中出现微小的偏差,也可体现于所述可靠性测试结构中,并可通过电阻测试检测出异常,进而可及时发现问题,避免异常扩大化。In this embodiment, an active region 111 is formed in the substrate, wherein the shape of the active region 111 is a strip, and its cross section may be a rectangle. The isolation structure 112 surrounds the active region 111 and has a rectangular ring shape in cross section. The width D of the active region 111 is greater than or equal to the minimum design dimension, and the minimum distance S between the conductive plug 130 and the isolation structure 112 is greater than or equal to the minimum design dimension. Since the smaller the width D of the active region 111 and the smaller the distance S between the conductive plug 130 and the isolation structure 112, the higher the process requirements for the subsequent formation of the barrier layer 120 are, therefore, if the reliability test The design dimensions of the structures all adopt the minimum design dimensions, which can improve the sensitivity of monitoring the abnormality of the formation of the barrier layer within the range required by the process capability. Therefore, when forming the barrier layer, even if there is a slight deviation in the process, it can be reflected in the reliability test structure, and the abnormality can be detected through the resistance test, so that the problem can be found in time and the expansion of the abnormality can be avoided.

其中,所述阻挡层120的材质例如为二氧化硅或氮化硅,所述插塞130的材质例如为钨(W),所述导电层140的材质例如铜(Cu)或铝(Al)。Wherein, the material of the barrier layer 120 is, for example, silicon dioxide or silicon nitride, the material of the plug 130 is, for example, tungsten (W), and the material of the conductive layer 140 is, for example, copper (Cu) or aluminum (Al). .

以下结合图3A至图3C对本实施例提供的可靠性测试结构的形成方法进一步详细说明。图3A至图3C为形成本实用新型实施例一的可靠性测试结构的步骤示意图,其中,图3A至图3C均为沿垂直于图1A中有源区的长度方向的剖面示意图。The method for forming the reliability test structure provided by this embodiment will be further described in detail below with reference to FIG. 3A to FIG. 3C . 3A to 3C are schematic diagrams of the steps of forming the reliability test structure of Embodiment 1 of the present invention, wherein, FIG. 3A to FIG. 3C are schematic cross-sectional views along the direction perpendicular to the length of the active region in FIG. 1A .

首先,参考图3A所示,提供一衬底,所述衬底中形成有源区111以及隔离结构112,所述隔离结构112的表面为需形成有阻挡层的区域。First, as shown in FIG. 3A , a substrate is provided, in which an active region 111 and an isolation structure 112 are formed, and the surface of the isolation structure 112 is a region where a barrier layer needs to be formed.

接着,参考图3B所示,于所述衬底上沉积阻挡层120,并于所述阻挡层120上旋涂光刻胶300。其中,所述阻挡层120例如为金属硅化物阻挡层。于半导体制造过程中,金属硅化物的形成是通过金属可与硅发生反应的这一特性而实现的。而通常于不需形成金属硅化物的区域,均覆盖有一金属硅化物阻挡层,以防止于不需形成金属硅化物的区域形成金属硅化物。在形成所述金属硅化物阻挡层的光刻工艺过程中,所需使用的光刻胶的厚度较厚,例如大于 Next, as shown in FIG. 3B , a blocking layer 120 is deposited on the substrate, and a photoresist 300 is spin-coated on the blocking layer 120 . Wherein, the barrier layer 120 is, for example, a metal silicide barrier layer. During semiconductor manufacturing, the formation of metal silicides is achieved through the property of metals to react with silicon. Usually, a metal silicide blocking layer is covered in the area where the metal silicide is not required to be formed, so as to prevent the metal silicide from forming in the area where the metal silicide is not to be formed. During the photolithography process for forming the metal silicide barrier layer, the thickness of the photoresist required to be used is relatively thick, for example greater than

然后,执行光刻及蚀刻工艺。由于光刻胶300的厚度较厚,并且所述有源区111的宽度较小。因此,执行光刻工艺时,需严格控制光刻工艺的条件,否则,当光刻工艺中出现微小的偏差,都可能导致位于有源区111上的光刻胶300无法完全去除的问题,如图3C所示,由于光刻胶残留,进而导致位于有源区111上的阻挡层120于蚀刻工艺后也无法完全去除。Then, photolithography and etching processes are performed. Since the thickness of the photoresist 300 is relatively thick, and the width of the active region 111 is relatively small. Therefore, when performing the photolithography process, it is necessary to strictly control the conditions of the photolithography process, otherwise, when a slight deviation occurs in the photolithography process, it may cause the problem that the photoresist 300 on the active region 111 cannot be completely removed, such as As shown in FIG. 3C , due to the remaining photoresist, the barrier layer 120 on the active region 111 cannot be completely removed after the etching process.

最后,于所述有源区111上依次形成导电插塞130以及导电层140。当在形成阻挡层的过程中出现异常而导致光刻胶残留,并进一步导致位于有源区上的金属硅化物阻挡无法完全去除时,则势必导致于后续所形成的导电插塞,与有源区电连接出现异常,例如连接的面积过小或者无法与有源区连接。Finally, a conductive plug 130 and a conductive layer 140 are sequentially formed on the active region 111 . When there is an abnormality in the process of forming the barrier layer, resulting in photoresist residue, and further causing the metal silicide barrier on the active region to not be completely removed, it will inevitably lead to the subsequent formation of conductive plugs, and active plugs. There is an abnormality in the electrical connection of the area, such as the area of the connection is too small or it cannot be connected to the active area.

可见,当对以上所形成的可靠性测试结构进行测试时,根据测试的结果即可判断所述有源区与导电插塞的连接状况,进而可推断于形成阻挡层的过程中是否存在异常。It can be seen that when the reliability test structure formed above is tested, the connection status between the active region and the conductive plug can be judged according to the test result, and then it can be deduced whether there is any abnormality in the process of forming the barrier layer.

实施例二Embodiment two

图2A为本实用新型实施例二的可靠性测试结构的示意图,图2B为本实用新型实施例二的可靠性测试结构沿AA’方向的剖面图。如图2A和图2B所示,本实施例中,所述可靠性测试结构包括:衬底、阻挡层220、导电插塞230、导电层240,所述衬底中形成有多个有源区211以及隔离结构212,所述阻挡层220形成于隔离结构212上,每个有源区211的两端各形成有一个所述导电插塞230,所述导电层140形成于所述导电插塞230的上方。本实施例中,相邻的两个有源区211上的四个导电插塞230中,其中位于不同有源区211上的两个导电插塞230连接于同一导电层240上,使所述有源区211、导电插塞230及导电层240形成串联的链状结构。Fig. 2A is a schematic diagram of the reliability testing structure of the second embodiment of the utility model, and Fig. 2B is a cross-sectional view of the reliability testing structure of the second embodiment of the utility model along the direction AA'. As shown in FIG. 2A and FIG. 2B, in this embodiment, the reliability test structure includes: a substrate, a barrier layer 220, a conductive plug 230, and a conductive layer 240, and a plurality of active regions are formed in the substrate. 211 and an isolation structure 212, the barrier layer 220 is formed on the isolation structure 212, a conductive plug 230 is formed at both ends of each active region 211, and the conductive layer 140 is formed on the conductive plug 230 above. In this embodiment, among the four conductive plugs 230 on two adjacent active regions 211, the two conductive plugs 230 on different active regions 211 are connected to the same conductive layer 240, so that the The active region 211 , the conductive plug 230 and the conductive layer 240 form a chain structure connected in series.

本实施例中,所述有源区、导电插塞及导电层为串联的链状结构,当对所述可靠性测试结构进行电阻测试时,于所述链状结构的首末两端施加电压或电流,然后根据检测出的对应的电流值或电压值,即可获得该串联的结构的电阻值,依所到的电阻值进而可判断于所述链状结构中的所述有源区与导电插塞的连接状况,从而可判断于所述有源区上是否残留有阻挡层。即使用本实用新型提供的可靠性测试结构,可以对阻挡层的形成过程进行异常监控。In this embodiment, the active region, the conductive plug and the conductive layer are a chain structure connected in series, and when the resistance test is performed on the reliability test structure, a voltage is applied to the first and last ends of the chain structure or current, and then according to the detected corresponding current value or voltage value, the resistance value of the series-connected structure can be obtained, and the active region in the chain structure can be judged according to the obtained resistance value. The connection status of the conductive plugs can be used to judge whether there is a barrier layer left on the active area. That is, by using the reliability test structure provided by the utility model, the abnormality monitoring of the formation process of the barrier layer can be carried out.

所述有源区211可以以任意形状进行排列以形成一线性结构,例如以L型、U形、M型或W形的线性方式进行排列或以迂回的方式排列成一蛇形结构。本实施例中,每个有源区211均为条状结构,多个所述有源区以迂回的方式排列成一蛇形结构。具体的,所述有源区211以不同的迂回间距进行排列,即所述蛇形结构具有多个不同的迂回间距。较佳的,所述迂回间距可根据最小设计尺寸成倍增长,如图2A所示,本实施例中,所述有源区211以5个不同的迂回间距进行排列,所述迂回间距分别等于:最小设计尺寸W1,2倍的最小设计尺寸W2,3倍的最小设计尺寸W3,4倍的最小设计尺寸W4,及5倍的最小设计尺寸W5。The active regions 211 can be arranged in any shape to form a linear structure, for example arranged in an L-shape, U-shape, M-shape or W-shape linearly or in a meandering way to form a serpentine structure. In this embodiment, each active region 211 is a strip structure, and multiple active regions are arranged in a meandering manner to form a serpentine structure. Specifically, the active regions 211 are arranged with different serpentine pitches, that is, the serpentine structure has multiple different serpentine pitches. Preferably, the detour pitch can be multiplied according to the minimum design size. As shown in FIG. 2A , in this embodiment, the active regions 211 are arranged with 5 different detour pitches, and the detour pitches are respectively equal to : Minimum design size W1, 2 times the minimum design size W2, 3 times the minimum design size W3, 4 times the minimum design size W4, and 5 times the minimum design size W5.

本实施例的可靠性测试结构中,所述有源区211采用不同的迂回间距排列,形成了密集度不同的排列方式,即后续所形成的阻挡层的宽度也不同。由于在光刻工艺过程中,对密集区域及疏散区域进行曝光时的聚焦深度不同,造成曝光精确度不同,因此在后续形成阻挡层的光刻工艺中,密集区域及疏散区域所形成的阻挡层的解析度不同,从而可找出在当前的曝光条件下,所述阻挡层的宽度的光刻工艺窗口。In the reliability test structure of the present embodiment, the active regions 211 are arranged with different detour pitches to form arrangements with different densities, that is, the widths of barrier layers formed subsequently are also different. During the photolithography process, the depth of focus is different when exposing dense areas and sparse areas, resulting in different exposure accuracy. Therefore, in the subsequent photolithography process for forming barrier layers, the barrier layers formed by dense areas and sparse areas The resolutions are different, so that under the current exposure conditions, the photolithography process window of the width of the barrier layer can be found.

上述描述仅是对本实用新型较佳实施例的描述,并非对本实用新型范围的任何限定,本实用新型领域的普通技术人员根据上述揭示内容做的任何变更、修饰,均属于权利要求书的保护范围。The above description is only a description of the preferred embodiments of the present utility model, and is not any limitation to the scope of the present utility model. Any changes and modifications made by those of ordinary skill in the field of the utility model according to the above disclosures all belong to the protection scope of the claims .

Claims (10)

1. a reliability testing structure, for monitoring the photoresist residual in the forming process of barrier layer Situation, it is characterised in that including: substrate, barrier layer, conductive layer and at least two conductive plunger, Described substrate is formed at least one active area and is positioned at the isolation junction of each described active area periphery Structure, described barrier layer is formed on described isolation structure, and the two ends of each described active area are respectively formed At least one described conductive plunger, described conductive layer is formed at the top of described conductive plunger, is positioned at same The conductive layer that on one active area two ends, conductive plunger is different from two respectively connects, so that described active area, Conductive plunger and conductive layer form the structure of series connection.
2. reliability testing structure as claimed in claim 1, it is characterised in that: shape in described substrate Cheng Youyi active area, the two ends of described active area are respectively formed a conductive plunger.
3. reliability testing structure as claimed in claim 1, it is characterised in that: shape in described substrate Become to have multiple active area, the two ends of each described active area are respectively formed a conductive plunger, adjacent Two active areas on four conductive plungers in, two conductive plungers being positioned on different active area are even It is connected on same conductive layer.
4. reliability testing structure as claimed in claim 3, it is characterised in that: multiple described active District is arranged in a serpentine configuration in the way of roundabout.
5. reliability testing structure as claimed in claim 4, it is characterised in that: described serpentine configuration There is multiple different roundabout spacing.
6. reliability testing structure as claimed in claim 5, it is characterised in that: described roundabout spacing For being doubled and redoubled according to minimum design dimension.
7. reliability testing structure as claimed in claim 3, it is characterised in that: multiple described active District arranges L-shaped, U-shaped, M type or W shape.
8. reliability testing structure as claimed in claim 1, it is characterised in that: described active area It is shaped as bar shaped.
9. reliability testing structure as claimed in claim 8, it is characterised in that: described active area Width is more than or equal to minimum design dimension.
10. reliability testing structure as claimed in claim 1, it is characterised in that: described conduction is inserted Plug is more than or equal to minimum design dimension with the spacing of described isolation structure.
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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113745124A (en) * 2020-05-28 2021-12-03 中芯国际集成电路制造(上海)有限公司 Test structure and test method
WO2022048249A1 (en) * 2020-09-04 2022-03-10 长鑫存储技术有限公司 Semiconductor structure
US11961774B2 (en) 2020-09-04 2024-04-16 Changxin Memory Technologies, Inc. Semiconductor device and method for manufacturing same
US12218016B2 (en) 2020-09-04 2025-02-04 Changxin Memory Technologies, Inc. Semiconductor structure

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113745124A (en) * 2020-05-28 2021-12-03 中芯国际集成电路制造(上海)有限公司 Test structure and test method
WO2022048249A1 (en) * 2020-09-04 2022-03-10 长鑫存储技术有限公司 Semiconductor structure
US11961774B2 (en) 2020-09-04 2024-04-16 Changxin Memory Technologies, Inc. Semiconductor device and method for manufacturing same
US12218016B2 (en) 2020-09-04 2025-02-04 Changxin Memory Technologies, Inc. Semiconductor structure

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