CN1534560A - Data driving circuit and method for driving data by the same - Google Patents

Abstract

The invention provides a data driving circuit and a method for driving data by the same, the data driving circuit comprises an input module, a plurality of latches, a plurality of shift registers and a digital-to-analog converter, the method comprises the steps of using the input module to receive N-bit digital data, dividing the N-bit digital data into m groups of bit data, using the shift registers to output a plurality of switching signals in sequence to input the m groups of bit data to the latches in sequence, then inputting the latched m groups of bit data to the digital-to-analog converter in sequence according to the sequence of the switching signals, finally using the digital-to-analog converter to convert the digital data into the analog voltage signal, and outputting the analog voltage signal to a data line.

Description

Data-driven circuit and method for driving data therefrom

technical field

The present invention provides a data driver circuit (Data Driver) and a method for driving data therefrom, in particular to a digital data driver circuit and at least one data line of a display driven by it, so as to save space and save data. The method of carrying out the pre-charging (Pre-Charging) function of the line.

Background technique

Liquid crystal display (liquid crystal display, LCD) and related display devices are thin and small display devices, and can be seen in many electrical products, and the distribution range is also very wide, from the fields of notebook computers and digital cameras, to even It is used in the fields of aerospace and medical diagnostic instruments. Among them, the thin film transistor liquid crystal display (TFT LCD) can provide flat, detailed, high-resolution images while maintaining good color contrast and screen scanning refresh rate, and operate under low power; and in recent years, the industry The Low Temperature Poly Silicon LCD (LTPS LCD) developed by the industry can directly manufacture the driving circuit on the glass substrate. In addition to effectively reducing the number of panel driving chips and reducing the cost of materials and packaging, it can also increase Product reliability and miniaturization.

Liquid crystal display systems are generally divided into digital interface and analog interface according to the type of input data. The general standard specifications of the two are different. In order to save power, facilitate system integration and save costs, more and more LCD The display system adopts the method of inputting data in digital form, so a digital-to-analog converter (Digital-to-Analog Converter) needs to be integrated into the data driving circuit, and in order to cooperate with the conversion of digital to analog data, a latch circuit is usually required (Latch) or sample and hold (Sample/Hold) circuit is also integrated into the data driving circuit, and placed before the digital/analog converter, please refer to FIG. 1, FIG. 1 is a functional block diagram of the data driving circuit 10 in the prior art, Figure 1 shows a data drive circuit 10 corresponding to the three primary colors (R, G, B) of a pixel (Pixel) 11 on the display, which includes an input module 12, two-stage latches 14, 16 (the first stage latch latch 14 and second-stage latch 16), a shift register (Shift Register) 18, and three digital-to-analog converters (DAC) 20r, 20b, 20g. The input module 12 includes three groups of N-bit circuit lines 12r, 12b, 12g, each group of N-bit circuit lines is used to receive a digital data with N-bit, and each group of N-bit digital data corresponds to One of the three primary colors (R, G, B) of a pixel 11 (Pixel) on the display (corresponding to a group of N-bit digital data of red (R) in the three primary colors of a pixel 11 on the display is DR0 ~ DR5, corresponding to A group of N-bit digital data of blue (B) among the three primary colors of one pixel 11 on the display is DB0-DB5, and a group of N-bit digital data corresponding to one group of N-bit green (G) of the three primary colors of one pixel 11 on the display is DG0˜DG5), wherein N is an integer greater than or equal to 2, and as shown in FIG. 1 , the value of N is 6, that is, each group of digital data is digital data of six bits. The two-stage latches 14 and 16 (Latch), electrically connected to the input module 12, have the functions of Level Shift and Buffering, and each stage of latches also includes three latches, Respectively correspond to the three primary colors of a pixel 11 (Pixel) on the display (the first stage latch 14 includes three latches 14r, 14b, 14g, and the second stage latch 16 includes three latches 16r, 16b, 16g ), each latch can latch N-bit digital data, so each latch must be an N-bit latch; and the shift register 18 can output a switch signal SR, once corresponding to The three sets of N-bit digital data of the three primary colors of a pixel 11 (Pixel) on the display are all sent to the first-stage latch, so that the first-stage latch 14 performs the functions of boosting and buffering, and then transmits the data to the second The first-stage latch 16 allows the second-stage latch 16 to continue to perform the functions of boosting and buffering. The digital-to-analog converters 20r, 20b, and 20g are connected behind the second-stage latch 16, and are used to receive the digital data output by the second-stage latch 16, convert the digital data into an analog voltage signal, and output the analog voltage signal respectively. Voltage signals to the data lines 22r, 22b, 22g, according to the strength of the analog voltage signal to control the color of the panel, between the first-stage latch 14 and the second-stage latch 16 of the data drive circuit 10, usually set Another switch LP transmits all the digital data originally latched in the first-stage latch 14 to the second-stage latch 16 in sequence, so as to control the time of data flow and allow the data to enter the digital-to-analog converters 20r, 20b, 20g charging time is more abundant. The basic structure of the above prior art has been described in many patents and documents related to digital data driving circuit design. Yojiro Matsueda et al published in SID 96Digest, "Low Temperature poly-Si TFT-LCD with integrated 6-bit Digital DataDriver" in 1996 that the data drive circuit was made on glass with LTPS technology, and a digital six-bit Yuan's data-driven circuit architecture. In order to cooperate with the data conversion, they proposed to integrate the latch circuit into the data-driven circuit and place it in the aforementioned architecture of the digital-to-analog converter. Then, Yojiro Matsueda et al. continued to summarize their "Concept of a System on Panel" in IDW'00 p.p.171-174, in which they analyzed the digital and analog data-driven circuit architecture, and further integrated the external memory into the system In this process, the idea of SOP (System on Panel) is more complete. Next, in US Patent 5,856,816, "Data driver for liquid crystal display", Youn et al. avoided using an external memory, and instead used a multi-bit register (Register) in the data drive circuit architecture to divide the drive frequency into Lower frequency to reduce the problems caused by high-frequency operation. Although the above-mentioned patents of the prior art are digital data drive circuits with the present invention, there are great differences in structure, technical features and the purpose of improvement. , and with the two documents of the above-mentioned prior art, all are listed as the prior art of the present invention.

It can be known from the above prior art that in order to latch N-bit digital data, in the digital data driving circuit, each latch must be an N-bit latch. Today, as users demand more and more picture quality, the fineness of the colors displayed by the display system is also becoming more and more important. For example, if a general panel can display 4096 colors, the digital data must be input in four bits. That is, at this time, the data driving circuit must also have a four-bit digital-to-analog converter and a four-bit latch circuit or a sample-and-hold circuit. The driving circuit must also have a six-bit digital-to-analog converter and a six-bit latch circuit or sample-and-hold circuit. However, when the resolution of the panel is increased, the size of each pixel is relatively reduced, thus limiting the space of the driving circuit. Therefore, if this digital interface method is to be used, the difficulty will be greatly increased. There are generally two ways to solve this problem. One method is not to make the data drive circuit on the glass with low-temperature polysilicon (LTPS) technology, but to use a method similar to an amorphous silicon liquid crystal display (a-Si LCD) to paste the driver chipset on the glass ( COG), the biggest advantage of this technology is to avoid the problems caused by the connection of components through "wires" or "pins". However, the test of stability such as thermal and thermal shocks needs to be strengthened. The application value of small and medium size panels. In 2000, T.Morita et al. (Toshiba Corp.) proposed a selection circuit (Selecting Circuit) makes the digital-to-analog converter and the latch circuit share the goal to reduce the space requirements of the data drive circuit. In this way, the number of digital-to-analog converters and latch circuits can be greatly reduced. However, in this design Next, the number of bits of data to be processed by each latch circuit at the same time must still be the same as the number of bits of each group of digital data, that is, if the digital data is four-bit input, the latch circuit must also be four-bit If the digital data is a six-bit input, the latch circuit must also be a six-bit latch circuit. Therefore, the circuit and space saving are still not perfect.

Contents of the invention

Therefore, the main purpose of the present invention is to use a digital data driver circuit (DataDriver) to cooperate with a method for time-division transmission of digital data packets to drive at least one data line of a display, so as to save space and save space on the data line. A precharge function is performed to solve the above problems.

The present invention provides a method for driving data with a data driver circuit (Data Driver), the data driver circuit is used to drive a data line of a display, the data driver circuit includes an input module, which includes N-bit circuit lines, Used to receive a digital data with N bits, the digital data of N bits has m sets of bit data, where N and m are integers greater than or equal to 2, and a plurality of latches (Latch), electrically connected to In the input module, each latch is used to latch a group of bit data in the digital data, and a plurality of shift registers (shift registers) are used to sequentially output a plurality of switching signals to control the m groups of bits The sequence of data transmission to the plurality of latches, and a digital to analog converter (DAC) connected to the plurality of latches for receiving digital data output by the plurality of latches , converting the digital data into an analog voltage signal, and outputting the analog voltage signal to the data line, and the method includes receiving the digital data by the N-bit circuit line of the input module, using the plurality of shift registers Sequentially output a plurality of switch signals to sequentially input the m groups of bit data to the plurality of latches for latching, and according to the order of the switch signals output by the shift register, the m groups of bits to be latched Data is sequentially input to the digital-to-analog converter so that the digital-to-analog converter receives the digital data, and uses the digital-to-analog converter to convert the digital data into the analog voltage signal, and outputs the analog voltage signal to the data line, wherein according to the order of the switching signals of the shift register, the digital data first input to the corresponding digital-to-analog converter among the m sets of byte data will perform the pre-charging function on the data line .

The present invention provides a data driver circuit (Data Driver), which is used to drive at least one data line of a display, and the data driver circuit includes N groups of bit circuit lines, respectively corresponding to one N-bit (N-bits) Each bit of digital data is used to receive the digital data, and divide the N-bit digital data into m groups of bit data, wherein N and m are integers greater than or equal to 2, and m shift registers (shift register), used to sequentially output m switch signals, used to control the sequence of the m group of bit data transmission, a plurality of latches (Latch), electrically connected to the N group of bit circuit lines, used to latch The digital data transmitted by the N groups of bit circuit lines, and at least one digital-to-analog converter (DAC), are used to receive the digital signal output by the latch and convert the digital signal into an analog Voltage signal, and output the analog voltage signal to the data line, wherein when the N group of bit circuit lines respectively receive each bit in the N-bit digital data, and divide the N-bit digital data into m groups After the bit data, according to the order of the switching signals generated by the m shift registers, the m groups of bit data are sequentially input to the corresponding latches for latching, and the latched m groups of bit data The switching signals generated by the m shift registers are also sequentially input to the corresponding digital-to-analog converter, and the digital-to-analog converter is used to convert the digital signal into the analog voltage signal, and output the analog voltage signal to the data line.

The advantage of the present invention is that the method of the present invention divides the N-bit digital data into m groups, and according to the m adjacent pulse signals generated by m shift registers, the m adjacent pulse signals jump The m sets of bit data are sequentially input into the same set of latches in order of time, so that each latch only needs to include N/m latch circuits (Latch Circuit), instead of N latch circuits need to be included to process N-bit digital data, thereby greatly reducing the space occupied by the circuit and meeting the requirement of saving space.

The advantage of the present invention is that a set of bit data firstly input to the corresponding digital-to-analog converter can pre-charge the data line, so as to increase the service life and stability of the circuit.

Description of drawings

Fig. 1 is the functional block diagram of prior art data driving circuit;

Fig. 2 is a functional block diagram of an embodiment of the data driving circuit of the present invention;

FIG. 3 is a timing diagram of switch signals and six-bit digital data in FIG. 2; and

FIG. 4 is a functional block diagram of another embodiment of the data driving circuit of the present invention.

The reference signs in the accompanying drawings are explained as follows:

10, 30 data drive circuit 11, 41 pixels

12, 32 input module

14r, 14b, 14g First stage 6-bit (bit) latch

16r, 16b, 16g Second Stage 6-Position Latch

18 shift registers

20r, 20b, 20g, 40r, 40b, 40g 6-bit digital-to-analog converter

22r, 22b, 22g, 42r, 42b, 42g data cable

34r, 34b, 34g First stage 3-position latch

36r, 36b, 36g Second Stage 3-Position Latch

37r, 37b, 37g Third Stage 6-Position Latch

38 The first shift register 39 The second shift register

Detailed ways

The main concept of the present invention is to divide an N-bit digital data into m sets of bit data, and then use at least m shift registers (shift registers) to control the transfer of the m sets of bit data to the latch. order. Please refer to FIG. 2. FIG. 2 is a functional block diagram of an embodiment of the data driving circuit 30 of the present invention, which inherits the similar architecture of the prior art in FIG. Made some major changes. Shown in Fig. 2 is a data driving circuit 30 corresponding to the three primary colors (R, G, B) of a pixel (Pixel) on the display, which includes an input module 32, three-stage latches 34, 36, 37 (first Stage latch 34, second stage latch 36, and third stage latch 37), two shift registers (Shift Register) 38, 39 (first shift register 38 and second shift register 39) , and three digital-to-analog converters (DACs) 40r, 40b, 40g. The input module 32 includes three groups of N-bit circuit lines, each group of N-bit circuit lines is used to receive a digital data with N-bits, and each group of N-bit digital data corresponds to a pixel on the display ( Pixel) one of the three primary colors (R, G, B) (corresponding to a set of N-bit digital data of red (R) in the three primary colors of a pixel on the display is DR0~DR5, corresponding to the blue in the three primary colors of a pixel on the display A group of N-bit digital data of color (B) is DB0~DB5, and a group of N-bit digital data corresponding to green (G) among the three primary colors of a pixel on the display is DG0~DG5), where N is greater than or an integer equal to 2, and as shown in FIG. 1, the value of N is six, that is, in this embodiment, each set of digital data is preset to be six-bit digital data. The three-level latches are electrically connected to the input module 32 as shown in Figure 2, and have the same functions as the prior art (Level Shift) and buffering (Buffering), and each level of latches also includes three sets of latches , respectively corresponding to the three primary colors of a pixel (Pixel) on the display (the first stage latch 34 includes three groups of latches 34r, 34b, 34g, and the second stage latch 36 includes three groups of latches 36r, 36b, 36g , the third-stage latch 37 includes three sets of latches 37r, 37b, 37g), and two shift registers 38, 39 sequentially output two switching signals SR1, SR2 (the first switching signal SR1 and the second switching signal SR2 ), please refer to Figure 3. Figure 3 is a timing diagram of two switch signals SR1, SR2 and six-bit digital data. A set of N-bit digital data DR0-DR5 is an example of six-bit digital data output. From FIG. 2 and FIG. 3 , it can be seen that the first switching signal SR1 and the second switching signal SR2 are two adjacent pulse signals, and the jump time of the first switching signal SR1 is just earlier than that of the second switching signal SR2 . The digital-to-analog converters 40r, 40b, and 40g are connected after the second-stage latch 36 and the third-stage latch 37, and are used to receive the digital output from the second-stage latch 36 and the third-stage latch 37. Data, convert the digital data into an analog voltage signal, and output the analog voltage signal to the data lines 42r, 42b, 42g respectively, and control the fineness of the panel according to the strength of the analog voltage signal.

The above-mentioned embodiment in FIG. 2 is to realize the structure of the data driving circuit 30 corresponding to the method disclosed in the present invention, and the detailed operation is described as follows. In the embodiment of Fig. 2, the digital data of each group of six bits is divided into two groups of bit data, and one group of bit data is ordered as the most important byte group (MSB: DR5～DR3, DB5～DB3, DG5～ DG3, DR5~DR3 is used as an example in the timing diagram of Figure 3), and the other group of bit data is set as the least significant byte (LSB: DR2~DR0, DB2~DB0, DG2~DG0, the timing diagram of Figure 3 Take DR2～DR0 as an example), therefore, each group of bit data includes each three bits of six-bit digital data, and then utilize two shift registers 38, 39 to control the two groups of bit data Please note that in the embodiment of Figure 2, since each group of six-bit digital data is divided into two groups of bit data, it corresponds to the most important aspect of the present invention described in the previous paragraph. After the concept, that is, m=2, therefore, each latch only needs to latch (N/m=3) bits of digital data, that is, each latch only needs to be a three-bit latch The latch can also be described as that each latch includes three (N/m=3) latch circuits (Latch Circuit) to process three-bit digital data, instead of six (N) as in the prior art = 6) bit latch. Please continue to refer to Fig. 2 and Fig. 3, after these two groups of byte data (most significant byte group MSB, least significant byte group LSB) are received by the N bit circuit line of input module 32, after the first shift When the first switch signal SR1 output by the register 38 jumps, the most important byte group MSB (DR5-DR3 is taken as an example in the timing diagram of Figure 3) will be sampled and sent to the first-stage three-bit latch 34r, 34b, 34g, three-bit latches 36r, 36b, 36g of the second stage (both function of level shifting) and three-bit latches 37r, 37b, 37g of the third stage , and latched in this three-stage latch, and then enter the digital-to-analog converter 40r, 40b, 40g to determine the voltage value of the most significant byte group MSB, and then when the second shift register 39 outputs the first When the second switch signal SR2 jumps, the least significant byte LSB (DR2-DR0 is taken as an example in the timing diagram of Figure 3) will be sampled (sampled) and sent to the first-stage three-bit latch and the second In the second-level three-bit latch (with the function of buck-boost), and rewrite the most significant byte MSB latched in these two sets of latch circuits to the least significant byte LSB, so First, the MSB of the most significant byte is input to the digital-to-analog converters 40r, 40b, and 40g at a time when the switch signal jumps earlier than the LSB data of the least significant byte. Please note that at this time, the three-bit latch of the third stage The lock circuit still latches the most significant byte group MSB, after the most significant byte group MSB enters the digital-to-analog converter 40r, 40b, 40g in advance to determine the voltage value of the most significant byte group MSB, the least significant byte group The signal of group LSB also immediately enters the digital-to-analog converter 40r, 40b, 40g to determine the voltage value of the least significant byte group LSB, plus the voltage value determined by the previous most significant byte group MSB to determine the final conversion Finally, write the analog signal voltage into each data line 42r, 42b, 42g and into the pixel 41.

Several important technical features of the present invention can be summarized from the above-mentioned embodiment in FIG. The concept of dividing digital data into m sets of bit data (N and m are integers greater than or equal to 2), so the m sets of bit data must be time-divisionally transmitted to the latch for latching and buck-boosting, so it is necessary Cooperate with the m switching signals generated by the upper m shift registers to sequentially input m sets of bit data into the latch. In the embodiment of FIG. 2, the value of m is preset to two, and the digital data Be a six-bit digital data (N=6), but when actually implementing, the values of N and m need not be limited to the same as the embodiment of Fig. 2, and should be determined according to the appropriate needs of the industry, and the same, because m The m switching signals generated by the shift registers are to correspond to the concept of sequential transmission of m groups of byte data. The shift register only needs to be able to time-divisionally transmit the m groups of byte data to the latch. The number of bit registers does not have to be the same as the number of groups of bit data, and the switching signals output by the shift registers do not have to be adjacent pulse signals, and other types can be used.

Furthermore, the present embodiment includes a three-stage latch in consideration of avoiding the fact that the step-up and step-down range is too large to affect the stability of the system. If only from the technical features and design concept of the present invention, because The invention divides an N-bit digital data into m groups of bit data, and at least m-level latches are required to latch and step up and down when transmitting the m group of bit data to the latch for latching and boosting and boosting. Stepping down the m sets of bit data, that is to say, in the embodiment of FIG. 2, at least two latches are enough. It can be seen that the number of stages of latches does not need to be limited to that of FIG. 2 The embodiments are the same, as long as it is the same as or slightly larger than the number of groups of bit data, and it should be determined according to the appropriate needs of the industry. As for the number of bits of each latch in each stage of latches (that is, the number of latch circuits included in each latch), in the present invention, an N-bit digital data is divided into m groups of bits After the data, it can basically be reduced to (N/m). In the embodiment of FIG. 2, each latch is a three-bit latch, but in actual implementation, the bit of each latch As long as the number is an integer equal to (N/m) or an integer slightly larger than (N/m), it should be determined according to the appropriate needs of the industry. That is to say, in the embodiment of FIG. 2, each The latch also can be made as a latch of four or other bit numbers, but the bit number of each latch is made closer to the bit number (N) of the original digital data, and the present invention is lost in order to save The character and meaning of space.

Third, one of the important technical features of the present invention is that according to the sequence of the switching signals of the shift register, the digital data first input to the digital-to-analog converter in the m sets of bit data will precharge the data line, Let the voltage not increase too fast at one time and damage the life of the hardware. In the embodiment of FIG. 2, the most significant byte MSB will be pre-entered into the digital-to-analog converters 40r, 40b, 40g to determine the voltage value of the most significant byte MSB, and precharge the data lines 42r, 42b, 42g , then the signal of the least significant byte LSB also enters the digital-to-analog converter 40r, 40b, 40g to determine the voltage value of the least significant byte LSB, plus the voltage value determined by the previous most significant byte MSB to determine the final converted analog signal voltage. For example, if the digital-to-analog converters 40r, 40b, and 40g directly convert binary digital data into decimal analog voltage signals, and the six-bit digital data in the embodiment of FIG. 2 is divided into The two groups are expressed as (the most significant byte MSB, the least significant byte LSB) is (110, 100), that is, the most significant byte MSB is (110), and the least significant byte LSB is (100 ), when the most significant byte group MSB enters the digital-to-analog converter 40r, 40b, 40g in advance, the voltage value of the most significant byte group MSB 48 volts (1*2 ⁵ +1*2 ⁴ =48( V)) and pre-charged to the data lines 42r, 42b, 42g, and then the signal of the least significant byte LSB enters the digital-to-analog converters 40r, 40b, 40g to determine the final voltage value of 52 volts. Similarly, if the six-bit digital data is (011, 101), that is, the MSB of the most significant byte is (011), and the LSB of the least significant byte is (101), when the MSB of the most significant byte is entered in advance In the digital-to-analog converters 40r, 40b, and 40g, the voltage value of the MSB of the most significant byte is determined to be 24 volts (1*2 ⁴ +1*2 ³ =24 (V)), and then the least significant byte The LSB signal then enters the digital-to-analog converters 40r, 40b, 40g to determine the final voltage value of 29 volts. Please note that it also corresponds to the basic concept of the present invention, because m groups of byte data only need to be "time-divisionally transmitted" to the latch, and in the function of precharging, it is emphasized that "input to the digital-to-analog converter first The group of byte data 40r, 40b, 40g has the function of precharging the data lines 42r, 42b, 42g", therefore, in the actual implementation of the present invention, it is not necessary to set the most important byte group MSB first as shown in the embodiment shown in Figure 2 Inputting the digital-analog converters 40r, 40b, 40g can also realize the pre-charging function, that is to say, there is no need to limit the bit data of a specific group to be input into the digital-analog converters 40r, 40b, 40g first or then input into the digital-analog converters 40r, 40b, 40g, can be adjusted according to the actual needs during manufacturing. Please refer to Fig. 3, Fig. 4 is the schematic diagram after the most significant byte group MSB and the least significant byte group LSB input digital-to-analog converter 40r, 40b, 40g order are reversed in the embodiment of Fig. 2, the device shown in Fig. 4 The functions and marks are the same as those in Fig. 2. In Fig. 4, the first shift register 38 and the second shift register 39 still sequentially output the first switch signal SR1 and the second switch signal SR2, the first switch signal SR1 and the second shift register SR2 The second switching signal SR2 is two adjacent pulse signals, and the jumping time of the first switching signal SR1 is also earlier than the second switching signal SR2. The only difference is that the embodiment of FIG. 4 uses the first shift register 38 connected to control the least significant byte group LSB, the second shift register 39 is connected to control the most significant byte group MSB, so that the least significant byte group LSB is input to the digital-to-analog converter 40r, earlier than the most significant byte group MSB 40b, 40g therefore become the function of precharging the data lines 42r, 42b, 42g with the least significant byte LSB. For example, if the digital-to-analog converters 40r, 40b, 40g directly convert binary digital data Converted to a decimal analog voltage signal, and the six-bit digital data in the embodiment of Fig. 2 is divided into two groups and expressed as (the most significant byte group MSB, the least significant byte group LSB) is (110, 100), that is, the most The MSB of the significant byte is (110), and the LSB of the least significant byte is (100). When the LSB of the least significant byte enters the digital-to-analog converters 40r, 40b, and 40g in advance, the least significant byte will be determined first The voltage value of the byte LSB is 4 volts (1*2 ² =4 (V)) and is precharged to the data lines 42r, 42b, 42g, and then the signal of the most significant byte MSB enters the digital-to-analog converter 40r, 40b , 40g to determine the final voltage value of 52 volts. Similarly, if the six-bit digital data is (011, 101), that is, the MSB of the most significant byte is (011), and the LSB of the least significant byte is (101). Entering the digital-to-analog converters 40r, 40b, and 40g, the voltage value of the MSB of the most significant byte group is determined to be 5 volts (1*2 ² +1*2 ⁰ =5 (V)), and then the least significant bit The signals of group LSB enter the digital-to-analog converters 40r, 40b, and 40g to determine the final voltage value of 29 volts. Of course, in this way, the effect of precharging in the embodiment of FIG. 4 is not as obvious as in the embodiment of FIG. 2 .

After having stated several important technical characteristics of the present invention, finally emphasize again that the digital data drive circuit 30 of the present invention is used in a display, and in various displays, including liquid crystal display (LCD), low temperature polysilicon liquid crystal display (LTPS) LCD), Light Emitting Diode (LED), Organic Light Emitting Diode (OLED), or Organic Polymer Light Emitting Diode (PLED) are all included in the applicable scope of the present invention.

Compared with the prior art, the method of the present invention divides the N-bit digital data into m groups, and sequentially inputs the m groups of bit data into the latch according to the order of the pulse signals generated by the shift register. In this way, the number of latch circuits included in each latch becomes the value obtained by dividing the original number by m, which greatly reduces the complexity and space of the latch and meets the requirement of saving space. At the same time, Among the m groups of bit data, the first group of bit data input to the corresponding digital-to-analog converter can precharge the data line, increasing the service life and stability of the circuit.

The above descriptions are only preferred embodiments of the present invention, and all equivalent changes and modifications made according to the claims of the present invention shall fall within the scope of the patent of the present invention.

Claims (16)

1. method with a data drive circuit driving data, this data drive circuit is used for driving at least one data line of a display, and this data drive circuit includes:

One load module, it comprises N bit circuitry lines, is used for receiving one and has the numerical data of N bit, and the numerical data of this N bit has m group bit data, and wherein N and m are the integer more than or equal to 2;

A plurality of latch units are electrically connected on this load module, and each latch unit is used for latching one group of bit data in this numerical data; And

A plurality of shift registers are used for exporting in proper order a plurality of switching signals, to control the order that these m group bit data are sent to these a plurality of latch units; And

One digital to analog converter is connected in this a plurality of latch units, is used for receiving the numerical data by these a plurality of latch unit outputs, is an analog voltage signal with this digital data conversion, and exports this analog voltage signal to this data line;

This method includes:

N bit circuitry lines by this load module receives this numerical data;

Using these a plurality of shift registers to export a plurality of switching signals in regular turn latchs so that these m group bit data are inputed to these a plurality of latch units in regular turn;

Order according to the switching signal of this shift register output inputs to this digital to analog converter so that this digital to analog converter receives this numerical data in regular turn with these m group bit data that are latched; And

Use this digital to analog converter that this digital data conversion is this analog voltage signal, and export this analog voltage signal to this data line;

Wherein, input to the numerical data of this corresponding digital to analog converter in these m group bit data earlier, can carry out precharge function this data line according to the order of the switching signal of this shift register.

2. the method for claim 1, wherein the number of this shift register is the integer that equals m, and produces m switching signal by this m shift register.

3. the method for claim 1, wherein the number of this shift register is the integer greater than m.

4. method as claimed in claim 2, wherein this m this m switching signal that shift register produced is m adjacent pulse signal, and in regular turn these m group bit data inputed in the same group of latch unit according to the time sequencing that this m adjacent pulse signal jumped up and to latch.

5. method as claimed in claim 4 wherein includes m latch unit in this group latch unit at least.

6. method as claimed in claim 4, wherein any latch unit in this group latch unit includes N/m latch circuit, and wherein this N/m is integer.

7. method as claimed in claim 4, wherein any latch unit in this group latch unit includes an integer latch circuit that is slightly larger than N/m.

8. method as claimed in claim 4, the time sequencing that the bit data of this m group that wherein is latched are jumped up according to this m adjacent pulse signal is sent to this corresponding digital to analog converter by this group latch unit in regular turn.

9. the method for claim 1, wherein this display is a LCD (LCD), low temperature polycrystalline silicon LCD (LTPS LCD), light emitting diode (LED), Organic Light Emitting Diode (OLED) or organic macromolecular LED diode (PLED).

10. data drive circuit is used for driving at least one data line of a display, and this data drive circuit includes:

N group bit circuitry lines, each bit that it corresponds to the numerical data of a N bit respectively is used for receiving this numerical data, and the numerical data of this N bit is divided into m group bit data, and wherein N and m all are the integers more than or equal to 2;

M shift register is used for exporting in proper order m switching signal, is used for controlling the order of this m group bit data transmission;

A plurality of latch units are electrically connected on this N group bit circuitry lines, are used for latching the numerical data that is transmitted by this N group bit circuitry lines; And

At least one digital to analog converter is used for receiving this digital signal by this latch unit output, this digital signal is converted to an analog voltage signal, and exports this analog voltage signal to this data line;

Wherein receive each bit in the numerical data of this N bit respectively when this N group bit circuitry lines, and after the numerical data of cutting apart this N bit becomes m group bit data, the order of the switching signal that produces according to this m shift register, these m group bit data are inputed to this corresponding latch unit in regular turn to latch, and this m that is latched group bit data also input to this corresponding digital to analog converter in regular turn according to the order of the switching signal of this m shift register generation, and use this digital to analog converter that this digital signal is converted to this analog voltage signal, export this analog voltage signal to this data line.

11. data drive circuit as claimed in claim 10, wherein this m this m switching signal that shift register produced is m adjacent pulse signal, and in regular turn these m group bit data inputed in the same group of latch unit according to the time sequencing that this m adjacent pulse signal jumped up and to latch.

12. data drive circuit as claimed in claim 11 wherein includes m latch unit in this group latch unit at least.

13. data drive circuit as claimed in claim 11, wherein any latch unit in this group latch unit includes N/m latch circuit, and wherein this N/m is an integer.

14. data drive circuit as claimed in claim 11, wherein any latch unit in this group latch unit includes an integer latch circuit that is slightly larger than N/m.

15. data drive circuit as claimed in claim 11, the time sequencing that the bit data of this m group that wherein is latched are jumped up according to this m adjacent pulse signal is sent to this corresponding digital to analog converter by this group latch unit in regular turn.

16. data drive circuit as claimed in claim 10, wherein this display is a LCD (LCD), low temperature polycrystalline silicon LCD (LTPS LCD), light emitting diode (LED), Organic Light Emitting Diode (OLED) or organic macromolecular LED diode (PLED).

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