CN1440161A

CN1440161A - Open single-wire asynchronous serial communication bus

Info

Publication number: CN1440161A
Application number: CN 02114884
Authority: CN
Inventors: 黄庆文
Original assignee: Individual
Current assignee: Individual
Priority date: 2002-02-21
Filing date: 2002-02-21
Publication date: 2003-09-03

Abstract

This invention discloses a method of asynchronous serial communication with single line of open type used in the family web and controlling web of distributing type. Any node in the web can transmit data through a signal line to other nodes, and any node's entering to and exiting from the web does not need another initialization of the whole web. The communication module with single line of open type carrying out this communication method consists mainly of the module for controlling communication commands, and module for reading and writing bytes, the module for receiving and transmitting signals, a shifting register for 8 bits and the ID bit memory. All nodes use the basic transmitting bitrate, however, higher bitrate can be used between two nodes according to a protocol.

Description

Open single-wire asynchronous serial communication bus

TECHNICAL FIELD OF THE INVENTION

The serial data that the present invention relates in a communication system sends agreement and its realization technology, specifically relate in one family network (Home Area Networks) or distributed control network, all information household appliances (Information Appliances), PC, controller and actuator can be realized a kind of method of asynchronous serial communication by a holding wire.

Background of invention is described

Digitlization and networking make that between electrical equipment and the electrical equipment, the information exchange between electrical equipment and the people just comes true, and are distributed in dozens of in the one family even hundreds of CPU and other integrated circuit and can constitute each node in the home network.Existing home network or personal network (Personal Area Networks) technology mainly comprises: wireless technology (for example bluetooth, HomeRF, and wireless ethernet IEEE 802.11b), utilize old line technology (for example telephone wire, power line) and laying new line technology (for example IEEE1394, general-purpose serial bus USB 2.0 and Ethernet etc.).Utilizing before the standard mesh of power line online is HomePNA 2.0, and object mainly is household electrical appliance, though its advantage is to lay ew line, exists the shortcoming that the power line noise jamming is big and equipment (HomePNA 2.0 modulator-demodulators) is expensive.In laying new line technology, IEEE1394 and USB2.0 are to be main object with the multimedia digital product, basically be the center with PC or USB master controller, connect various digital products, adopt the network topology structure of master-pair (Master-Slave), be that a main device can only be arranged in the system, other is passive ancillary equipment; Data transmission bauds height (IEEE1394 can reach 3.2Gbps, and USB2.0 can reach 480Mbps), so transmission cable can not be oversize, distance to increase hub (Hub); Ethernet is the technology of comparative maturity, because the signal demand coding and decoding, hardware requirement is higher.Suitable those requirements of these technology have the information household appliances than higher transmission baud rate, but present hardware costs is all than higher.

Also have the new line technology of laying of other two kinds of economy to be applied among home network and the distributed control network: a kind of is the I2C pipeline bus (Access Bus) that Dutch PHILIPS Co. utilizes the I2C bus to be extended to, this is a kind of multi-thread serial communication bus, at least comprise holding wire (SDA), clock line (SCL) and ground wire, for preventing capacitive coupling, SDA and scl line are not suitable for existing in same the twisted-pair feeder.I2C pipeline bus initial design purpose is to replace RS-232 to connect computer peripheral device; Another is that U.S. Patent number is the single bus structure of 5210846 dallas, u.s.a semiconductor company, the single bus of Dallas company exists the shortcoming of the low and network configuration unification of bit rate, single bus adopts the network topology structure of master-pair, is fit to monitor with a main device occasion of multiple sensor (routine hygrometer, thermometer, anemoscope etc.).

Abstract of invention

The purpose of this invention is to provide a kind of economical and practically, can connect into home network or distributed control network, adopt the asynchronous serial communication method of equity (Peer to Peer) network topology structure by a holding wire.Be primarily aimed to as if need be connected to the various electrical equipment of network, various controllers or transducer, non-high-speed multimedia digital product, these are called node, but are not suitable for the high-speed video media product.The peer to peer topology structure that adopts makes each node that is connected to home network or distributed control network can both be as main device, and promptly each node can be on one's own initiative and other node switching data.Each node can " one insert promptly use " (Plug and Play), the adding of node and withdrawing from do not need whole network from new initialization, so the present invention is the localized network technology of exploitation formula.This network system is made up of two parts: the open single-wire bus between node and connected node.In fact the open single-wire bus is made up of a holding wire and a ground wire, can be with the sound equipment line or the video line of band shielding, also can be with twisted pair telephone or flat cable, but be not limited to given example; The node of realizing the open single-wire agreement has the CPU that can finish protocol operation usually, or other integrated circuit, application-specific integrated circuit (ASIC) (ASIC) for example, field programmable gate array (FPGA), CPLD (CPLD), and signal drive circuit.Each node has one only one identifier (ID), and identifier is obtained when node adds network at first.

Usually, if node needs the power supply supply, can also increase a power line in the open single-wire bus is the node power supply.

Description of drawings

By the following accompanying drawing of reference, those skilled in the art can be expressly understood open single-wire bus structures feature set forth in the present invention and advantage thereof.In the accompanying drawing:

Fig. 1 describes the baseband signal waveform that exists on the open single-wire holding wire;

Fig. 2 describes the module diagram of carrying out the open single-wire serial communication by a holding wire;

Fig. 3 describes the communications command control module and sends the order flow chart;

Fig. 4 describes the communications command control module and receives the order flow chart;

Fig. 5 is described in the state machine of byte module for reading and writing inner control byte read-write;

Fig. 6 is described in writing of signal transceiver inner control initial signal and byte of sync and confirmation signal, logical one, the state machine of 0 read-write;

Fig. 7 is described in the state machine of following the trail of initial signal and byte of sync and confirmation signal in the signal transceiver;

Fig. 8 description node signal input and output circuit;

Describe in detail

According to the present invention, holding wire on the open single-wire bus always is in high level under no signal condition, when signal is arranged, exist four kinds of baseband signal waveform: initial signal STR on the holding wire, byte of sync and confirmation signal ACK, logical one, and logic zero signal will be formed all orders and data message by these four kinds of signals.With reference to Fig. 1, four baseband signal oscillograms on the open single-wire bus have been shown.Clock 10 is the coordination clocks in the transmit leg node communication module, is used for coordinating to control the output and the reception of four baseband signals.Usually, in no signal when output on the holding wire, each communication module is all moved holding wire to high level H, when certain communication module write pulse ' 0 ', then holding wire is moved to low level L, during write pulse ' 1 ', then allows holding wire remain on high level.Before each communication module was requested to make a speech, it all will be observed holding wire and has stopped to have held one section preset time on high level, just can send initial signal STR, and this section scheduled time should surpass the time of a byte of transmission usually.The coordination clock of each communication module will have identical frequency when communication, but more or less asynchronous all, therefore according to the present invention, each communication module all required to send a byte of sync and confirmation signal ACK before byte data of transmission, so that second the coordination clock cycle of recipient's node after observing the end of ACK waveform begins to read the data of a byte, therefore the single bus before byte data of transmission always is not in high level.Signal ACK for example, according to the present invention, in the Point-to-Point Data exchange on open single-wire, requires the recipient to respond a signal ACK after receiving a byte data simultaneously also as recipient's confirmation signal, and the other side's data have been received in expression.

In a preferred embodiment of the invention, signal STR is the pulse trains (sequential 20) of five positions for " 00110 ", signal ACK is the pulse trains (sequential 30) of four positions for " 0100 ", logical one is the pulse trains (sequential 40) of three positions for " 111 ", and logical zero is the pulse trains (sequential 50) of three positions for " 000 ".5 high level sequences (i.e. " 11111 ") of coordinating the clock cycle under signal STR and the no signal condition, be 3 with under ack signal and the no signal condition 4 Hamming distance (Hamming Distance) d that coordinate the high level sequence (i.e. " 1111 ") of clock cycle (have 3 positions inconsistent), make that t is the wrong figure place that can correct, usually think d 2t+1 in the coding theory, so t=1, be that mistake appears in the last arbitrary position of signal STR and signal ACK, they can both come with overall height level separation, thereby still can be recognized.Similarly, the Hamming distance of logical one and logical zero is 3, even they have one mistake to occur, can both make a distinction with the other side.Logical one and logical zero are duplication code (Repetition Code), reasonable position error correcting capability are arranged, though exist the shortcoming that reduces transmission bit rate.

Clock 60 is the coordination clocks in recipient's node communication module.Therefore clock 10 was on the different silicons with clock in 60 minutes, more or less asynchronous all.Clock 60 is clocks that recipient's node is used for coordinating to read signal, and when this node during at next write signal, clock 60 is exactly the clock 10 of this node, therefore should be understood that, the communication module of a node has only one to coordinate clock.Because clock 10 and clock 60 need not propagated, therefore can reduce electromagnetic radiation on open single-wire.

With reference to Fig. 2, shown according to a preferred embodiment of the present invention, carry out the module diagram of open single-wire communication by a holding wire.In fact open single-wire is made up of two lines, and one is that 70, one of ground wires are holding wires 80, and ground wire provides reference low level.Open single-wire communication module 90 is mainly by signal transceiver module 100, byte module for reading and writing 110, communications command control module 120,8 bit shift register, and a composition such as ID bit memory.Signal transceiver is responsible for the read-write control to baseband signal, it is the lowermost layer in the open single-wire communication module, can be application-specific integrated circuit (ASIC) (ASIC) or the programmable logic device (FPGA that uses in the information household appliances, CPLD etc.) a signal transceiver module, also can be a controll block of the microprocessor (CPU) that uses in the information household appliances, for example universal asynchronous receiver transmit (UART) with data input and output.The byte module for reading and writing is the intermediate layer in the open single-wire communication module, receives the control command from the communications command control module, is responsible for the control to the byte read-write, signal transceiver is sent the read write command of four kinds of baseband signals.Shift register is connected between signal transceiver and the byte module for reading and writing, realized bi-directional conversion parallel and serial signal, when the byte module for reading and writing is read byte, the logical message that signal transceiver will read is temporary in the lowest order (the 1st) of shift register, shift register moves to left one subsequently, and the byte module for reading and writing then reads byte from shift register; And when the byte module for reading and writing was write byte, it write shift register to byte data earlier, signal transceiver read shift register highest order (the 8th), and shift register moves to left one subsequently.The communications command control module is top in the open single-wire communication module, is responsible for reception and transmission to communications command, and the byte module for reading and writing is sent byte read write command or signal ACK, the write order of signal STR.The ID bit memory is used for the storage node online record, receive the affirmation signal of certain identifier corresponding node when node after, the corresponding positions of the ID bit memory of node will be designated as ' 1 ', otherwise be designated as ' 0 ', and node can be searched record from the ID bit memory when needed.

In the communications command control module, communications command generally includes four kinds of basic commands: new node adds order, data broadcasting order, Point-to-Point Data transmission order and identifier querying command; Node (comprise add new node) must equisignal line remains on high level could send communications command after one period scheduled time, must send out an initial signal STR earlier before the transmission communications command; Therefore order can be had 256 different orders, but only used four kinds of basic commands in a preferred embodiment of the invention by a byte representation; Following what order the back is the identifier (except the new node) of this node, each identifier ID can be made of a byte, ID is used to addressing and identification, therefore exist 256 different node addresss, but the invention is not restricted to this, under the enough big permission of signal driving force, figure place that can extended identifier, thereby the quantity that expands node on the open single-wire bus; Each node is before sending a byte ID or data, all must send a byte of sync and confirmation signal waveform earlier, and second the coordination clock cycle of reciever node after observing a byte of sync and confirmation signal waveform begins to read the data of this byte.

Fig. 3 has shown that the communications command control module of transmit leg node sends the flow chart of communications command.Step 2 after beginning, node is required to observe in advance the single-wire signal line and has been in one section preset time T1 is arranged on the high level, for example equal 24 width (writing the clock width of a byte) of coordinating clock, if communications command is arranged will be carried out, send a STR initial signal in step 4, send the corresponding communication command byte in step 5.Enter different flow process branches according to different communications commands.

If new node adds networking command, send ID number of queries n in step 7, establish initial transmission identifier ID in step 8 and be " 00000001 ", in the preferred embodiment of the present invention, ID is defined as a byte word length; After the transmission byte finished, bus automatically reverted to high level.In step 10, if bus has signal ACK to confirm, then the ID bit memory corresponding positions of a n position is recorded as ' 1 ' in one section scheduled time T2, the node of representing this ID on line, no signal ACK confirms, then the ID of this ID as oneself; In step 15, ID increases progressively 1, arrive the ID maximum number just withdraws from always, do like this and can make new node look through all identifier IDs, therefore the node of knowing what id number on line, what id number does not have node, what node cuts off the power supply or leaves holding wire, any outage or the node that leaves holding wire add fashionable again in next time, require to add networking command from new execution.

If broadcast data order, then send the ID of oneself in step 17, send the data byte number in step 18, in a preferred embodiment of the invention, total amount of byte should be above 256, therefore node can only be broadcasted the data set smaller or equal to 256 bytes on the single-wire signal line in a communications command, can prevent that so the oversize string data from losing, and also can prevent the some oversize time of node seizing signal line.The communications command control module reads the transmission data from data storage, repeating step 19,20 is till Data Transfer Done.Preferably, data set begins with a data head, and data head generally includes operational order, inquiry command, beginning or finishes to use non-basic transmission bit rate order, and the data head order of broadcasting can also comprise that each node of requirement restarts, or a certain node is notified each node etc. before leaving.Follow data to comprise measured value, controlling value, Control Parameter, perhaps other display message etc. in the data head back.Data head can be made up of more than one byte, and the present invention suggestion is placed on the processing of data set in the higher level module that is based upon on the open single-wire communication module and carries out.

If point-to-point transmission data command, usually, node often will be checked the ID bit memory of oneself earlier, to determine just to send this order under the online situation of recipient.In step 22, send recipient's ID, under receiving that signal ACK responds with the online situation of the node of be sure oing this ID, flow process continues to enter step 25 and sends the ID of oneself, and the node communication module will be received byte of sync and confirmation signal ACK by T2 (for example equaling 6 fundamental clock width) in one period scheduled time then.According to the present invention, after point-to-point data send, the recipient requires to send a byte of sync and confirmation signal ACK, because recipient's node will send byte of sync and confirmation signal at T2 in the time, and transmit leg will just be sent out the byte of sync and the confirmation signal of second byte after time T 2, so both sides' node will can not be obscured the implication of these two signal ACK.Send the data byte number in step 28, equally preferably, byte number is no more than 256.Repeating step 31 to 34 sends up to data and finishes.In point-to-point transmission data command process, if can not receive signal ACK in once the scheduled time T2 in office, this order is done failure in step 35 and is handled, and turns back to initial state.But the invention is not restricted to this, under no signal ACK affirmation situation, the node communication module can repeat to send and just withdraw from several times, before the data that repeat, then make the byte of sync signal to add difference with continuous 2 signal ACK, prevent that the recipient from having replied confirmation signal, but, thereby avoid the repetition reading of data on holding wire because of noise is lost.

The data head of point-to-point transmission can be concrete order, and for example the central controller as node sends enabling signal can for another the local household electrical appliance (for example: heater, air conditioner etc.) at home network; Perhaps an air conditioner sends the order that requires recovery temperature value, humidity value for the transducer of other end, room, and replying data will be as the reference of next step operation of air conditioner.

If the node ID querying command then enters step 37, after ID sends,, then corresponding position on the ID bit memory is designated as ' 1 ', otherwise is designated as ' 0 ' if there is signal ACK to respond.If desired, this order can be used before Point-to-Point Data transmits.

Fig. 4 has shown the flow chart of recipient's node communication command control module received communication order.Step 44 after beginning, node are observed the signal STR on the holding wire, and certain node is requested to make a speech on this signal indication network.If receive signal ACK, receive the transmit leg communications command in step 45, the communications command control module will enter different flow process branches according to each communications command.

If being new node, the communications command that receives adds networking command, then earlier receive the ID number of queries in step 47, read the ID of inquiry in step 48, if the ID of oneself, then send confirmation signal ACK in step 50, expression is own on exploitation formula single bus, if not the ID of oneself, then forward step 51 to and wait for the affirmation signal of other node, if in time T 2, there is signal ACK to respond, then corresponding position on the ID bit memory is designated as ' 1 ', represents that this ID value has corresponding node on bus.If no signal ACK responds corresponding position is designated as ' 0 '.Repeating step 48～52 is finished by inquiry up to all ID.

If the communications command that receives is the data broadcasting order, then the data that receive are deposited in data storage in step 56.

If being Point-to-Point Data, the communications command that receives sends order, then enter step 59, if the ID that receives is the ID of oneself, then continue to receive the other side's ID in step 62, receive data in step 66, after receiving data, whenever to read the content of a byte and will on holding wire, send confirmation signal ACK, these data have been received in expression.If the ID that receives is not the ID of oneself, then be withdrawn into initial state.

If the order that receives is the ID querying command, node judges whether the id number of oneself after receiving ID, if then send confirmation signal ACK.

In the reception order flow process of Fig. 4 display communication command control module, if recipient's node is not received byte of sync and confirmation signal ACK in one section scheduled time T2, then make the order Interrupt Process, return to initial state then.

According to the present invention, the communications command control module will realize the transmission and the reception of communications command by the write order that the byte module for reading and writing is sent byte read-write and signal ACK, signal STR on stream.According to the present invention, data are unit of transfer with the byte, therefore will preferably set up the read-write that a state machine comes control byte in the byte module for reading and writing, and this state machine also is responsible for signal transceiver is sent the control of writing of signal ACK and signal STR simultaneously.This state machine is coordinated by faster three times than transmission bit rate at least fundamental clock, requires two nodes in communication to use identical coordination clock frequency simultaneously.Fig. 5 has shown this state machine, and the next state of this state machine will be by the operation of current state, decide from the control command of communications command control module with from the input signal of signal transceiver.This state machine is checked its order and signal incoming event during each period of state, change over NextState when the next one is coordinated rising edge clock.Listing the condition of change state in the following table describes:

The condition of change state	Describe	Remarks
The condition of change state	Describe	Remarks	??NOP	What is not done
??STR	Signalling STR	The control command of communications command control module	??NOP	What is not done
??STR	Signalling STR		??ACK	Signalling ACK	The control command of communications command control module
??RDB	Read byte	The control command of communications command control module	??ACK	Signalling ACK
??RDB	Read byte		??WRB	Write byte	The control command of communications command control module
??SILEN	Holding wire rests on high level at T2 in the time	Input signal from signal transceiver	??WRB	Write byte
??SILEN	Holding wire rests on high level at T2 in the time	Input signal from signal transceiver	??RACK	Receive byte of sync and confirmation signal	Input signal from signal transceiver
??UFR	Do not read the 8th	The operation of current state	??RACK	Receive byte of sync and confirmation signal	Input signal from signal transceiver
??UFR	Do not read the 8th	The operation of current state	??UFW	Do not write the 8th	The operation of current state
??FR	Run through the 8th	The operation of current state	??UFW	Do not write the 8th	The operation of current state
??FR	Run through the 8th	The operation of current state	??FW	Write the 8th	The operation of current state
??EX	No matter what		??FW	Write the 8th	The operation of current state

Following table is listed 7 kinds of possibilities state description of this state machine:

State	State description	This state is handed down to the order of signal transceiver
State	State description		??idle	Idle condition	What is not done
??str	Write signal STR state	Signalling STR	??idle	Idle condition	What is not done
??str	Write signal STR state	Signalling STR	??ack	Write signal ACK state	Signalling ACK
??rd1	Read byte status 1	Do not say the word wait byte synchronizing signal ACK	??ack	Write signal ACK state	Signalling ACK
??rd1	Read byte status 1	Do not say the word wait byte synchronizing signal ACK	??rd2	Read byte status 2	Read logical message
??wr1	The nodular attitude 1 of writing	Signalling ACK	??rd2	Read byte status 2	Read logical message
??wr1	The nodular attitude 1 of writing	Signalling ACK	??wr2	The nodular attitude 2 of writing	Write logic (1 or 0)

According to a preferred embodiment of the invention, will set up a state machine and control initial signal STR in signal transceiver, byte of sync and confirmation signal ACK write and logical one, 0 read-write.This state machine uses identical coordination clock to coordinate with byte module for reading and writing internal state machine.Fig. 6 has shown this state machine, and the next state of state machine decides by current state with from the control command of byte module for reading and writing.This state machine is checked its control command input during each period of state, coordinate rising edge clock at the next one and change over NextState temporarily.List description in the following table from the control command of byte module for reading and writing:

The control command of byte module for reading and writing	Control command is described
The control command of byte module for reading and writing	Control command is described	????NOP	What is not done
????ST	Signalling STR	????NOP	What is not done
????ST	Signalling STR	????AC	Signalling ACK
????RD	Read logical message	????AC	Signalling ACK
????RD	Read logical message	????WR	Write logic (1 or 0)

????EX

No matter the order of input

16 kinds of possibilities state description of this state machine:

State	State description	Concrete operations under this state
State	State description	Concrete operations under this state	??idle	Idle condition	What is not done
??st1	First cycle of write signal STR	Write pulse ' 0 ' on holding wire	??idle	Idle condition	What is not done
??st1	First cycle of write signal STR	Write pulse ' 0 ' on holding wire	??st2	The second period of write signal STR	Write pulse ' 0 ' on holding wire
??st3	The 3rd cycle of write signal STR	Write pulse ' 1 ' on holding wire	??st2	The second period of write signal STR	Write pulse ' 0 ' on holding wire
??st3	The 3rd cycle of write signal STR	Write pulse ' 1 ' on holding wire	??st4	The 4th cycle of write signal STR	Write pulse ' 1 ' on holding wire
??st5	The 5th cycle of write signal STR	Write pulse ' 0 ' on holding wire	??st4	The 4th cycle of write signal STR	Write pulse ' 1 ' on holding wire
??st5	The 5th cycle of write signal STR	Write pulse ' 0 ' on holding wire	?ack1	First cycle of write signal ACK	Write pulse ' 0 ' on holding wire
?ack2	The second period of write signal ACK	Write pulse ' 1 ' on holding wire	?ack1	First cycle of write signal ACK	Write pulse ' 0 ' on holding wire
?ack2	The second period of write signal ACK	Write pulse ' 1 ' on holding wire	?ack3	The 3rd cycle of write signal ACK	Write pulse ' 0 ' on holding wire
?ack4	The 4th cycle of write signal ACK	Write pulse ' 0 ' on holding wire	?ack3	The 3rd cycle of write signal ACK	Write pulse ' 0 ' on holding wire
?ack4	The 4th cycle of write signal ACK	Write pulse ' 0 ' on holding wire	??rd1	First cycle that logic is read	The current level of reading signal lines
??rd2	The second period that logic is read	The current level of reading signal lines	??rd1	First cycle that logic is read	The current level of reading signal lines
??rd2	The second period that logic is read	The current level of reading signal lines	??rd3	The 3rd cycle that logic is read	The current level of reading signal lines
??wr1	First cycle that logic is write	Write pulse ' 0 ' on holding wire (during logical zero) or write pulse ' 1 ' (during logical one)	??rd3	The 3rd cycle that logic is read	The current level of reading signal lines
??wr1	First cycle that logic is write		??wr2	The second period that logic is write	Write pulse ' 0 ' on holding wire (during logical zero) or write pulse ' 1 ' (during logical one)
??wr3	The 3rd cycle that logic is write	Write pulse ' 0 ' on holding wire (during logical zero) or write pulse ' 1 ' (during logical one)	??wr2	The second period that logic is write

If signal transceiver in certain coordinates clock cycle to holding wire on write pulse ' 1 ', then keep high level, if to write pulse on the holding wire ' 0 ', then drag down level.

As shown in Figure 6, state machine just receives new operational order under idle state or the final state in command operation.Behind state st1, state machine is carried out the order that st5 finishes a write signal STR continuously, at the st5 state, if receive the AC order, then enters the ack1 state.As a same reason, after entering rd1 and wr1 state, all be to carry out continuously just to accept other order after a complete logic reads or writes order.NOP do not need to represent the order of what operation.

According to a preferred embodiment of the invention, in signal transceiver, set up the generation that the another one state machine comes trace signals STR and signal ACK.Fig. 7 has shown this state machine, and the next state of this state machine is decided by the incident under current state and the current state.Similarly, this state machine is checked event during each period of state, changes over NextState when the next one is coordinated rising edge clock.Following table is listed the description of each incident:

Incident	Event description
Incident	Event description	??HL	Holding wire transfers low level to by high level
??E0	Holding wire is a low level	??HL	Holding wire transfers low level to by high level
??E0	Holding wire is a low level	??E1	Holding wire is a high level
??EX	No matter what level	??E1	Holding wire is a high level

14 kinds of possibilities state description of state machine:

State	State description	Operation under this state
State	State description	Operation under this state	??idle	Idle condition	Read current demand signal line level
??ACK	Receive signal ACK	Notification module has signal ACK	??idle	Idle condition	Read current demand signal line level
??ACK	Receive signal ACK	Notification module has signal ACK	??STR	Receive signal STR	Notification module has signal STR
?n1～n11	Follow the trail of ACK or STR signal	Read current demand signal line level	??STR	Receive signal STR	Notification module has signal STR

As shown in Figure 7, under the idle state,, represent may occurring of a signal ACK or signal STR, so NextState transfers the n1 state to when holding wire takes place to transfer low level incident HL to by high level.This state machine is checked the logic level of holding wire during each period of state, read from signal STR on the holding wire or signal ACK by observing correct pulse train.But the invention is not restricted to this, this state machine can also be modified as can recognize STR or the ack signal that a digit pulse mistake takes place, as previously described, according to the present invention, 5 high level sequences (i.e. " 11111 ") of coordinating the clock cycle under signal STR sequence and the no signal condition, be 3 with 4 Hamming distance d that coordinate the high level sequence (i.e. " 1111 ") of clock cycle under ack signal sequence and the no signal condition, therefore arbitrary position receives error level on STR and the signal ACK sequence, can both be distinguished, for example, the Hamming distance of " 01110 " and " 00110 " is nearer with the Hamming distance of " 11111 " than " 01110 ", and therefore " 01110 " is recognized it is signal STR but not the high level of no signal.

Fig. 8 has shown the preferred embodiment of realizing open single-wire nodes in communication signal input and output circuit.There are two nodes that separate 130 and 140 in this system, to show.When all nodes are not exported, show that the single-wire signal line is in high level state, therefore, the signal output part of each node can connect a CMOS/TTL supply voltage (for example 5v) by a pull-up resistor (Ra, Rb among the figure), moves the holding wire level to high level.Because the output of node signal transceiver can not influence input Rx, therefore the output circuit of node has a ternary not gate, the reverse output of signal transceiver connects the control end of ternary not gate, when signal transceiver just when received signal is imported, its output Tx transfers high level to, the output of ternary not gate will become high-impedance state, block the influence of this node output to input by the high-impedance state of ternary not gate.

Long holding wire and the node on the line exist direct-to-ground capacitance, and wherein longer signal line capacitance Cs is bigger than node direct-to-ground capacitance (C1, C2 among the figure), if but interstitial content is a lot, and then total node capacitor will increase.When the node output is write logical zero and during degrade signal line level, this process can be regarded all capacitance discharges processes as, this moment, the output of ternary not gate will be received the electric current and the pull-down current of capacitance load as quickly as possible; And when the node output is write logical one, the single line level will be drawn high, this process can be regarded the charging process of electric capacity as, make that R is a pull-up resistor in parallel, C is electric capacity sum (all lead capacitances and a node direct-to-ground capacitance sum), then time constant RC is restricting the switching rate (slew rate) of level, and promptly the RC time must be less than level conversion time, so R or C can not be too big.

In sum, the factor that influences open single-wire bus transfer bit rate mainly comprises: on the length of the selected cable of bus, cable, the bus in the number of the node of hanging and the node signal output circuit ternary not gate receive electric current (Iol) or drop-out current (Sinking Current).If cable is very long, interstitial content is a lot, then will sacrifice transmission bit rate.

The selection of cable is very important, the present invention's suggestion (total line length is less than 50m) under general case can be selected non-shielding twisted pair telephone (Category 3), select class 5 twisted-pair feeder (Category 5) under the longer situation for use, perhaps parallel flat cable, preferred IEEE1394 (Fire Wire) cable under the longer situation of holding wire.Usually, twisted pair telephone electric capacity is about 65pF/m, and parallel flat cable is 50pF/m.For example, when output circuit used two ternary not gates (Iol=40mA), setting and drawing electric current was 20mA, and then total parallel resistance should be R=5V/20 mA=250 ohms, suppose to have on the bus n pull-up resistor, then the resistance Ri=R/n=250/n ohms of each pull-up resistor.Suppose that transmission bit rate is 100Kbps, be 1 microsecond (μ s) change-over time, but then single bus capacitor load should not use unshielded twisted pair Cate3 greater than 4000pF, can transfer to about 60 meters long distances.Because resembling, open single-wire bus of the present invention do not need the transmitting synchronous clock the I2C bus, therefore do not resemble two cable (SLC of I2C, SDA) exist the phenomenon that electromagnetism interferes mutually when high-speed bit rate (particularly) between like that, therefore the open single-wire signal can propagate longer distance.

Connected node input Rx and output Tx's can be two of general serial transceiver (UART) ends number above the microprocessor: Rx, Tx, if the open single-wire communication module is the functional module of FPGA or CPLD, Rx then, Tx can be two input and output ports above the logical device.Those skilled in the art can also pass through level conversion, utilizes the serial signal I/O mouth of RS-232 to carry out open single-wire communication.

According to the present invention, it is freely that each node adds the open single-wire network, therefore exist a problem: along with the increase of interstitial content, pull-up resistor in parallel can reduce along with the increase of parallel resistance number, thereby cable capacitance can prolong discharge time, single line is pulled to the low level time by high level and can extends, and capacitor charging time can shorten.Therefore the present invention's suggestion is not that each node all needs to be with pull-up resistor, and the nearer node of particularly being separated by can a shared pull-up resistor; And longer at cable, interstitial content is more, and transmission bit rate is greater than under the 100Kbps situation, and node should be in parallel a plurality of or be used the ternary not gate that receives electric current (Iol) is more greatly arranged.According to one embodiment of present invention, select the DM74LS125A chip of National Semiconductor for use, this chip contains four ternary not gates, each Iol electric current up 24mA.

Consider that each node need use identical coordination clock frequency to communicate by letter, therefore the present invention has preferably stipulated the coordination clock frequency of a basic 50KHz, require when node need be with all node communications to use this basic coordination clock frequency to control the transmission communications command, for example add networking command, broadcast data order and ID querying command, and each node requires under idle condition to use the coordination clock frequency of 50KHz to follow the trail of speech initial signal STR.Many nodes also need other transmission bit rate, so they can use point-to-point communication bidding protocol both sides communication frequency next time when the coordination clock frequency of 50KHz.For example, certain node can utilize the point-to-point communication order to send the data set of 3 bytes for the another one node, data set begins with a data head, the data head of first byte is defined as newly coordinating the initiation command of clock frequency, second, it is the coordination clock frequency number of unit that the 3rd byte data is defined as with 1KHz, after this communications command finishes, both sides' node will use new communication-cooperation clock frequency conversation, behind sign off, node sends data for the other side's node with the point-to-point communication order again, and first byte data head is the order that finishes present communication-cooperation clock frequency.

As previously described, if use higher transmission bit rate, require reception and transmit leg node must have bigger drop-down level and receive electric current.The present invention suggestion is only coordinated clock or bit rate with 50KHz and is used a ternary not gate (Iol=20mA) to connect holding wire less than the node of 16Kbps, and bit rate is higher than the node of 100Kbps and will uses the bigger output circuit that receives electric current.The present invention does not limit concrete designing circuitry.

Be to be understood that, the open single-wire agreement is except being applied to the home network, can also be applied in the Distributed Control Network System, the for example distributed control of central air-conditioning, each room controller can be got in touch by open single-wire and central controller, the complicated control circuit that both can avoid Star Network to distribute being brought can add new Control Node easily within the specific limits again and not need to change whole control circuits.Can also be applied in the agriculture supervisory control system of market garden, only need a holding wire, a ground wire and a power line, can minimally reduce circuit and distribute, and picture signal and temperature, moisture measurement numerical signal can transmit by different bit rates.

Compare with a wire protocol of dallas, u.s.a semiconductor company, the open single-wire agreement uses repeater (Repeater) just can arrive longer distance by the extended network cable; Also because open single-wire uses the network topology structure of equity (Peer to Peer), each node is all as main device, and a main device comparing a wire protocol can make network that more purposes is arranged; Different nodes on the open single-wire are on the fundamental clock frequency basis of 50KHz, and agreement is used higher transmission bit rate neatly, and a wire protocol has only a kind of transmission bit rate.I with Dutch PHILIPS Co. ²C pipeline bus is compared, open single-wire has only a holding wire, eliminated the electromagnetic interference phenomenon between holding wire and the clock line, can also reduce the abundance of cable, in addition, the I2C bus also only defines two kinds of transmission bit rate: 100Kbps and 400Kbps, thereby the open single-wire agreement can be applied to occasion widely.

Those skilled in the art can do many modifications not breaking away from principle of the present invention and the spiritual basis, and disclosed example is exemplary and nonrestrictive in the specification of the present invention, and scope of the present invention is limited by appended claims.

Claims

1. asynchronous serial communication method that is applied to home network and distributed control network, its feature comprises:

Node is realized open single-wire communication by holding wire, and all nodes can both transmit data to other node on one's own initiative, the adding of any node and exitting network do not need whole network from new initialization.

2. node as claimed in claim 1 is characterized in that all nodes all have one only one identifier, and this identifier is obtained when node adds the open single-wire network at first, and identifier is used to addressing and identification.

3. holding wire as claimed in claim 1, it is characterized in that under no signal condition, holding wire always is in high level, is having under the signal condition, exists four kinds of basic pulse signal waveform: initial signal STR, byte of sync and confirmation signal ACK, logical one signal and logic zero signal on the holding wire.

4. open single-wire communication as claimed in claim 1, the open single-wire communication module that it is characterized in that realizing this communication means is mainly by the byte module for reading and writing in top communications command control module, intermediate layer, the signal transceiver module of lowermost layer, 8 bit shift register that are connected between signal transceiver and the byte module for reading and writing, and an ID bit memory is formed.

5. communications command control module as claimed in claim 4 is characterized in that the communications command of being controlled comprises: new node adds order, data broadcasting order, Point-to-Point Data transmission order and identifier querying command; Before sending communications command, the communications command control module must send an initial signal STR earlier.

6. data broadcasting order as claimed in claim 5 and Point-to-Point Data transmit order, it is characterized in that one group of data that the transmit leg node sends begin with a data head; Transmit in the order flow process in Point-to-Point Data, the reciever node must be sent out a byte of sync and confirmation signal ACK confirms after receiving a byte data.

7. byte module for reading and writing as claimed in claim 4, it is characterized in that realizing the control of byte read-write by a state machine, with to the signal transceiver transmitting control commands, this state machine is by coordinating than the fast three times clock of bit rate of transmission at least, and the node that requires two dialogues uses identical coordination clock frequency, and the next state of state machine will be by the operation of current state, decide from the control command of communications command control module with from the input signal of signal transceiver.

8. byte module for reading and writing as claimed in claim 4, it is characterized in that each byte is before sending, must send a byte of sync and confirmation signal ACK earlier, second clock cycle of recipient's node after observing signal ACK begins to read the information of this byte.

9. signal transceiver module as claimed in claim 4, it is characterized in that realizing writing with the read-write of logical one, logic zero signal of initial signal STR, byte of sync and confirmation signal ACK controlled by a state machine, this state machine uses and coordinates with the described identical clock of claim 7, and the next state of this state machine decides by current state and from the control command of byte module for reading and writing; Come the generation of initial signal STR on the trace signals line, byte of sync and confirmation signal ACK by the another one state machine, this state machine uses and coordinates with the described identical clock of claim 7, and the next state of this state machine is decided by the incident under current state and the current state.

10. the method for claim 1, it is characterized in that node uses a fundamental clock frequency of making an appointment to coordinate the work of open single-wire communication module need be with all node communications the time, and each node uses also when idle condition this fundamental clock frequency to follow the trail of initial signal STR; Node can also transmit order by Point-to-Point Data, uses higher coordination clock frequency with other node agreement.