CN120452516A - Method and device for testing storage unit and storage medium thereof - Google Patents
Method and device for testing storage unit and storage medium thereofInfo
- Publication number
- CN120452516A CN120452516A CN202510479804.2A CN202510479804A CN120452516A CN 120452516 A CN120452516 A CN 120452516A CN 202510479804 A CN202510479804 A CN 202510479804A CN 120452516 A CN120452516 A CN 120452516A
- Authority
- CN
- China
- Prior art keywords
- storage unit
- environment
- voltage
- test
- temperature
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Techniques For Improving Reliability Of Storages (AREA)
Abstract
本申请提供了一种存储单元的测试方法、装置及存储介质，该方法包括：获取多个目标工作参数范围；根据所述多个目标工作参数范围确定第一模拟环境，其中，所述第一模拟环境用于模拟驱动所述存储单元的多个跳变环境；在所述第一模拟环境中基于所述多个跳变环境控制所述存储单元执行目标操作，得到第一测试结果。本申请的方案能够实现对存储单元模拟在实际使用环境中的测试，以此提高了对存储单元进行检测准确性，进而能够基于得到的第一测试结果来对存储单元进行筛选，进一步提高了存储单元的实际使用的适用性。
The present application provides a method, device, and storage medium for testing a storage unit, the method comprising: obtaining multiple target operating parameter ranges; determining a first simulation environment based on the multiple target operating parameter ranges, wherein the first simulation environment is used to simulate multiple transition environments for driving the storage unit; and controlling the storage unit to perform a target operation based on the multiple transition environments in the first simulation environment to obtain a first test result. The solution of the present application can simulate the test of the storage unit in an actual use environment, thereby improving the accuracy of the detection of the storage unit, and can further screen the storage unit based on the obtained first test result, further improving the applicability of the storage unit for actual use.
Description
Technical Field
The present invention relates to the field of data storage, and in particular, to a method and apparatus for testing a storage unit, and a storage medium thereof.
Background
At present, with the rapid development of technology, the storage performance of the device becomes one of the important performances of the device, and the storage performance is mainly related to the storage unit of the device, and further, the storage performance of the device in practical application can be ensured by detecting the storage unit in advance. At present, the method for detecting the storage unit can only detect the problem that the storage unit is easy to expose, and can not avoid some fault products. Therefore, how to improve the applicability of the practical use of the memory cell by improving the detection accuracy of the memory cell is a problem to be solved.
Disclosure of Invention
The invention mainly solves the technical problems that the existing method for detecting the storage unit has lower accuracy, thereby causing low accuracy in screening the fault product and low applicability in actual use of the storage unit.
According to a first aspect, in one embodiment, a method for testing a memory cell is provided, and the method includes the steps of obtaining a plurality of target working parameter ranges, determining a first simulation environment according to the plurality of target working parameter ranges, wherein the first simulation environment is used for simulating a plurality of jump environments for driving the memory cell, and controlling the memory cell to execute target operation based on the plurality of jump environments in the first simulation environment to obtain a first test result.
According to a second aspect, an embodiment provides a testing device of a storage unit, which comprises an acquisition module, a first simulation environment determining module and a first testing module, wherein the acquisition module is used for acquiring a plurality of target working parameter temperature ranges, the first simulation environment determining module is used for determining a first simulation environment according to the plurality of target working parameter ranges, the first simulation environment is used for simulating a plurality of jumping environments for driving the storage unit, and the first testing module is used for controlling the storage unit to execute target operation based on the plurality of jumping environments in the first simulation environment to obtain a first testing result.
According to a third aspect of embodiments of the present application, there is provided a computer readable storage medium having stored thereon computer readable instructions which, when executed by a processor, implement a method of testing a storage unit as described above.
According to a fourth aspect of an embodiment of the present application, there is provided an electronic device including a processor, and a memory having stored thereon computer readable instructions which, when executed by the processor, implement a method of testing a memory unit as described above.
According to the method and the device for testing the memory cell, the plurality of target working parameter ranges of the memory cell are acquired, so that the first simulation environment corresponding to the plurality of jump environments for simulating and driving the memory cell can be determined according to the plurality of working parameter ranges, the memory cell can be controlled to execute target operation according to the plurality of jump environments in the first simulation environment, a first test result is obtained, the memory cell is simulated in an actual use environment, the detection accuracy of the memory cell is improved, the memory cell can be screened based on the obtained first test result, and the applicability of the memory cell in actual use is further improved.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the application and together with the description, serve to explain the principles of the application. It is evident that the drawings in the following description are only some embodiments of the present application and that other drawings may be obtained from these drawings without inventive effort for a person of ordinary skill in the art.
FIG. 1 is a flow chart of a method for testing a memory cell according to an embodiment of the application.
Fig. 2 is a flow chart of a method for testing a memory cell according to another embodiment of the application.
FIG. 3 is a flow chart of a method for testing a memory cell according to another embodiment of the application.
Fig. 4 is a flow chart of a method for testing a memory cell according to still another embodiment of the application.
FIG. 5 is a flow chart illustrating a detailed step description of step 430 according to an embodiment of the present application.
FIG. 6 is a flow chart of a method for testing a memory cell according to still another embodiment of the application.
FIG. 7 is a block diagram of a memory cell testing apparatus according to an embodiment of the present application.
Fig. 8 is a hardware configuration diagram of an electronic device according to an embodiment of the present application.
Specific embodiments of the present invention have been shown by way of the above drawings and will be described in more detail below.
Detailed Description
The application will be described in further detail below with reference to the drawings by means of specific embodiments. Wherein like elements in different embodiments are numbered alike in association. In the following embodiments, numerous specific details are set forth in order to provide a better understanding of the present application. However, one skilled in the art will readily recognize that some of the features may be omitted, or replaced by other elements, materials, or methods in different situations. In some instances, related operations of the present application have not been shown or described in the specification in order to avoid obscuring the core portions of the present application, and may be unnecessary to persons skilled in the art from a detailed description of the related operations, which may be presented in the description and general knowledge of one skilled in the art.
Furthermore, the described features, operations, or characteristics of the description may be combined in any suitable manner in various embodiments. Also, various steps or acts in the method descriptions may be interchanged or modified in a manner apparent to those of ordinary skill in the art. Thus, the various orders in the description and drawings are for clarity of description of only certain embodiments, and are not meant to be required orders unless otherwise indicated.
The numbering of the components itself, e.g. "first", "second", etc., is used herein merely to distinguish between the described objects and does not have any sequential or technical meaning. The term "coupled" as used herein includes both direct and indirect coupling (coupling), unless otherwise indicated.
At present, storage devices such as embedded multimedia cards (embedded multimedia MEDIA CARD, emmc) commonly used in electronic devices generally consist of a main control and a flash memory, wherein a sram memory is an important component of a main control chip, and can be used for temporary storage functions (cache) such as a ram, data, a table and the like of instruction codes, and can also be used as a register of the main control chip. Therefore, the direct relation emmc, ufs, ssd between the quality of the sram memory and other embedded application devices can work normally. At present, the detection of the sram memory can only detect some problems that are relatively easy to be exposed, can not avoid some fault products before the electronic equipment leaves the factory, and is more complex in the actual use environment of the electronic equipment, but the common detection method can not cover the actual use environment of the electronic equipment.
In the embodiment of the invention, a plurality of target working parameter ranges of the storage unit are acquired firstly, so that a first simulation environment corresponding to a plurality of jumping environments for simulating and driving the storage unit can be determined according to the plurality of working parameter ranges, the storage unit can be controlled to execute target operation according to the plurality of jumping environments in the first simulation environment, a first test result is obtained, the test of the storage unit in an actual use environment is realized, the detection accuracy of the storage unit is improved, the storage unit can be screened based on the obtained first test result, and the practical use applicability of the storage unit is further improved.
The block diagrams depicted in the figures are merely functional entities and do not necessarily correspond to physically separate entities. That is, the functional entities may be implemented in software, or in one or more hardware modules or integrated circuits, or in different networks and/or processor devices and/or microcontroller devices. The flow diagrams depicted in the figures are exemplary only, and do not necessarily include all of the elements and operations/steps, nor must they be performed in the order described. For example, some operations/steps may be decomposed, and some operations/steps may be combined or partially combined, so that the order of actual execution may be changed according to actual situations.
Referring to fig. 1, fig. 1 illustrates a method for testing a memory cell according to an embodiment of the present application, and in a specific embodiment, the method for testing a memory cell may be applied to a device 600 for testing a memory cell shown in fig. 7 and an electronic apparatus 700 (fig. 8) configured with the device 600 for testing a memory cell. The specific flow of the present embodiment will be described below, and it will be understood that the method may be performed by a computer terminal with computing processing capability, other processors, or a memory chip. The following details about the flow shown in fig. 1, the method for testing the storage unit may specifically include the following steps:
Step 110, a plurality of target operating parameter ranges are obtained.
As one way, the performance of the memory cell is mainly related to parameters such as the reading speed, writing speed, storage capacity, data reliability and energy consumption efficiency of the memory cell, which are related to the working parameters of the memory cell, for example, the voltage, current and temperature of the memory cell when the memory cell is working, so that the environment corresponding to the working parameters of the memory cell when the memory cell is working can be simulated in the test stage of the memory cell by adjusting the working parameters of the memory cell when the memory cell is working, and the memory cell can be tested in the environment, so that the memory cell can cover most of the use scenes.
In some embodiments, the target operating parameter comprises a voltage and/or a temperature, the plurality of voltage ranges is determined by a rated voltage of the memory cell, and the plurality of temperature ranges is determined by a rated temperature of the memory cell.
Optionally, the storage unit has corresponding operating parameters such as rated voltage, rated current, rated power and rated temperature, and the actual operating parameters of the storage unit may be in preset ranges corresponding to the rated voltage, the rated current, the rated power and the rated temperature, so that a plurality of voltage ranges can be determined according to the rated voltage of the storage unit, and a plurality of temperature ranges can be determined according to the rated temperature of the storage unit.
And step 120, determining a first simulation environment according to the target working parameter ranges, wherein the first simulation environment is used for simulating a plurality of jump environments for driving the storage unit.
As one way, after a plurality of target operating parameter ranges are acquired, the operating parameters of the storage unit may be set to specific parameter values corresponding to the corresponding target operating parameter ranges, respectively, so as to determine the first simulation environment.
Optionally, after the multiple target working parameter ranges of the storage unit are obtained, multiple jump environments for simulating the working of the storage unit can be set based on the multiple target working parameter ranges, and in the jump environments, the parameter range differences corresponding to different target working parameters are larger than a preset value, so that the jump environments can be used for simulating the first simulation environment. For example, when the target working parameter is voltage, in the first simulation environment, the voltage difference between the first jump environment and the second jump environment is greater than a preset voltage difference, wherein the preset voltage difference is a preset difference value corresponding to the jump voltage.
Alternatively, to be able to better test the memory cells in the first simulation environment, a plurality of jump environments may be determined according to a plurality of step voltage/temperature levels. Alternatively, a jump environment may be determined by fusing at least two stepped voltage/temperature levels into one voltage/temperature level.
And 130, controlling the storage unit to execute target operation based on the jump environments in the first simulation environment to obtain a first test result.
As a mode, after the first simulation environment is determined, the memory unit can be controlled to perform operations such as reading operation, writing operation, continuous reading and writing operation and the like through a plurality of jump environments in the first simulation environment, so that whether the memory unit can normally execute target operation in the jump environments or not can be tested, and a first test result can be obtained.
Optionally, the first test result includes that the storage unit can normally execute the target operation and cannot normally execute the target operation in the first simulation environment, if the first test result indicates that the storage unit can normally execute the target operation in the first simulation environment, the storage unit is determined to be capable of normally operating in the jump environment, and if the first test result indicates that the storage unit cannot normally execute the target operation in the first simulation environment, the storage unit is determined to not pass the test and cannot be subjected to online application, and the design of the storage unit is required to be repeated, so that the storage unit can normally execute the target operation in the jump environment.
Optionally, in order to further ensure the test accuracy of the storage unit, if the first test result indicates that the storage unit can work normally in the first simulation environment, it is determined whether the data written by the storage unit in the first simulation environment is identical to the read data (when the data is not written, no other data exists in the storage unit), so that the storage unit is determined to pass the jump environment test when the data is determined to be identical, and the storage unit is determined to not pass the test when the data is determined to be different.
In the embodiment of the application, a plurality of target working parameter ranges of the storage unit are acquired first, so that a first simulation environment corresponding to a plurality of jumping environments for simulating and driving the storage unit can be determined according to the plurality of working parameter ranges, the storage unit can be controlled to execute target operation according to the plurality of jumping environments in the first simulation environment, and a first test result is obtained.
Referring to fig. 2, fig. 2 shows a method for testing a memory cell according to an embodiment of the application. The following details about the flow shown in fig. 2, the method for testing the storage unit may specifically include the following steps:
Step 210, a plurality of target operating parameter ranges are obtained.
Step 220, determining at least one transition temperature range according to the plurality of temperature ranges, and determining at least one transition temperature range according to the determined voltage range.
As one way, at least two temperature ranges may be combined after a plurality of temperature ranges are acquired, so that at least one jump temperature range can be obtained, and at least two voltage ranges may be combined after a plurality of voltage ranges are acquired, so that at least one jump voltage range can be obtained.
Optionally, in the plurality of jump temperature ranges, a temperature difference value corresponding to a limit temperature corresponding to each jump temperature range is greater than a temperature difference threshold value, so that a corresponding temperature jump environment can be determined based on each jump temperature range. Similarly, in the plurality of jump voltage ranges, the voltage difference value corresponding to the limit voltage corresponding to each jump voltage range is larger than the voltage difference threshold value, so that the corresponding voltage jump environment can be determined based on each jump voltage range.
Step 230, determining a voltage jump environment of the memory cell according to the limit temperature corresponding to the at least one jump temperature range, and determining the temperature jump environment of the memory cell according to the limit voltage determined by the at least one jump voltage.
In one manner, in the voltage hopping environment, the operating voltage of the device may be reduced by a cliff or increased by a jump due to various reasons (e.g., power on, power off, etc.), so that the voltage hopping environment of the memory cell may be determined according to the limit voltage corresponding to at least one jump voltage range in order to accurately simulate the voltage cliff or the jump that occurs during the operation of the memory cell. For example, if a jump voltage range is (1.2-7.2), it can be determined that the voltage jump environment of the memory cell is that the operating voltage of the memory cell is switched before 1.2 and 7.2, so as to obtain the voltage jump environment. Similarly, in the temperature jump environment, the working temperature of the device may be reduced in a cliff-like manner or increased in a jump-like manner due to various reasons (for example, multiple threads processed by the device simultaneously, etc.), so that in order to accurately simulate the temperature drop or increase in a jump-like manner, which occurs in the working process of the memory unit, the temperature jump environment of the memory unit may be determined according to the limit temperature corresponding to at least one jump temperature range.
And step 240, controlling the storage unit to execute target operation based on the jump environments in the first simulation environment to obtain a first test result.
The specific step descriptions of step 210 and step 240 may refer to step 110 and step 130, and will not be described herein.
In this embodiment, at least one jump temperature range is determined according to the acquired multiple temperature ranges, so that a temperature jump environment of the memory cell can be determined according to a limit temperature corresponding to the at least one jump temperature range, and at least one jump voltage range is determined according to the acquired multiple voltage ranges, so that a voltage jump environment of the memory cell can be determined according to a limit voltage corresponding to the at least one jump voltage range, and further the memory cell can be tested in the voltage jump environment and/or the temperature jump environment, so that the situation of using the memory cell in the limit environment is simulated, and the accuracy of the memory cell is further ensured.
Referring to fig. 3, fig. 3 illustrates a method for testing a memory cell according to an embodiment of the application. The following details about the flow shown in fig. 3, the method for testing the storage unit may specifically include the following steps:
Step 310, a plurality of target operating parameter ranges are obtained.
The specific step description of step 310 may refer to step 110, and will not be described herein.
Step 320, determining a plurality of polling test voltages according to the plurality of voltage ranges, and determining a plurality of polling test temperatures according to the plurality of temperature ranges.
As one way, to further ensure the availability of the storage unit, it is also possible to determine whether the storage unit can operate normally by simulating the environment in which the storage unit operates normally under the target operating parameter range. Alternatively, the memory cell may perform the corresponding target operation only within the rated voltage or the rated range, and thus the stepped polling test voltage may be determined according to a plurality of voltage ranges of the memory cell, so that the memory cell may be tested according to a plurality of polling test voltages, or the stepped polling test temperature may be determined according to a plurality of temperature ranges of the memory cell, so that the memory cell may be tested according to a plurality of polling test temperatures.
Optionally, the multiple polling test voltages/multiple polling test temperatures may be an arithmetic series, or an arithmetic series, and the appropriate voltage value/temperature value may be selected according to the multiple voltage ranges/multiple temperature ranges, so that the obtained multiple voltage values/temperature values form the arithmetic series or the arithmetic series, so as to obtain multiple polling test voltages/temperatures.
And 330, sequentially performing voltage test on the memory cells according to the polling test voltages to obtain a voltage test result.
As one way, after obtaining the plurality of polling test voltages, the operating voltage of the memory cell may be set according to the plurality of polling test voltages, so that the memory cell performs the target operation under the corresponding plurality of polling test voltages, thereby implementing the voltage test on the memory cell.
Optionally, the voltage test result includes that the memory cell can normally perform the target operation under a plurality of polling test voltages and the memory cell cannot normally perform the target operation under some polling test voltages. Optionally, in order to further ensure the accuracy of the voltage test of the storage power supply, when it is determined that the storage unit can normally execute the target operation under the multiple polling test voltages, it is determined whether the data written by the storage power supply under the same polling test voltage is the same as the read data, if so, the storage unit is determined to pass the voltage test, and if not, the storage unit is determined to not pass the voltage test.
And 340, sequentially performing temperature test on the storage units according to the plurality of polling test temperatures to obtain a temperature test result.
As a way, after obtaining the plurality of polling test temperatures, the working temperature of the storage unit may be set according to the plurality of polling test temperatures, so that the storage unit performs the target operation at the corresponding plurality of polling test temperatures, thereby implementing the temperature test on the storage unit.
Optionally, the temperature test result includes that the memory unit can normally execute the target operation at a plurality of polling test temperatures and that the memory unit cannot normally execute the target operation at some polling test temperatures. Optionally, in order to further ensure the accuracy of the temperature test of the storage power supply, when it is determined that the storage unit can normally execute the target operation at a plurality of polling test temperatures, it is determined whether the data written by the storage power supply at the same polling test temperature is the same as the read data, if so, the storage unit is determined to pass the temperature test, and if not, the storage unit is determined to not pass the temperature test.
In this embodiment, a plurality of polling test voltages are determined according to a plurality of voltage ranges and a plurality of polling test temperatures are determined according to a plurality of temperature ranges, so that voltage test can be performed on the memory unit according to the plurality of polling test voltages, and temperature test can be performed on the memory unit according to the plurality of polling test temperatures, so that the memory unit can be ensured to simulate working in a stepped environment, the test environment is enriched, and the test accuracy of the memory unit is further improved.
Referring to fig. 4, fig. 4 shows a method for testing a memory cell according to an embodiment of the application. The following details about the flow shown in fig. 4, the method for testing the storage unit may specifically include the following steps:
step 410, a plurality of target operating parameter ranges are obtained.
The specific step description of step 410 may refer to step 110, and will not be described herein.
And step 420, determining a second simulation environment according to the plurality of temperature ranges and the plurality of voltage ranges, wherein the second simulation environment is used for simulating the environment of the memory unit for executing the first target operation and the second target operation under different conditions.
As one way, in order to ensure that the memory cell can continue to operate normally when the user uses the memory cell normally, after the plurality of temperature ranges and the plurality of voltage ranges are acquired, a second simulation environment that can simulate when the voltage and the temperature of the memory cell change continuously when the user uses the memory cell can be determined according to the plurality of temperature ranges and the plurality of voltage ranges.
Alternatively, the memory cell may be tested in a second simulation environment by performing different operations under different temperature conditions and different voltage conditions to achieve the first target operation and the second target operation performed under different conditions. Optionally, the first target operation and the second target operation complete the formation storage unit to complete continuous read-write operation.
And step 430, testing the storage unit in the second simulation environment to obtain a second test result.
As one way, when the second simulation environment is determined, the first target operation is performed at the first temperature and the second voltage in the second simulation environment, and the second target operation is performed at the second temperature and the second voltage in the second simulation environment, thereby realizing the test of the memory cell in the second simulation environment.
Optionally, the second test result includes the storage unit being capable of performing the first target operation and the second target operation under different conditions in the second environment and the storage unit being incapable of performing the first target operation and/or the second target operation under different conditions in the second environment.
In some embodiments, as shown in fig. 5, the step 430 includes:
Step 431, determining a first condition environment based on the second simulation environment, and controlling the storage unit to execute a first target operation in the first condition environment to obtain target data.
As one way, to ensure that the second test result can be accurately obtained, the first condition environment may be determined according to the second simulation environment, where the first condition environment may be a low temperature and low voltage environment determined based on the plurality of temperature ranges and the plurality of voltage ranges, so as to control the memory cell to perform the first target operation in the low temperature and low voltage environment. Alternatively, the low temperature and low voltage environment may refer to an environment in which the temperature and voltage values corresponding to the temperature and voltage ranges supporting the normal operation of the memory device are small.
Alternatively, the first target operation may be a read operation or a write operation, and the first target operation may be set according to actual needs. The corresponding data can be obtained after the corresponding operation is executed by the storage unit whether the read operation or the write operation is executed.
Step 432, determining a second condition environment based on the second simulation environment, and controlling the storage unit to execute a second target operation in the second condition environment to obtain reference data, where the first condition environment is different from a temperature range and/or a voltage range corresponding to the first condition environment.
As one way, in order to be able to accurately simulate the situation in which the environment in which the storage device is located is changed by the user during the use of the storage unit, a second conditional environment different from the first conditional environment may be determined by a second simulation environment, which may be a high temperature and high voltage environment determined based on a plurality of temperature ranges and a plurality of voltage ranges, thereby being able to control the storage unit to perform a second target operation in the high temperature and high voltage environment. Alternatively, the high temperature and high voltage environment may refer to an environment in which a temperature value and a voltage value corresponding to a temperature range and a voltage range supporting normal operation of the storage device are large, and a temperature range and/or a voltage range corresponding to the second condition environment is different from the first condition environment.
Optionally, the second target operation is a different target operation than the first target operation, and if the first target operation is a read operation, the second target operation is a write operation, and if the first target operation is a write operation, the second target operation is a read operation. The sequence of executing the first target operation and the second target operation is related to the types of the target operations, namely writing is performed before reading, and is irrelevant to the first condition environment and the second condition environment, and the first target operation and the second target operation form complete read-write operation of the storage unit, so that the testing accuracy of the storage unit is ensured.
In other embodiments, the first target operation may be controlled to be executed by the storage unit under the second condition environment and the second target operation may be controlled to be executed by the storage unit under the first condition environment, so that the first target operation and the second target operation are ensured to be completed under different condition environments, thereby ensuring the testing accuracy of the storage unit.
And 433, determining the second test result according to the target data and the reference data.
In order to test whether the memory unit can normally work in the simulated second simulation environment, the second test result of the memory unit can be determined by comparing the target data after the first target operation is executed with the reference data after the second target operation is executed, and whether the memory unit can execute the corresponding target operation under different conditions in the second simulation environment can be further determined according to the second test result.
In some embodiments, the step 433 includes determining whether the target data is the same as the reference data, if so, determining that the second test result indicates that the memory cell passed the test, and if not, determining that the second test result indicates that the memory cell failed the test.
As one way, to determine the second test result of the memory cell, the second test result may be determined by comparing the data written by the memory cell in the second simulation environment with the data read in the second simulation environment, thereby determining whether the target data is identical to the reference data.
Optionally, if the target data and the reference data are different, it is determined that the memory cell fails in the process of performing the read operation in the second environment, so that the read data is different from the written data, and it may be determined that the memory cell fails the test. If the target data and the reference data are the same, determining that the storage unit has no fault in the process of executing the writing operation and the reading operation in the second environment, so that the read data are the same as the written data, and determining that the storage unit passes the test.
In this embodiment, the second simulation environment is determined according to the plurality of temperature ranges and the plurality of voltage ranges, so that the situation that the environment of the simulation storage unit continuously changes in the actual use process can be realized by controlling the storage unit to execute the first target operation under the first condition environment of the second simulation environment and controlling the storage unit to execute the second target operation under the second condition environment, the testing environment is enriched, and the testing accuracy of the storage unit is further improved.
Referring to fig. 6, fig. 6 shows a method for testing a memory cell according to an embodiment of the application. The following details about the flow shown in fig. 6, the method for testing the storage unit may specifically include the following steps:
If it is determined that the storage unit fails the test, a target simulation environment of the storage unit that fails the test is determined, step 510.
In one mode, when the storage unit is determined to not pass the test, the storage unit can be determined to fail in the practical application process, and in order to ensure the practicability of the subsequent storage unit, the target simulation environment of the storage unit, which specifically fails the test, is determined when the storage unit is determined to not pass the test, so that the storage unit can be improved based on the target simulation environment. Alternatively, the target simulation environment may specifically include a voltage environment and/or a temperature environment where the memory cell fails the test.
And step 520, generating prompt information according to the target simulation environment, and carrying out design prompt on the storage unit based on the prompt information.
As one way, after the target simulation environment is determined, a hint may be generated based on the specific voltage value and/or temperature value, the voltage range, the temperature range, etc. corresponding to the target simulation environment, where the hint indicates that the memory cell fails the test at the specific temperature and/or voltage.
Optionally, the prompt information may further include a specific test result of the storage unit failing to pass the test, for example, if the storage unit fails to pass the test in the second simulation environment, the prompt information includes a specific fault type (such as a read fault, a write fault, a difference between the read data and the written data, and a failure of the storage unit to work normally) in addition to a specific voltage value and a specific temperature value, so that the prompt information can be generated in the test device communicatively connected with the storage unit, and a developer can further improve the storage unit by checking the prompt information in the test device.
In this embodiment, when it is determined that the storage unit fails the test, the target simulation environment of the storage unit that fails the test is determined, so that prompt information can be generated according to the target simulation environment, and design prompt is performed on the storage unit according to the prompt information, so that a developer can improve the storage unit based on the design prompt, and development efficiency of the storage unit is further improved.
Fig. 7 is a block diagram of a test apparatus for a memory cell according to an embodiment of the present application, and as shown in fig. 7, the test apparatus 600 for a memory cell includes an acquisition module 610, a first simulation environment determination module 620, and a first test module 630.
The device comprises an acquisition module 610, a first simulation environment determining module 620, a first test module 630 and a second test module, wherein the acquisition module 610 is used for acquiring a plurality of target working parameter temperature ranges, the first simulation environment determining module 620 is used for determining a first simulation environment according to the plurality of target working parameter ranges, the first simulation environment is used for simulating a plurality of jump environments for driving the storage unit, and the first test module 630 is used for controlling the storage unit to execute target operation based on the plurality of jump environments in the first simulation environment to obtain a first test result.
In some embodiments, the target operating parameter comprises a voltage and/or a temperature, the plurality of voltage ranges is determined by a rated voltage of the memory cell, and the plurality of temperature ranges is determined by a rated temperature of the memory cell.
In some embodiments, the first simulation environment determining module 620 includes a first determining sub-module configured to determine at least one transition temperature range according to the plurality of temperature ranges and at least one transition temperature range according to the plurality of voltage ranges, a second determining sub-module configured to determine a voltage transition environment of the memory cell according to a limit temperature corresponding to the at least one transition temperature range, and determine a temperature transition environment of the memory cell according to a limit voltage determined by the at least one transition voltage.
In some embodiments, the device 600 for testing a memory cell further includes a voltage/temperature determining module configured to determine a plurality of polling test voltages according to the plurality of voltage ranges and determine a plurality of polling test temperatures according to the plurality of temperature ranges, a voltage testing module configured to sequentially perform voltage testing on the memory cell according to the plurality of polling test voltages to obtain a voltage test result, and a temperature testing module configured to sequentially perform temperature testing on the memory cell according to the plurality of polling test temperatures to obtain a temperature test result.
In some embodiments, the device 600 for testing a memory cell further includes a second simulation environment determining module configured to determine a second simulation environment according to the plurality of temperature ranges and the plurality of voltage ranges, where the second simulation environment is configured to simulate the environment of the memory cell that performs the first target operation and the second target operation under different conditions, and a second testing module configured to test the memory cell in the second simulation environment to obtain a second test result.
In some embodiments, the second test module comprises a first control sub-module, a second control sub-module and a test result determination sub-module, wherein the first control sub-module is used for determining a first condition environment based on the second simulation environment and controlling the storage unit to execute a first target operation in the first condition environment to obtain target data, the second control sub-module is used for determining a second condition environment based on the second simulation environment and controlling the storage unit to execute a second target operation in the second condition environment to obtain reference data, the temperature range and/or the voltage range corresponding to the first condition environment are different from each other, and the test result determination sub-module is used for determining the second test result according to the target data and the reference data.
In some embodiments, the test result determining submodule comprises a judging unit, a first determining unit and a second determining unit, wherein the judging unit is used for determining whether the target data and the reference data are identical, the first determining unit is used for determining that the second test result indicates that the storage unit passes the test if the target data and the reference data are identical, and the second determining unit is used for determining that the second test result indicates that the storage unit fails the test if the target data and the reference data are not identical.
In some embodiments, the device 600 for testing a storage unit further includes a target simulation environment determining module configured to determine a target simulation environment of the storage unit that fails the test if it is determined that the storage unit fails the test, and a prompting module configured to generate prompting information according to the target simulation environment and perform design prompting on the storage unit based on the prompting information.
According to an aspect of the embodiment of the present application, there is further provided an electronic device, as shown in fig. 8, where the electronic device 700 includes a processor 710 and one or more memories 720, and the one or more memories 720 are used to store program instructions executed by the processor 710, and the processor 710 executes the program instructions to implement the method for testing the storage unit.
Further, the processor 710 may include one or more processing cores. Processor 710 executes or performs instructions, programs, code sets, or instruction sets stored in memory 720 and invokes data stored in memory 720. Alternatively, the processor 710 may be implemented in hardware in at least one of digital signal Processing (DIGITAL SIGNAL Processing, DSP), field-Programmable gate array (Field-Programmable GATE ARRAY, FPGA), programmable logic array (Programmable Logic Array, PLA). The processor 710 may integrate one or a combination of several of a central processing unit (Central Processing Unit, CPU), an image processor (Graphics Processing Unit, GPU), and a modem, etc. The CPU mainly processes an operating system, a user interface, an application program and the like, the GPU is used for rendering and drawing display contents, and the modem is used for processing wireless communication. It will be appreciated that the modem may not be integrated into the processor and may be implemented solely by a single communication chip.
According to an aspect of the present application, there is also provided a computer-readable storage medium that may be included in the electronic device described in the above embodiment, or may exist alone without being incorporated into the electronic device. The computer readable storage medium carries computer readable instructions which, when executed by a processor, implement the method of any of the above embodiments.
It should be noted that, the computer readable medium shown in the embodiments of the present application may be a computer readable signal medium or a computer readable storage medium, or any combination of the two. The computer readable storage medium can be, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or a combination of any of the foregoing. More specific examples of a computer-readable storage medium may include, but are not limited to, an electrical connection having one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-Only Memory (ROM), an erasable programmable read-Only Memory (Erasable Programmable Read Only Memory, EPROM), a flash Memory, an optical fiber, a portable compact disc read-Only Memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing. In the context of this document, a computer readable storage medium may be any tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device. In the present application, however, the computer-readable signal medium may include a data signal propagated in baseband or as part of a carrier wave, with the computer-readable program code embodied therein. Such a propagated data signal may take any of a variety of forms, including, but not limited to, electro-magnetic, optical, or any suitable combination of the foregoing. A computer readable signal medium may also be any computer readable medium that is not a computer readable storage medium and that can communicate, propagate, or transport a program for use by or in connection with an instruction execution system, apparatus, or device. Program code embodied on a computer readable medium may be transmitted using any appropriate medium, including but not limited to wireless, wireline, etc., or any suitable combination of the foregoing.
The units involved in the embodiments of the present application may be implemented by software, or may be implemented by hardware, and the described units may also be provided in a processor. Wherein the names of the units do not constitute a limitation of the units themselves in some cases.
The foregoing description of the invention has been presented for purposes of illustration and description, and is not intended to be limiting. Several simple deductions, modifications or substitutions may also be made by a person skilled in the art to which the invention pertains, based on the idea of the invention.
Claims (10)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202510479804.2A CN120452516A (en) | 2025-04-16 | 2025-04-16 | Method and device for testing storage unit and storage medium thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202510479804.2A CN120452516A (en) | 2025-04-16 | 2025-04-16 | Method and device for testing storage unit and storage medium thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN120452516A true CN120452516A (en) | 2025-08-08 |
Family
ID=96610103
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202510479804.2A Pending CN120452516A (en) | 2025-04-16 | 2025-04-16 | Method and device for testing storage unit and storage medium thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN120452516A (en) |
-
2025
- 2025-04-16 CN CN202510479804.2A patent/CN120452516A/en active Pending
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN108073519B (en) | Test case generation method and device | |
| US9990458B2 (en) | Generic design rule checking (DRC) test case extraction | |
| US11003817B2 (en) | Hard error simulation and usage thereof | |
| TW202326503A (en) | Chip design verification system, chip design verification method, and computer readable recording media with stored programs | |
| US8868976B2 (en) | System-level testcase generation | |
| US20130013246A1 (en) | Method and apparatus for post-silicon testing | |
| CN112731117A (en) | Automatic verification method and system for chip, and storage medium | |
| CN113760751A (en) | Method for generating test case, electronic device and storage medium | |
| CN115599618B (en) | Register dynamic change-allocation verification method and device, storage medium and processor | |
| US20130311164A1 (en) | Dynamic generation of test segments | |
| CN112035341A (en) | Automatic testing method and device | |
| US9501390B1 (en) | Enhancing automated mobile application testing | |
| CN105183641A (en) | Data consistency check method and system for kernel module | |
| EP3553681B1 (en) | Method and apparatus for error test coverage determination for a circuit by simulation | |
| CN112380127A (en) | Test case regression method, device, equipment and storage medium | |
| CN120452516A (en) | Method and device for testing storage unit and storage medium thereof | |
| US10503854B1 (en) | Method and system for generating validation tests | |
| CN115757099B (en) | Automatic testing method and device for platform firmware protection and recovery function | |
| US9852259B2 (en) | Area and/or power optimization through post-layout modification of integrated circuit (IC) design blocks | |
| KR102216281B1 (en) | Method and apparatus for detecting depth learning chip, electronic device and computer storage medium | |
| CN115563930A (en) | Automatic verification method and device based on storage model, terminal and storage medium | |
| CN104915352B (en) | A kind of method and apparatus that data correctness is handled under verification MapReduce environment | |
| US10540461B1 (en) | Method and system for functional safety verification | |
| US8527923B1 (en) | System, method, and computer program product for hierarchical formal hardware verification of floating-point division and/or square root algorithmic designs using automatic sequential equivalence checking | |
| US20130262932A1 (en) | Stream Generation |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |