CN120375899A

CN120375899A - Decoding method and storage device

Info

Publication number: CN120375899A
Application number: CN202510557918.4A
Authority: CN
Inventors: 陈昭佑; 吴宗霖
Original assignee: Hosin Global Electronics Co Ltd
Current assignee: Hosin Global Electronics Co Ltd
Priority date: 2025-04-29
Filing date: 2025-04-29
Publication date: 2025-07-25

Abstract

The invention provides a decoding method and a storage device. The method includes the steps of responding to a reading instruction of reading first data from the memory module, reading the first data and a first error correction code corresponding to a first logic unit, determining first sub-data from the first data, executing first data detection operation on the first sub-data according to preset bit information so as to correct errors in the first sub-data, and executing decoding operation on the first data according to the first error correction code after executing the first data detection operation on the first sub-data. Therefore, the decoding capability of the storage device can be effectively improved without obviously improving (even reducing) the overall operation load.

Description

Decoding method and storage device

Technical Field

The present invention relates to the field of storage technologies, and in particular, to a decoding method and a storage device.

Background

In solid State Storage Devices (SSDs), due to their internal flash technology based nature, data is subject to various types of errors, particularly bit-flip errors, during storage, which requires that the SSD controller must integrate Error Checking and Correction (ECC) circuitry to ensure data integrity.

In a Solid State Disk (SSD), error checking and correction (Error Correction Code, ECC) circuitry is a critical component for detecting and correcting bit errors occurring within a memory cell. ECC maintains the integrity and reliability of data by adding redundant information to the original data so that the SSD controller can detect and repair a certain number of bit errors when reading the data. Although ECC can significantly improve data reliability, its correction capability is limited, i.e., ECC can only correct the number of erroneous bits within a certain range. If an error occurring in a block exceeds the maximum error rate tolerated by the ECC algorithm (commonly referred to as the "erasure capability" of the erasure code), then even if an ECC mechanism exists, the data of that block cannot be recovered, which can result in the loss of data irrecoverability.

In view of this, how to effectively manage NAND flash memory has become one of the core issues of current industry engineers.

Disclosure of Invention

The invention provides a decoding method and a storage device, which can improve the decoding efficiency of the storage device.

An embodiment of the present invention provides a decoding method for a storage device, wherein the storage device includes a memory module, and the decoding method includes reading first data corresponding to a first logic unit and a first error correction code in response to a read instruction for reading the first data from the memory module, determining first sub-data from the first data, performing a first data detection operation on the first sub-data according to preset bit information to correct an error in the first sub-data, and performing a decoding operation on the first data according to the first error correction code after performing the first data detection operation on the first sub-data.

The embodiment of the invention further provides a storage device, which comprises a connection interface, a memory module and a memory controller. The memory controller is connected to the connection interface and the memory module. The memory controller is used for responding to a reading instruction of reading first data from the memory module, reading the first data and a first error correction code corresponding to a first logic unit, determining first sub-data from the first data, executing first data detection operation on the first sub-data according to preset bit information so as to correct errors in the first sub-data, and executing decoding operation on the first data according to the first error correction code after executing the first data detection operation on the first sub-data.

Based on the above, in response to a read instruction for reading the first data, the first data and the first error correction code corresponding to the first logic unit may be read, and the first sub-data may be determined from the first data. According to the preset bit information, a first data detection operation can be performed on the first sub-data first to correct errors in the first sub-data. After the first data detection operation is performed on the first sub-data, a decoding operation may be further performed on the first data according to the first error correction code. Therefore, the decoding capability of the storage device can be effectively improved without obviously improving (even reducing) the overall operation load.

Drawings

FIG. 1 is a schematic diagram of a data storage system shown in accordance with an embodiment of the present invention;

FIG. 2 is a schematic diagram of a memory controller shown according to an embodiment of the present invention;

FIG. 3 is a schematic diagram of a managed memory module shown in accordance with an embodiment of the present invention;

FIG. 4 is a schematic diagram of a variable sampling window and a target bit interval according to an embodiment of the present invention;

FIG. 5 is a schematic diagram of a first data detection operation shown in accordance with an embodiment of the present invention;

FIG. 6 is a schematic diagram of an operational scenario of a decoding method shown according to an embodiment of the present invention;

Fig. 7 is a flowchart of a decoding method according to an embodiment of the present invention.

Detailed Description

Reference will now be made in detail to the exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings and the description to refer to the same or like parts.

FIG. 1 is a schematic diagram of a data storage system shown in accordance with an embodiment of the present invention. Referring to fig. 1, a data storage system 10 includes a host system 11 and a storage device 12. The storage device 12 may be connected to the host system 11 and may be used to store data from the host system 11. For example, the host system 11 may be a smart phone, a tablet computer, a notebook computer, a desktop computer, an industrial computer, a game machine, a server, or a computer system provided in a specific carrier (e.g., a vehicle, an aircraft, or a ship), or the like, and the type of the host system 11 is not limited thereto. Further, the storage device 12 may include a solid state disk, a USB flash drive, a memory card, or other type of non-volatile storage device.

The memory device 12 includes a connection interface 121, a memory module 122, and a memory controller 123. The connection interface 121 is used to connect the storage device 12 to the host system 11. For example, connection interface 121 may support an embedded multimedia card (embedded Multi-MEDIA CARD, EMMC), universal flash memory (Universal Flash Storage, UFS), peripheral component interconnect Express (PERIPHERAL COMPONENT INTERCONNECT EXPRESS, PCI Express), non-volatile memory Express (Non-Volatile Memory Express, NVM Express), serial advanced technology attachment (SERIAL ADVANCED Technology Attachment, SATA), universal serial bus (Universal Serial Bus, USB), or other types of connection interface standards. Accordingly, storage device 12 may communicate (e.g., exchange signals, instructions, and/or data) with host system 11 via connection interface 121.

The memory module 122 is used for storing data. For example, the memory module 122 may include one or more rewritable non-volatile memory modules. Each of the rewritable non-volatile memory modules may include one or more memory cell arrays. Memory cells in a memory cell array store data in the form of voltages (also referred to as threshold voltages). For example, the memory module 122 may include a single level memory cell (SINGLE LEVEL CELL, SLC) NAND-type flash memory module, a second level memory cell (Multi LEVEL CELL, MLC) NAND-type flash memory module, a third level memory cell (TRIPLE LEVEL CELL, TLC) NAND-type flash memory module, a fourth level memory cell (Quad LEVEL CELL, QLC) NAND-type flash memory module, and/or other memory modules having the same or similar characteristics.

The memory controller 123 is connected to the connection interface 121 and the memory module 122. Memory controller 123 may be considered a control core of storage device 12 and may be used to control storage device 12. For example, the memory controller 123 may be used to control or manage the operation of the storage device 12 in whole or in part. For example, the memory controller 123 may include a central processing unit (CentralProcessing Unit, CPU), or other programmable general purpose or special purpose microprocessor, digital signal Processor (DIGITAL SIGNAL Processor, DSP), programmable controller, application SPECIFIC INTEGRATED Circuits (ASIC), programmable logic device (Programmable Logic Device, PLD), or other similar device or combination of devices. In an embodiment, the memory controller 123 may comprise a flash memory controller.

Memory controller 123 may send a sequence of instructions to memory module 122 to access memory module 122. For example, memory controller 123 may send a sequence of write instructions to memory module 122 to instruct memory module 122 to store data in a particular memory location. For example, memory controller 123 can send a sequence of read instructions to memory module 122 to instruct memory module 122 to read data from a particular memory location. For example, memory controller 123 can send a sequence of erase instructions to memory module 122 to instruct memory module 122 to erase data stored in a particular memory cell. In addition, memory controller 123 may send other types of instruction sequences to memory module 122 to instruct memory module 122 to perform other types of operations, as the invention is not limited. The memory module 122 may receive a sequence of instructions from the memory controller 123 and access memory locations within the memory module 122 according to the sequence of instructions.

FIG. 2 is a schematic diagram of a memory controller according to an embodiment of the invention. Referring to fig. 1 and 2, the memory controller 123 includes a host interface 21, a memory interface 22, and a memory control circuit 23. The host interface 21 is used to connect to the host system 11 through the connection interface 121 to communicate with the host system 11. The memory interface 22 is used to connect to the memory module 122 to access the memory module 122.

The memory control circuit 23 is connected to the host interface 21 and the memory interface 22. The memory control circuit 23 may be used to control or manage the operation of the memory controller 123 in whole or in part. For example, the memory control circuit 23 may communicate with the host system 11 through the host interface 21 and access the memory module 122 through the memory interface 22. For example, the memory control circuit 23 may include a control circuit such as an embedded controller or a microcontroller. In the following embodiment, the explanation of the memory control circuit 23 is equivalent to the explanation of the memory controller 123.

In one embodiment, memory controller 123 may also include buffer memory 24. The buffer memory 24 is connected to the memory control circuit 23 and is used for buffering data. For example, buffer memory 24 may be used to buffer instructions from host system 11, data from host system 11, and/or data from memory module 122.

In an embodiment, memory controller 123 may also include error correction circuitry 25. The error correction circuit 25 is connected to the memory control circuit 23 and performs encoding and decoding of data to ensure the correctness of the data. For example, the error correction circuit 25 may support various coding/decoding algorithms such as Low DENSITY PARITY CHECK codes (LDPC codes), BCH codes, reed-solomon codes (RS codes), and Exclusive OR (XOR) codes. In one embodiment, the memory controller 123 may also include various circuit modules of other types (e.g., power management circuits, etc.), which are not limiting.

FIG. 3 is a schematic diagram illustrating managing memory modules according to an embodiment of the invention. Referring to fig. 1 to 3, the memory module 122 includes a plurality of physical units 301 (1) to 301 (B). Each physical unit comprises a plurality of memory cells and is used for nonvolatile memory data.

In one embodiment, a physical unit may include a physical programming unit. In one embodiment, a physical programmer may include a plurality of physical sectors (sectors). For example, a physical sector may have a data size of 512 Bytes (Bytes), and a physical programming unit may include 32 physical sectors. However, the data capacity of one physical fan and/or the total number of physical fans included in one physical programming unit can be adjusted according to the practical requirements, and the present invention is not limited thereto. In one embodiment, a physical programmer may be considered a physical page. For example, the storage capacity of one physical programming unit may be 16 kilobytes, and the present invention is not limited thereto.

In one embodiment, one physical programmer is the minimum unit of synchronous write data in the memory module 122. For example, when performing a programming operation (also referred to as a write operation) on a physical programming unit to write data into the physical programming unit, a plurality of memory cells in the physical programming unit may be synchronously programmed to store corresponding data. For example, when programming a physical programming unit, a write voltage may be applied to the physical programming unit to change the threshold voltage of at least some of the memory cells in the physical programming unit. For example, the threshold voltage of a memory cell may reflect the bit data stored by the memory cell.

In one embodiment, a physical erase unit may include a plurality of physical program units. Multiple physical program units in a physical erase unit can be erased simultaneously. For example, when performing an erase operation on a physically erased cell, an erase voltage may be applied to a plurality of physically programmed cells in the physically erased cell to change the threshold voltage of at least some of the physically programmed cells. By performing an erase operation on a physically erased cell, data stored in the physically erased cell may be erased. In one embodiment, a physical erased cell may be considered a physical block.

In one embodiment, the memory control circuit 23 can logically associate the physical units 301 (1) to 301 (A) and 301 (A+1) to 301 (B) to the data area 31 and the idle area 32, respectively. The physical units 301 (1) -301 (a) in the data area 31 all store data (also referred to as user data) from the host system 11. For example, any entity in the data area 31 may store valid (valid) data and/or invalid (invalid) data. In addition, none of the physical units 301 (a+1) -301 (B) in the spare area 32 stores data (e.g., valid data).

In one embodiment, if a certain physical unit does not store valid data, the physical unit may be associated with the idle area 32. In addition, the physical cells in the spare area 32 may be erased to erase the data in the physical cells. In one embodiment, the physical units in the idle region 32 are also referred to as idle physical units. In one embodiment, the free area 32 is also referred to as a free pool (free pool).

In one embodiment, when data is to be stored, the memory control circuit 23 may select one or more physical units from the idle area 32 and instruct the memory module 122 to store the data in the selected physical units. After storing the data in the physical unit, the physical unit may be associated with the data area 31. In other words, one or more physical units may be used alternately between the data area 31 and the idle area 32.

In one embodiment, the memory control circuit 23 may configure a plurality of logic units 302 (1) -302 (C) to map physical units (i.e., physical units 301 (1) -301 (A)) in the data area 31. For example, a logical unit may correspond to a logical block address (Logical Block Address, LBA) or other logical management unit. One logical unit may be mapped to one or more physical units.

In one embodiment, if a physical unit is currently mapped by any logical unit, the memory control circuit 23 may determine that the data currently stored in the physical unit includes valid data. Conversely, if a physical unit is not currently mapped by any logical unit, the memory control circuit 23 may determine that the physical unit does not currently store any valid data.

In one embodiment, the memory control circuit 23 may record the mapping relationship between the logical unit and the physical unit in at least one management table (also referred to as a logical-to-physical mapping table). In one embodiment, the memory control circuit 23 instructs the memory module 122 to perform data reading, writing or erasing operations according to the information in the management table (i.e. the logical-to-physical mapping table).

In one embodiment, the memory control circuit 23 may retrieve the read instruction from the host system 11. The read instruction is used to instruct the reading of data (also referred to as first data) from the memory module 122. For example, the read instruction may carry an instruction code indicating the logical unit to which the read first data belongs (also referred to as the first logical unit). For example, the first logic unit may include at least one of the logic units 302 (1) -302 (C) of FIG. 3.

In one embodiment, in response to the read instruction, the memory control circuit 23 may read the first data corresponding to the first logic unit and an error correction code (also referred to as a first error correction code) corresponding to the first data from the memory module 122. For example, the first error correction code may be used to correct errors (also referred to as error bits) in the first data.

Specifically, the first data may include data (e.g., user data) from the host system 11, program code (also referred to as firmware code) for running the storage device 12, and/or data (also referred to as system data) for managing the storage device 12. User data refers to data to be saved by a user, such as documents, images, video files, and the like. Further, the program code for operating the storage device 12 may include firmware code.

In one embodiment, the system data includes one or more types of management data for a file system (FILE SYSTEM) of the storage device 12. For example, the system data may include management data for various file systems such as FAT32、exFAT(Extended File Allocation Table)、NTFS、ext4、F2FS(Flash-Friendly File System)、YAFFS、APFS(Apple File System)、Btrfs or ZFS. The system data is critical to managing and maintaining the file system of the storage device 12 and its structure. Different types of storage devices 12 may use different file systems and the data structures within the different types of file systems may also be different.

FAT32 is the most common file system for early U-discs. The USB flash disk has wide compatibility, and almost all operating systems can read and write the USB flash disk in the FAT32 format. But FAT32 has a single file size that cannot exceed the limit of 4 GB. exFAT is developed by Microsoft to address the limitations of FAT32, particularly the problem of large file support. The exFAT supports larger files, has good support in Windows and MAC OS, and is gradually becoming a new standard for U disk. NTFS is mainly used in Windows operating systems, and although some usb discs may use NTFS, its cross-platform compatibility is not as good as FAT32 or exFAT. ext4 is common to eMMC storage in Android devices. ext4 is a journaling file system that provides better data integrity and recovery capabilities and is widely used in Linux systems. F2FS is a file system optimized for flash memory, which is mainly used for Android devices to improve performance and extend flash memory life. YAFFS was once used as a file system for embedded systems, especially on early kernel versions of Android devices. Btrfs is an advanced file system designed for Linux that supports copy, snapshot, check, etc. functions, which, while still under development, have been adopted in some scenarios. ZFS is another advanced file system, originally developed by Sun Microsystems, and is now found in many systems, which provide data redundancy, compression, snapshot, etc. functions, which are well suited to the data center environment.

Wherein, the above products share some file systems as follows:

FAT32 and exFAT-these two file systems are commonly used for various types of removable storage devices, including U-discs, SSDs (when acting as external drives), because of their broad compatibility. ext4 although mainly used in Linux operating systems, it can be found on a variety of storage media, such as eMMC, UFS and SSD, especially in Android devices and Linux servers. F2FS, which is mainly used for eMMC and UFS storage on mobile equipment to adapt to the characteristics and requirements of flash memory.

In one embodiment, the system data includes file allocation table (File Allocation Table, FAT) data. In the storage area, FAT data is part of a file system. When writing FAT data to the memory module 122, the FAT data exhibits different characteristics than the user data is written. These differences are mainly reflected in the distribution characteristics of the data and the distribution requirements for "1" and "0".

FAT data is structured metadata used to record allocation of files in a file system. Each FAT Entry (Entry, typically 16 or 32 bits) indicates the location of the next Cluster of a Cluster (Cluster) of a file or marks whether the Cluster is unused. Unused clusters are typically marked with a particular value (e.g., all "0"), while clusters assigned to a file contain an address pointing to the next cluster in the chain. Such structured data typically has a high regularity, i.e. the distribution of "1" and "0" in the FAT data follows a certain rule. For example, unused cluster items are all "0" s, while items pointing to other clusters exhibit mixed "1" and "0" s.

On the other hand, the user data is typically unstructured and may be any form of data including text, images, video, etc. The distribution of user data is typically random. In effect, to reduce the risk of bit flip errors, the user data is randomized prior to being written to the memory module 122. For example, the most effective randomization may be selected for writing to the memory module 122. Thus, in user data, the state of each bit (bit) ("1" or "0") has no apparent regularity.

In one embodiment, for the FAT32 file system, taking an 8GB size usb disk as an example, the maximum possible value of the number of bytes occupied by the FAT data (i.e., the size of a single FAT data table) is calculated as follows:

The FAT data size of the FAT32 file system depends on the total number of clusters and the size of each FAT entry. For FAT32, each FAT entry occupies 4 bytes (32 bits), because FAT32 is able to manage larger disk space and more clusters.

To calculate the maximum capacity of FAT data on an 8GB U disk, assume that the maximum volume size supported by FAT32 is 2TB. The cluster size in FAT32 is typically between 512 bytes and 32KB, depending on the total size of the volume. For an 8GB U disk, the common cluster size is 4KB (4096 bytes). For an 8GB USB flash disk, assuming a cluster size of 4KB (4096 bytes) and each FAT entry occupies 4 bytes, the FAT data size can be calculated as follows:

2097152×4 (bytes) = 8388608 bytes=8 MB

Further, the maximum possible value of the number of bytes occupied by the FAT data (i.e., the size of a single FAT data) may be represented in hexadecimal as follows:

2X 1024 cluster=0x 0020000

Or may be converted to a binary representation as follows:

0000 0000 0010 0000 0000 0000 0000 0000

As above, if a piece of FAT data is represented in binary, the first 10 bits in the FAT data can be considered as part of the data having the structured feature (i.e., 10 "0" s in succession), while the remaining bits in the FAT data do not have the structured feature. However, other types of management data may have structured features that each correspond to and/or differ in morphology, and the invention is not limited.

For example, in the exFAT file system, the management data with structured features may include FAT data and Cluster Bitmap (Cluster Bitmap) data. This FAT data is used to track the allocation status of the cluster. In addition, cluster bit map data is used to record which clusters have been used and/or which clusters are free. Or in the ext4 file system, the management data having the structured feature may include Block Bitmap (Block Bitmap) data. The block bitmap data is used to track whether blocks on the disk are allocated. Alternatively, in the F2FS file system, the management data with the structured feature may include management data for Node Segment (Node Segment) data and data Segment (DATA SEGMENT) that are used to manage allocation of metadata and user data, and this mechanism helps to improve read-write efficiency and reduce fragmentation. Or in an XFS file system, the management data with structured features may include allocation group (Allocation Groups) data, which contains metadata, such as space allocation data, that provides a more flexible way to manage and recover file allocation information. In addition, many other types of management data may have the foregoing or similar structural features, which are described in detail herein.

In an embodiment, after the first data is read from the memory module 122, the memory control circuit 23 may determine specific data (also referred to as first sub-data) from the first data. For example, the first sub data includes a portion of the first data, and the data amount of the first sub data is less than the total data amount of the first data.

In an embodiment, the first sub-data is data having a structured feature in the first data. The structured feature may be a sequence of bits distributed according to a particular law (e.g., "0" and/or "1" distributed according to a particular law). For example, part-type system data may have the aforementioned structured features.

In an embodiment, the memory control circuit 23 may determine the type of the first data. For example, the memory control circuit 23 may determine that the type of first data is data having a structured feature (e.g., one or more of the management data described previously) or data not having the structured feature (e.g., user data or firmware data).

In one embodiment, if the type of the first data is data having a structured feature, the memory control circuit 23 may further confirm the type of the first data. For example, the memory control circuit 23 may confirm which of the one or more management data belongs to the first data. For example, the memory control circuit 23 may confirm that the type of the first data is management data belonging to various file systems for FAT32, exFAT, NTFS, ext4, F2FS, YAFFS, APFS, btrfs, ZFS, or the like. In addition, the type of the data with the structural characteristics can be adjusted or expanded according to the practical requirements, and the invention is not limited.

In one embodiment, the memory control circuit 23 may determine a sampling window (also referred to as a variable sampling window) according to the type of the first data. The number of variable sampling windows may be one or more. The memory control circuit 23 may determine at least one bit interval (also referred to as a target bit interval) in the first data according to the variable sampling window. For example, a target bit interval may correspond to a variable sampling window. Then, the memory control circuit 23 may determine (all) bit data located within the target bit section of the first data as first sub data.

In one embodiment, if the type of the first data is a certain type (also referred to as a first type), the memory control circuit 23 may determine a certain sampling window (also referred to as a first candidate sampling window) as the variable sampling window. Or if the type of the first data is another type (also referred to as a second type), the memory control circuit 23 may determine another sampling window (also referred to as a second candidate sampling window) as the variable sampling window. It should be noted that, according to the first candidate sampling window, the bit interval (also referred to as a first target bit interval) determined by the memory control circuit 23 in the first data may be different from the bit interval (also referred to as a second target bit interval) determined in the first data according to the second candidate sampling window.

FIG. 4 is a schematic diagram of a variable sampling window and a target bit interval according to an embodiment of the present invention. Referring to fig. 4, in one embodiment, the first data includes data 41. Depending on the type of data 41, the memory control circuit 23 may determine the variable sampling window W (1). The variable sampling window W (1) corresponds to the bit interval R (1) in the data 41. Accordingly, the memory control circuit 23 can determine the sub data 401 located within the bit section R (1) of the data 41 as the first sub data.

In one embodiment, the first data includes data 42. Depending on the type of data 42, the memory control circuit 23 may determine a variable sampling window W (2). The variable sampling window W (2) corresponds to the bit interval R (2) in the data 42. Accordingly, the memory control circuit 23 may determine the sub-data 402 located within the bit section R (2) of the data 42 as the first sub-data.

In one embodiment, the first data includes data 43. Depending on the type of data 43, the memory control circuit 23 may determine a variable sampling window W (3). The variable sampling window W (3) corresponds to the bit interval R (3) in the data 43. Accordingly, the memory control circuit 23 can determine the sub data 403 located within the bit section R (3) of the data 43 as the first sub data.

In one embodiment, the first data includes data 44. Depending on the type of data 44, the memory control circuit 23 may determine the variable sampling windows W (4) and W (5). The variable sampling windows W (4) and W (5) correspond to bit intervals R (4) and R (5), respectively, in the data 44. Therefore, the memory control circuit 23 can determine the sub-data 404 and 405 respectively located in the bit intervals R (4) and R (5) in the data 42 as the first sub-data.

It should be noted that in the embodiment of fig. 4, the positions and/or coverage of the variable sampling windows W (i) and R (i) in the corresponding data can be adjusted according to the practical requirements. In the embodiment of fig. 4, i may be 1 to 5, but the present invention is not limited thereto. In addition, the number of the variable sampling windows W (i) and the number of R (i) can be adjusted according to the practical requirement.

In one embodiment, after the first data is read, the memory control circuit 23 may obtain the preset bit information corresponding to the first data. The preset bit information may reflect a preset data format of the first sub data. In an embodiment, the predetermined data format may be matched with the structured feature of the first sub-data. For example, the preset data format may reflect the structured characteristics of the first sub-data. For example, the predetermined data format may reflect that the structured feature of the first sub-data is a bit sequence distributed according to a particular rule (e.g. "0" and/or "1" distributed according to a particular rule).

In an embodiment, the memory control circuit 23 may determine the preset bit information according to the type of the first data. For example, if the type of the first data is a certain type (e.g., the first type), the memory control circuit 23 may determine a certain bit information (also referred to as a first candidate bit information) as the preset bit information. Or if the type of the first data is another type (e.g., a second type), the memory control circuit 23 may determine another bit information (also referred to as a second candidate bit information) as the preset bit information. It should be noted that the predetermined data format (also referred to as a first predetermined data format) reflected by the first candidate bit information may be different from the predetermined data format (also referred to as a second predetermined data format) reflected by the second candidate bit information.

In an embodiment, the first predetermined data format may reflect that the structural feature of the first sub-data is a bit sequence (also referred to as a first bit sequence) distributed according to a certain rule (also referred to as a first rule). The second predetermined data format may reflect that the structured feature of the first sub-data is a bit sequence (also referred to as a second bit sequence) distributed according to another law (also referred to as a second law). The first rule is different from the second rule. For example, the distribution of bits "0" and "1" in the first bit sequence may be different from the distribution of bits "0" and "1" in the second bit sequence. Furthermore, the data length of the first bit sequence may be the same or different from the data length of the second bit sequence.

In one embodiment, in response to a data write event for the first logical unit, the memory control circuit 23 may store category information corresponding to the first logical unit in the management table. For example, the data write event may be used to store data belonging to a first logical unit (i.e., first data) into the memory module 122 along with a first error correction code. The category information may reflect a type of the first data. Then, in response to a data read event for the first logic unit, the memory control circuit 23 may retrieve the category information from the management table, thereby determining the preset bit information according to the category information. For example, the data read event may be used to read data belonging to a first logical unit (i.e., first data) and a first error correction code from the memory module 122. Thus, during the subsequent reading of the first data, the memory control circuit 23 can determine the type of the first data synchronously, thereby obtaining the predetermined bit information.

In one embodiment, after the first sub-data and the predetermined bit information are obtained, the memory control circuit 23 may perform a data detection operation (also referred to as a first data detection operation) on the first sub-data according to the predetermined bit information to correct an error (i.e. an error bit) in the first sub-data. For example, in the first data detection operation, the memory control circuit 23 may flip (flip) at least a portion of bits in the first sub data (e.g., flip a bit from "1" to "0" or from "0" to "1") based on the preset bit information to correct an error in the first sub data. It should be noted that the first data detection operation does not involve decoding the first data based on the first error correction code.

In an embodiment, the memory control circuit 23 may compare the first sub-data with a predetermined data format reflected by the predetermined bit information to obtain a comparison result. For example, the comparison may reflect whether there is at least one bit (i.e., an error bit) in the first sub-data that does not match the structured feature of the first sub-data. For example, according to the structural feature of the first sub-data, if the preset bit information reflects that the bit value of a certain bit (also referred to as the first bit) in the first sub-data is preset to be "1", but the first bit in the first sub-data currently acquired is actually "0", the comparison result may reflect that the first bit is an error bit. Or according to the structural feature of the first sub-data, if the preset bit information reflects that the bit value preset of another bit (also called a second bit) in the first sub-data is "0", but the bit value of the second bit in the first sub-data currently obtained is actually "1", the comparison result may reflect that the second bit is an error bit. The memory control circuit 23 may then flip at least one bit (e.g., the first bit and/or the second bit) in the first sub-data according to the comparison result. Thus, errors in the first sub-data can be quickly corrected by the first data detection operation that is relatively low in computational complexity and/or relatively fast in execution speed without involving decoding of the first data based on the first error correction code.

Fig. 5 is a schematic diagram of a first data detection operation shown according to an embodiment of the present invention. Referring to fig. 5, it is assumed that the first data includes data 51. After determining the variable sampling window W (i), the sub-data 501 of the data 51 that is located within the bit interval R (i) may be determined as the first sub-data. Further, the remaining data of the data 51, which is not located within the bit section R (i), is not determined as the first sub-data. On the other hand, the memory control circuit 23 may acquire preset bit information corresponding to the data 51. This preset bit information may reflect a preset data format 502 of the sub-data 501.

After determining that the sub-data 501 is the first sub-data and the predetermined data format 502, in the first data detection operation, the memory control circuit 23 may compare the sub-data 501 with the predetermined data format 502 to obtain a comparison result. For example, the comparison may reflect whether there is at least one bit (i.e., an error bit) in the sub-data 501 that does not match the structured characteristics of the sub-data 501. If the comparison reflects the presence of the error bit in the sub-data 501, the memory control circuit 23 may flip the error bit. Or if the comparison reflects that there is not at least one bit (i.e., an error bit) in the sub-data 501 that does not match the structured characteristics of the sub-data 501, the memory control circuit 23 may not flip any bit in the sub-data 501.

In one embodiment, the memory control circuit 23 may detect whether at least one bit (i.e. an error bit) that does not match the structural feature of the sub-data 501 exists in the sub-data 501 by performing an exclusive or (XOR) operation or other logic operation on the sub-data 501 and a plurality of bits in the predetermined data format 502 one by one. Alternatively, in an embodiment, the memory control circuit 23 may perform the one-by-one or batch comparison on the plurality of bits in the sub-data 501 and the predetermined data format 502 in other manners, which is not limited in the present invention.

In one embodiment, after performing the first data detection operation on the first sub-data, the memory control circuit 23 may instruct the error correction circuit 25 to further perform a decoding operation on the first data according to the first error correction code. For example, in this decoding operation, the error correction circuit 25 may correct errors (i.e., error bits) in the first data in cooperation with the first error correction code based on the LDPC or other decoding algorithm.

It should be noted that, since at least a part of errors (even all errors) in the first sub-data in the first data have been corrected in advance in the first data detection operation, the error correction information carried by the first error correction code can be used as much as possible to decode the rest of the first data that does not belong to the first sub-data in the decoding operation performed on the first data by the subsequent error correction circuit 25. Thus, the overall decoding performance of the memory device 12 for the first data can be effectively improved.

In one embodiment, the memory control circuit 23 may update the first sub data to new data (also referred to as the second sub data) according to the operation result of the first data detection operation. For example, after a portion of error bits in the first sub data are flipped in the first data detection operation, the corrected first sub data may be determined as the second sub data. In particular, the second sub-data conforms to a predetermined data format reflected by the predetermined bit information. For example, the bit sequence formed by the plurality of bits included in the second sub data may have the predetermined data format. Or from another point of view, the bit sequence formed by the plurality of bits included in the second sub-data may be identical (e.g., identical) to the distribution and/or ordering of bits "1" and/or "0" defined by the predetermined data format.

In one embodiment, after determining the second sub-data, the memory control circuit 23 may combine the second sub-data with the rest of the first data (also referred to as third sub-data) into new data (also referred to as second data). Then, the error correction circuit 25 may perform the decoding operation on the second data according to the first error correction code. The corrected second data may then be transmitted to the host system 11, in response to the read command,

Fig. 6 is an operational scenario diagram of a decoding method according to an embodiment of the present invention. Referring to fig. 6, it is assumed that the first data includes data 61. After determining the variable sampling window W (i), the sub-data 602 within the bit interval R (i) in the data 61 may be determined as the first sub-data. In addition, the data 61 further includes remaining data, i.e., sub-data 601 and 603, which are not located within the bit interval R (i).

After the first data detection operation for the sub data 602, the sub data 602 may be updated to the sub data 621 according to the operation result of the first data detection operation. For example, compared to the sub-data 602, at least a portion of the errors in the sub-data 621 have been corrected based on the structured features of the sub-data 602. The sub-data 621 may then be combined with sub-data 601 and 603 as data 62. For example, data 62 includes sub-data 601, 621, and 603. For example, the second data includes data 62.

After the data 62 is obtained, the error correction circuit 25 may perform a decoding operation on the data 62 according to the first error correction code. For example, the data 62 may be updated to the data 63 according to the result of the execution of this decoding operation. For example, data 63 includes sub-data 631, 621, and 632. The sub data 631 is generated based on the first error correction code to correct errors in the sub data 601. The sub-data 632 is generated by correcting errors in the sub-data 603 based on the first error correction code. Compared to the data 62, the error originally existing in the data 62 in the data 63 has been corrected based on the first error correction code.

In particular, in the embodiment of fig. 6, since at least a portion of the errors (even all the errors) in the sub-data 602 have been corrected in advance in the first data detection operation, the error correction information carried by the first error correction code can be concentrated as much as possible in the decoding operation performed on the data 62 to correct the errors in the sub-data 601 and 603, so as to generate the sub-data 631 and 632. Thus, the overall decoding performance of the memory device 12 for the first data can be effectively improved.

From another point of view, in the embodiment of fig. 6, the error of the sub-data 602 is corrected based on the structural features of the sub-data 602, and then the errors in the sub-data 601 and 603 are corrected based on the first error correction code, so that the error correction capability of the storage device 12 for the data 61 can be effectively improved without greatly increasing the operation load.

Fig. 7 is a flowchart of a decoding method according to an embodiment of the present invention. Referring to fig. 7, in step S701, in response to a read command for reading first data from the memory module, the first data and the first error correction code corresponding to the first logic unit are read. In step S702, first sub data is determined from the first data. In step S703, a first data detection operation is performed on the first sub data according to the preset bit information to correct errors in the first sub data. In step S704, after the first data detection operation is performed on the first sub data, a decoding operation is performed on the first data according to the first error correction code.

However, the steps in fig. 7 are described in detail above, and will not be described again here. It should be noted that each step in fig. 7 may be implemented as a plurality of program codes or circuits, and the present invention is not limited thereto. In addition, the method of fig. 7 may be used with the above exemplary embodiment, or may be used alone, and the present invention is not limited thereto.

In summary, the decoding method and the storage device provided by the embodiments of the present invention can improve the decoding efficiency of the storage device. In particular, by splitting the data to be decoded into data with structured features and data without structured features and correcting the data with structured features in the data to be decoded based on the structured features (or preset bit information) before performing the decoding operation on the data to be decoded, the number of error bits that need to be corrected by the decoding operation in the following can be effectively reduced. Therefore, the decoding capability of the storage device can be effectively improved without obviously improving (even reducing) the overall operation load.

It should be noted that the above embodiments are merely for illustrating the technical solution of the present invention and not for limiting the same, and although the present invention has been described in detail with reference to the above embodiments, it should be understood by those skilled in the art that the technical solution described in the above embodiments may be modified or some or all of the technical features may be equivalently replaced, and these modifications or substitutions do not make the essence of the corresponding technical solution deviate from the scope of the technical solution of the embodiments of the present invention.

Claims

1. A decoding method for a storage device, wherein the storage device comprises a memory module, and the decoding method comprises:

Reading first data and a first error correction code corresponding to a first logic unit in response to a read instruction for reading the first data from the memory module;

Determining first sub-data from the first data;

Performing a first data detection operation on the first sub-data according to preset bit information to correct errors in the first sub-data, and

After the first data detection operation is performed on the first sub-data, a decoding operation is performed on the first data according to the first error correction code.

2. The decoding method of claim 1, wherein determining the first sub-data from the first data comprises:

Determining a variable sampling window according to the type of the first data;

determining a target bit interval in the first data according to the variable sampling window, and

And determining bit data in the target bit interval in the first data as the first sub data.

3. The decoding method of claim 2, wherein determining the variable sampling window according to the type of the first data comprises:

if the type is a first type, determining a first candidate sampling window as the variable sampling window, and

And if the type is a second type, determining a second candidate sampling window as the variable sampling window, wherein a first target bit interval determined in the first data according to the first candidate sampling window is different from a second target bit interval determined in the first data according to the second candidate sampling window.

4. The decoding method of claim 1, wherein the preset bit information reflects a preset data format of the first sub data.

5. The decoding method of claim 1, further comprising:

and determining the preset bit information according to the type of the first data.

6. The decoding method of claim 5, wherein determining the preset bit information according to the type of the first data comprises:

if the type is the first type, determining the first candidate bit information as the preset bit information, and

And if the type is a second type, determining second candidate bit information as the preset bit information, wherein the first preset data format reflected by the first candidate bit information is different from the second preset data format reflected by the second candidate bit information.

7. The decoding method of claim 5, wherein determining the preset bit information according to the type of the first data comprises:

storing category information corresponding to the first logical unit in a management table in response to a data write event for the first logical unit, wherein the category information reflects a type of the first data, and

And in response to a data reading event for the first logic unit, acquiring the category information from the management table, and determining the preset bit information according to the category information.

8. The decoding method of claim 1, wherein performing the first data detection operation on the first sub data according to the preset bit information to correct the error in the first sub data comprises:

Comparing the first sub data with a preset data format reflected by the preset bit information to obtain a comparison result, and

And according to the comparison result, turning at least one bit in the first sub-data.

9. The decoding method of claim 1, wherein after performing the first data detection operation on the first sub-data, performing the decoding operation on the first data according to the first error correction code comprises:

updating the first sub data into second sub data according to the operation result of the first data detection operation;

combining the second sub-data with a third sub-data of the first data to form second data, and

And performing the decoding operation on the second data according to the first error correction code.

10. The decoding method of claim 9, wherein the second sub-data conforms to a preset data format reflected by the preset bit information.

11. A memory device, comprising:

a connection interface for connecting to a host system;

memory module, and

A memory controller connected to the connection interface and the memory module,

Wherein the memory controller is to:

Determining first sub-data from the first data;

12. The storage device of claim 11, wherein the operation of the memory controller to determine the first sub-data from the first data comprises:

Determining a variable sampling window according to the type of the first data;

13. The memory device of claim 12, wherein the operation of the memory controller to determine the variable sampling window according to the type of the first data comprises:

14. The storage device of claim 11, wherein the preset bit information reflects a preset data format of the first sub data.

15. The storage device of claim 11, wherein the memory controller is further to:

16. The memory device of claim 15, wherein the operation of the memory controller to determine the preset bit information according to the type of the first data comprises:

17. The memory device of claim 15, wherein the operation of the memory controller to determine the preset bit information according to the type of the first data comprises:

18. The memory device of claim 11, wherein the memory controller performing the first data detection operation on the first sub data to correct the error in the first sub data according to the preset bit information comprises:

19. The storage device of claim 11, wherein the memory controller, after performing the first data detection operation on the first sub-data, performs the decoding operation on the first data according to the first error correction code, comprises:

20. The memory device of claim 19, wherein the second sub-data conforms to a preset data format reflected by the preset bit information.