CN120295959A

CN120295959A - Method and device for accessing memory

Info

Publication number: CN120295959A
Application number: CN202410042162.5A
Authority: CN
Inventors: 乔义川; 田亦鸽; 房帅磊
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2024-01-10
Filing date: 2024-01-10
Publication date: 2025-07-11
Also published as: WO2025148598A1

Abstract

The present application discloses a method and device for accessing a memory, which relates to the field of terminal technology and can solve the problem that a terminal device with a multi-processor architecture cannot achieve scientific and orderly memory access. In the present application, multiple processors of a terminal device share the same memory, which can ensure that any processor can normally perform data storage, modification or reading of stored data, etc. in any usage scenario. In addition, any of the multiple processors can realize mutually exclusive access to the memory by multiple processors based on whether other processors are accessing the memory, thereby achieving more scientific and orderly memory sharing. The solution in which multiple processors of a terminal device share the same memory can also reduce the production cost of the terminal device and provide support for the miniaturization of the terminal device.

Description

Method and device for accessing memory

Technical Field

The present application relates to the field of terminal technologies, and in particular, to a method and apparatus for accessing a memory.

Background

Currently, some terminal devices use a multiprocessor architecture, such as including dual processors, such as a main processor and a coprocessor, in some terminal devices, for service functions, endurance, and the like. For terminal devices of a multiprocessor architecture, how to access memory by multiple processors is a problem to be solved.

Disclosure of Invention

The application provides a method and equipment for accessing a memory, which can solve the problem that terminal equipment of a multiprocessor architecture cannot realize scientific and orderly memory access.

In order to achieve the above purpose, the application adopts the following technical scheme:

In a first aspect, a method for accessing a memory is provided, the method is applied to a first processor in a terminal device, the terminal device comprises a second processor and a memory in addition to the first processor, the first processor and the second processor share the memory, the method comprises the steps that the first processor receives a service request applied for requesting to access the memory, the first processor obtains first information used for representing whether the second processor is accessing the memory from the second processor, and the first processor responds to the service request to access the memory when the first information represents that the second processor does not access the memory.

According to the scheme provided by the first aspect, the multiple processors (such as the first processor and the second processor) of the terminal equipment can ensure that any processor can normally store data, modify or read stored data and the like under any use scene by sharing the same memory. And any one of the plurality of processors (such as the first processor) can realize exclusive access to the memory based on the situation that other acquired processors (such as the second processor) access the memory, such as the situation that whether other processors are accessing the memory, so as to realize more scientific and ordered sharing of the memory. Moreover, the scheme that the multiple processors (such as the first processor and the second processor) of the terminal equipment share the same memory can also reduce the production cost of the terminal equipment and provide support for miniaturization of the terminal equipment.

As an example, the first information may represent, in plain text, whether the second processor is accessing the memory, such as a direct indication, or the first information may represent, in implied form, whether the second processor is accessing the memory, such as a parameter representation, a preset action (e.g., no reply) representation, and the like.

As an example, the first processor may obtain information directly from the second processor that characterizes whether the second processor is accessing memory. The application is not limited to the particular manner and process by which the first processor and the information characterizing whether the second processor is accessing memory, for example, in some examples, the first processor may also obtain information characterizing whether the second processor is accessing memory from a third party, such as a state storage unit.

As an example, the first processor is an application processor (application processor, AP) and the second processor is a micro-program controller (microprogrammed control unit, MCU), or the first processor is an MCU, the second processor is an AP, and the memory is an embedded multimedia memory card (eMMC) MEDIA CARD. Of course, the first processor or the second processor may also be a device, a module or a chip with other structures or functions, and the application is not limited thereto.

As one possible implementation, the first processor includes a first pin and the second processor includes a second pin, the first pin being connected to the second pin, the first processor obtaining first information from the second processor, including the first processor obtaining a state of the first pin, the state of the first pin being used to characterize whether the second processor is accessing the memory. It will be appreciated that since the first pin of the first processor is connected to the second pin of the second processor, the first pin is able to sense the state of the second pin, based on which it can be identified from the sensed state of the second pin whether the second processor is accessing memory. The scheme provides a more convenient, low-cost, low-consumption and accurate implementation mode for acquiring the conditions of other processors accessing the memory.

As one possible implementation, the state of the first pin includes a first level and a second level, and the method further includes determining that the second processor is accessing the memory if the state of the first pin is the first level, and determining that the second processor is not accessing the memory if the state of the first pin is the second level. Based on the method, the implementation mode for obtaining the conditions of other processors accessing the memory can be provided more conveniently, at lower cost and with lower consumption.

As an example, the present application is not particularly limited, and the first level may be a high level, the second level may be a low level, or the first level may be a low level, and the second level may be a high level.

As a possible implementation, the state of the first pin is the first level when the state of the second pin is the third level, and the state of the first pin is the second level when the state of the second pin is the fourth level. Based on the method, the first processor can be supported to sense the state of the second pin according to the state of the first pin, and further whether the second processor is accessing the memory or not can be accurately judged, so that the condition that the second processor accesses the memory can be conveniently and accurately obtained.

As an example, the present application is not particularly limited, and the third level may be a high level, the fourth level may be a low level, or the third level may be a low level, and the fourth level may be a high level.

As one possible implementation, the first processor further includes a third pin, the state of the third pin being indicative of whether the first processor is accessing the memory. Based on the method, other processors can conveniently know whether the first processor is accessing the memory or not, so that conflicts caused by the fact that a plurality of processors access the memory simultaneously are prevented, and more scientific and ordered sharing of the memory is achieved.

As a possible implementation, the state of the third pin is the fifth level when the first processor accesses the memory, and the state of the third pin is the sixth level when the first processor does not access the memory. Based on this, it is possible to easily and accurately inform other processors whether the first processor is accessing the memory.

As an example, the present application is not particularly limited, and the fifth level may be a high level, the sixth level may be a low level, or the fifth level may be a low level, and the sixth level may be a high level.

As a possible implementation manner, the method further includes, before the first processor accesses the memory, adjusting the state of the third pin from the sixth level to the fifth level. Based on the method, other processors can conveniently know whether the first processor is accessing the memory or not, so that conflicts caused by the fact that a plurality of processors access the memory simultaneously are prevented, and more scientific and ordered sharing of the memory is achieved.

As a possible implementation manner, the first processor adjusts the state of the third pin from the sixth level to the fifth level, which includes that the first processor obtains second information indicating whether the second processor accesses the memory from the second processor after receiving the service request, and when the second information indicates that the second processor does not access the memory, the first processor adjusts the state of the third pin from the sixth level to the fifth level. Based on this, the first processor informs the other processors in time whether the first processor is accessing the memory by adjusting the state of the third pin when the memory access is about to be started. In addition, in order to avoid the conflict caused by that the second processor starts to access the memory after the first processor determines that the state of the first pin is the second level based on the second information and further determines that the second processor does not access the memory, the first processor can determine whether the second processor accesses the memory through the acquired first information again, so as to ensure that the first processor and the second processor cannot access the memory simultaneously.

As a possible implementation manner, the first processor acquires the first information from the second processor, where the first processor acquires the first information from the second processor after waiting for a preset time period when the second information indicates that the second processor is accessing the memory. Based on the above, the first processor can avoid the waste of power consumption, processing resources and the like brought by the terminal equipment by continuously acquiring the first information from the second processor.

As one possible implementation, the memory includes a partition corresponding to the first processor and not corresponding to the second processor, a partition corresponding to the first processor and the second processor, and the service request is for requesting access to one or more partitions in the memory that are corresponding to the first processor and not corresponding to the second processor, and a partition corresponding to the first processor and the second processor. Based on the method, no matter which partition of the memory is accessed by the first processor, data storage, modification or reading of stored data and the like can be normally performed, and more scientific and orderly sharing of the memory by a plurality of processors can be realized.

As an example, the memory further includes a partition corresponding to the second processor and not corresponding to the first processor. Of course, the present application is not limited to a particular partition of memory, e.g., a memory may not include an exclusive partition corresponding to the first processor or the second processor.

As one possible implementation, the first processor accesses the memory for performing one or more of reading data in the memory, writing data to the memory, and modifying data in the memory. Based on the method, no matter what the purpose of the first processor accessing the memory is, the data access can be normally performed, and more scientific and orderly sharing of the memories by a plurality of processors can be realized.

In a second aspect, a chip is provided, the chip comprising a processing module and one or more pins for supporting the chip to implement a method as in any one of the possible implementations of the first aspect.

As an example, the chip is such as an AP or MCU.

In a third aspect, there is provided a terminal device comprising a first processor, a second processor and a memory, the first processor and the second processor sharing the memory, the first processor or the second processor being adapted to implement a method as in any one of the possible implementations of the first aspect.

In a fourth aspect, a computer readable storage medium is provided, having stored thereon computer program instructions which, when executed by a processor, implement a method as in any one of the possible implementations of the first aspect.

In a fifth aspect, there is provided a computer program product containing instructions which, when run on a computer, cause the computer to carry out the method as in any one of the possible implementations of the first aspect.

In a sixth aspect, a chip system is provided, where the chip system includes a processing circuit, a storage medium having stored therein computer program instructions, which when executed by the processor, implement a method as in any of the possible implementations of the first aspect. The chip system may be formed of a chip or may include a chip and other discrete devices.

Drawings

FIG. 1 is a schematic diagram of a terminal device including a dual processor and dual memory architecture;

fig. 2 is a schematic hardware structure of a terminal device according to an embodiment of the present application;

Fig. 3 is a schematic structural diagram of a terminal device in which a main processor and a coprocessor share the same memory according to an embodiment of the present application;

FIG. 4 is a schematic diagram of a memory area division manner of a memory according to an embodiment of the present application;

Fig. 5 is a schematic software structure of a terminal device according to an embodiment of the present application;

FIG. 6 is a diagram of a memory access process architecture according to an embodiment of the present application;

FIG. 7 is a diagram of another memory access process architecture according to an embodiment of the present application;

FIG. 8 is a schematic diagram of an interactive process when accessing a memory according to an embodiment of the present application;

FIG. 9 is a flowchart of a method for accessing a memory according to an embodiment of the present application;

FIG. 10 is a flowchart of another method for accessing a memory according to an embodiment of the present application;

FIG. 11 is a flow chart of a process for accessing a memory according to an embodiment of the present application.

Detailed Description

The technical solutions in the embodiments of the present application will be described below with reference to the accompanying drawings in the embodiments of the present application. In the description of the embodiment of the present application, unless otherwise indicated, "/" means or, for example, a/B may represent a or B, and "and/or" herein is merely an association relationship describing an association object, which means that three relationships may exist, for example, a and/or B, and that three cases, i.e., a alone, a and B together, and B alone, exist. In addition, in the description of the embodiments of the present application, "plurality" means two or more than two.

Hereinafter, the terms "first", "second", and the like are used merely to distinguish different description objects, and do not limit the position, order, priority, number, or content of the described objects. For example, when the object is described as a "field", the ordinal words before the "field" in the "first field" and the "second field" do not limit the position or the sequence between the "fields", and the "first" and the "second" do not limit whether the modified "fields" are in the same message or not, and do not limit the sequence of the "first field" and the "second field". For another example, if the object to be described is "level", the ordinal words before "level" in the "first level" and "second level" do not limit the priority between "levels". As another example, the number of the described objects is not limited by the ordinal words, and may be one or more, taking the "first device" as an example, where the number of "devices" may be one or more. Further, the objects modified by different prefix words may be the same or different, for example, the described object is a "device", the "first device" and the "second device" may be the same type of device or different types of devices, and for example, the described object is a "level", the "first level" and the "second level" may be the same level or different levels. In summary, the use of ordinal words, etc., to distinguish between the prefix words describing the object in the embodiments of the present application does not limit the described object, and statements of the described object are to be taken in the claims or the context of the embodiments and should not be construed as unnecessary limitations due to the use of such prefix words.

In addition, in the embodiment of the present application, the "connection" may be a direct connection or an indirect connection, and further may refer to an electrical connection or a communication connection, for example, two electrical elements a and B may be connected, and may refer to a direct connection between a and B, or may refer to an indirect connection between a and B through other electrical elements or a connection medium, or may refer to an indirect connection between a and B through other communication devices or communication mediums, so long as a communication between a and B is enabled.

As described in the background, some terminal devices use a multiprocessor architecture such as a dual processor, for example, a dual processor architecture using a main processor and a coprocessor, due to service functions, endurance, and the like. As an example, the terminal device may include an application processor (application processor, AP) and a micro-program controller (microprogrammed control unit, MCU). The AP is mainly used for running an operating system and multimedia applications, such as a System On Chip (SOC), and the MCU is sometimes called a singlechip and is mainly used for signal control, and the MCU can be used for performing simple operations due to the characteristics of low cost and low power consumption.

As a possible structure, the terminal device further includes a memory for providing a data storage service for the AP, such as an embedded multimedia memory card (eMMC), based on which the MCU can interact with the AP to achieve the purpose of storing MCU-related data by means of the memory configured for the AP.

Along with the diversification development of terminal devices and the low power consumption requirement of the terminal devices, more and more terminal devices support a low power consumption mode (such as a super power saving mode, without limiting specific mode names), and some idle hardware modules can be powered down in the low power consumption mode to save the power consumption of the terminal devices. For example, in a low power mode, the AP of the terminal device and the memory (e.g., eMMC) configured for it may be powered down, while the MCU operates normally. In this case, the MCU may fail to perform normal data storage and normal reading, modification, deletion, etc. of data already stored to the memory due to power-down of the AP and the memory.

In order to solve the above-mentioned problems of the terminal device in the low power consumption mode, as a possible structure, the terminal device may include a plurality of memories configured for a plurality of processors, respectively, for example, the terminal device may employ a dual processor and dual memory architecture. As shown in fig. 1, an eMMC1 and an eMMC2 configured for an AP and an MCU, respectively, may be included in the terminal device, where the AP and the MCU may be connected to the eMMC1 and the eMMC2 through secure digital input output card (secure digital input and output, SDIO) interfaces (SDIO 1 and SDIO2 as shown in fig. 1), respectively, and the AP and the MCU may be connected through a serial peripheral interface (SERIAL PERIPHERAL INTERFACE, SPI) as shown in fig. 1 for related interaction. Based on this, the MCU can normally perform data storage and normal reading, modification, deletion, etc. of stored data, whether in a normal mode or a low power consumption mode.

The dual processor and dual memory architecture of fig. 1 creates a split of the memory space corresponding to the AP and MCU, which may result in some data (e.g., music, etc.) for applications associated with both the AP and MCU being written to both eMMC1 and eMMC2 memories simultaneously. In addition, the cost of the dual memory is high, and the layout of hardware in the terminal device is affected, and particularly, at present, the cost and the layout challenges may bring about a great barrier to the requirements of lower cost and miniaturization of the device.

In order to solve the above-mentioned problems of the dual processor and dual memory architecture terminal device and solve the problem that the MCU cannot perform normal data storage and normal reading, modification and deletion of data stored to the memory in the low power mode of the dual processor and single memory architecture terminal device, the embodiment of the present application provides a scheme in which multiple processors share the same memory, in which the terminal device includes multiple processors, such as a main processor and a coprocessor, and the multiple processors share the same memory. Based on this, compared with the architecture in which the MCU stores MCU-related data by means of the memory configured for the AP, even if the AP and the memory configured for the AP are powered down in the low power mode, the storage of MCU-related data and the normal reading, modification, deletion, etc. of stored data can be normally performed.

Compared with the dual processor and dual memory architecture shown in fig. 1, the scheme provided by the embodiment of the application can avoid the problem that data of applications related to the AP and the MCU are repeatedly written, can reduce the production cost of the terminal equipment, and provides support for miniaturization of the terminal equipment.

In addition, in the scheme provided by the embodiment of the application, multiple processors of the terminal equipment can share the same memory, and any one of the multiple processors can realize exclusive access of the multiple processors to the memory based on the acquired condition that other processors access the memory, such as whether the other processors are accessing the memory, so as to realize more scientific and ordered memory sharing.

The terminal device in the embodiment of the present application may include, but is not limited to, a smart phone, a netbook, a tablet computer, an intelligent drawing board, a handwriting board, a smart watch, a smart bracelet, a phone watch, smart glasses, a smart camera, a palm computer, a vehicle-mounted computer, a personal computer (personal computer, PC), a personal digital assistant (personal DIGITAL ASSISTANT, PDA), a portable multimedia player (portable multimedia player, PMP), an augmented reality (augmented reality, AR)/Virtual Reality (VR) device, a smart television, a projection device, or a motion sensing game machine in a human-computer interaction scene. Or the terminal device may be other types or structures of terminal devices, which are not limited by the present application.

As an example, please refer to fig. 2, fig. 2 illustrates a schematic hardware structure of a terminal device provided by an embodiment of the present application, which includes a main processor and a coprocessor, wherein the main processor and the coprocessor share the same memory.

As shown in fig. 2, the terminal device may include a main processor, a coprocessor, a memory, an audio module, a speaker, a microphone, a display screen, a camera, a sensor module, and the like. The sensor module may include an acceleration sensor, a gyro sensor, a magnetic sensor and gravity sensor, a bone conduction sensor, etc. as shown in fig. 2, among others. In some possible configurations, the sensor module may further include a touch sensor, a pressure sensor, a barometric sensor, a distance sensor, a proximity sensor, a fingerprint sensor, an ambient light sensor, and other types of sensors, and embodiments of the present application are not limited in detail.

The main processor is mainly responsible for running an operating system and multimedia applications, such as managing and maintaining application information and application related user information, implementing system functions (such as a music playing function and a dial function), and the like, and may include, but is not limited to, an AP and the like. The coprocessor is mainly used for signal control, simple operations and the like, such as music player related control, dial related control, sensor module measurement control, sensor acquired data related calculation and the like, and can comprise but not limited to a low-power-consumption processor such as an MCU and the like.

The terminal device may implement audio functions through an audio module, a speaker, a microphone, an AP, and the like. Such as music playing, recording, etc.

The audio module is used for converting digital audio information into analog audio signals for output and also used for converting analog audio input into digital audio signals. The audio module may also be used to encode and decode audio signals. In some embodiments, the audio module may be disposed in the main processor, or a portion of the functional modules of the audio module may be disposed in the main processor.

Speakers, also known as "horns," are used to convert audio electrical signals into sound signals. The terminal device can listen to music through a speaker or listen to hands-free conversation.

Microphones, also known as "microphones" and "microphones", are used to convert sound signals into electrical signals. When making a call or transmitting voice information, a user can sound near the microphone through the mouth, inputting a sound signal to the microphone. The terminal device may be provided with at least one microphone C. In other embodiments, the terminal device may be provided with two microphones, and may implement a noise reduction function in addition to collecting the sound signal. In other embodiments, the terminal device may further be provided with three, four or more microphones to collect sound signals, reduce noise, identify the source of sound, implement directional recording functions, etc.

The acceleration sensor (or accelerometer) may detect the magnitude of the acceleration of the terminal device in various directions (typically three axes). The gravity and direction can be detected when the terminal equipment is stationary, and the gravity detection device can be used for identifying the gesture of the terminal equipment and the like and can be applied to pedometers and the like. In some embodiments, the terminal device may derive a movement direction and a movement speed of the user, etc., based on the data detected by the acceleration sensor.

The gyro sensor may be used to determine a motion gesture during motion of the terminal device. In some embodiments, the rotational direction and rotational angular velocity of the terminal device about three axes (i.e., x, y, and z axes) may be determined by a gyroscopic sensor.

A magnetic sensor, such as a hall sensor, is a device that converts a change in magnetic properties of a sensing element caused by external factors such as a magnetic field, a current, a stress strain, a temperature, light, etc., into an electrical signal, and in this way, detects a corresponding physical quantity. In some embodiments, the angles between the terminal device and the four directions of southwest, southwest and north can be measured through the magnetic sensor.

The gravity sensor can be used for detecting the magnitude and direction of gravity applied to the terminal equipment. In some embodiments, the terminal device may obtain information of a location, an altitude, etc. where the user is located based on the data detected by the gravity sensor.

The bone conduction sensor may acquire a vibration signal. In some embodiments, the bone conduction sensor may acquire a vibration signal of the human vocal tract vibrating the bone pieces. The bone conduction sensor can also contact the pulse of a human body to receive the blood pressure jumping signal. In some embodiments, the heart rate information can be analyzed based on the blood pressure beat signal obtained by the bone conduction sensor, so that the functions of heart rate detection, sleep detection and the like are realized.

The display screen is used for displaying images, videos, and the like. The display screen includes a display panel. The display panel may employ a Liquid Crystal Display (LCD) screen (liquid CRYSTAL DISPLAY), an organic light-emitting diode (OLED), an active-matrix organic LIGHT EMITTING diode (AMOLED), a flexible light-emitting diode (FLED), miniled, microLed, micro-OLED, a quantum dot LIGHT EMITTING diodes (QLED), or the like.

The memory may be used to store computer-executable program code. By way of example, computer programs may include operating system programs and application programs. Wherein the executable program code includes instructions. The main processor or co-processor performs various functional applications of the terminal device and data processing by executing instructions stored in the memory.

Taking the example that the main processor is an AP and the coprocessor is an MCU, the memory may be used to store AP related data and MCU related data, where the AP related data is AP system data, AP application data for implementing different functions, and the like, and the MCU related data is sensor hub (sensorhub) system data, sensorhub application data, sensor module related data (such as exercise data, health data, and the like), and the embodiment of the present application is not limited specifically.

As an example, the memory may be eMMC, or the memory may include eMMC.

In an embodiment of the present application, the memory may include a storage program area and a storage data area. The storage program area may store an operating system, an application program required for at least one function, and the like. The storage data area may store data created during use of the terminal device, etc. In addition, the memory may include high-speed random access memory, and may also include non-volatile memory, such as at least one disk storage device, flash memory device, universal flash memory (universal flash storage, UFS), and the like. The main processor or the coprocessor performs various functional applications of the terminal device and data processing by executing instructions stored in a memory.

It will be appreciated that the structure illustrated in fig. 2 of the present application does not constitute a specific limitation on the terminal device. In other embodiments of the application, the terminal device may include more or fewer components than shown. For example, the terminal device may further include one or more other processing units such as a modem processor, a graphics processor (graphics processing unit, GPU), an image signal processor (IMAGE SIGNAL processor, ISP), a flight controller, a video codec, a digital signal processor (DIGITAL SIGNAL processor, DSP), a baseband processor, a neural-Network Processor (NPU), etc., where the different processing units may be separate devices or may be integrated into one or more processors. As another example, the terminal device may further include one or more devices such as a charge management module, a power management module, a battery, an antenna, a mobile communication module, a wireless communication module, a key, an indicator, and the like.

Or the terminal device may also combine certain components, split certain components, or different arrangements of components. The components shown in fig. 2 may be implemented in hardware, software, or a combination of software and hardware.

As an example, please refer to fig. 3, fig. 3 illustrates a schematic structure of a terminal device provided by an embodiment of the present application, which includes a main processor and a coprocessor, wherein the main processor and the coprocessor share the same memory. The main processor shown in fig. 3 is an AP, a coprocessor is an MCU, and a memory shared by the main processor and the coprocessor is an eMMC.

In some embodiments, the memory may include multiple partitions, which may include a first partition (i.e., a main processor exclusive partition) and a second partition (i.e., a coprocessor exclusive partition) as shown in fig. 3, which are exclusive partitions of the main processor and the coprocessor, respectively. In this embodiment of the present application, exclusive partitioning refers to providing a data access service for a specific processor, including providing a data storage service, a data reading service, and the like, while not providing a data access service for other processors. That is, the first partition of the memory shown in FIG. 3 is used to store data from the host processor and may support the host processor to read the data stored in the first partition, the first partition cannot store data from the coprocessor and cannot support the coprocessor to read the data stored in the first partition, and likewise the second partition of the memory shown in FIG. 3 is used to store data from the coprocessor and may support the coprocessor to read the data stored in the second partition, the second partition cannot store data from the host processor and cannot support the host processor to read the data stored in the second partition.

In some embodiments, to avoid the problem of data being repeatedly written to by applications both of the AP and the MCU, as one possible structure, as shown in fig. 3, the memory may further include a third partition (i.e., a shared partition) that the main processor and the coprocessor may share, in addition to the first partition and the second partition that the main processor and the coprocessor are exclusive to each other. The third partition shown in fig. 3 may store data from the host processor and support the host processor to read the data stored in the third partition, and may also store data from the coprocessor and support the coprocessor to read the data stored in the third partition.

In some embodiments, a first partition, shown in fig. 3, may be used to store data related to functions or applications associated with a host processor (e.g., an AP), a second partition, shown in fig. 3, may be used to store data related to functions or applications associated with a coprocessor (e.g., an MCU), and a third partition, shown in fig. 3, may be used to store data related to functions or applications associated with both a host processor (e.g., an AP) and a coprocessor (e.g., an MCU).

As an example, please refer to fig. 4, fig. 4 illustrates a schematic diagram of a storage area division manner of a memory provided by an embodiment of the present application, taking a terminal device as a smart watch, where the terminal device includes an AP and an MCU as an example. As shown in fig. 4, a memory, such as eMMC, may include a first partition exclusive to an AP, a second partition exclusive to an MCU, and a third partition shared by the AP and the MCU.

The first partition (e.g., an AP exclusive partition) shown in fig. 4 may be used to store AP system data, application data of an AP application program corresponding to one or more functions provided by an AP (hereinafter referred to as "AP application data"), and other AP-related functions or application-related data. The AP may execute various AP system functions of the terminal device by executing the AP system-related instructions stored in the first partition, and the AP application data such as AP application-related instructions may execute the AP application functions of the terminal device and related data processing by executing the AP application-related instructions stored in the first partition.

As an example, as shown in fig. 4, the first partition may also include a plurality of sub-partitions, and different sub-partitions may be used to store different types of data, such as storing AP system data, AP application data, and the like, respectively.

The second partition (e.g., an exclusive partition of the MCU) shown in FIG. 4 may be used to store sensor hub (sensorhub) system data, application data, sensor module measurement data (e.g., motion, health data, etc.), etc., related data for MCU related functions or applications. Illustratively, the MCU may execute various sensorhub system functions of the terminal device by executing the sensor hub system-related instructions stored in the second partition, the sensor hub application data such as the sensor hub application-related instructions, and the MCU may execute the MCU application functions of the terminal device and related data processing such as calculating, processing, etc. the sensor module measurement data to obtain heart rate conditions, sleep conditions, step counting conditions, exercise health conditions, etc. of the user, and the sensor module measurement data such as heart rate data, sleep data, pedometer data, exercise health data, etc. of the user measured by the sensor module by executing the sensor hub application-related instructions stored in the second partition.

As an example, as shown in FIG. 4, the second partition may also include a plurality of sub-partitions, and different sub-partitions may be used to store different types of data, such as for storing sensor hub system data and application data, sensor module measurement data, and the like, respectively.

The third partition (e.g., shared partition) shown in fig. 4 may be used to store music, dials, etc. related data for functions or applications related to both the host processor (e.g., AP) and the coprocessor (e.g., MCU).

As an example, please refer to fig. 5, fig. 5 illustrates a software structure schematic diagram provided by an embodiment of the present application, taking an example that a main processor is an AP and a coprocessor is an MCU. As shown in fig. 5, the terminal device may include an AP system, an MCU system, and a memory (e.g., eMMC). The AP system and the MCU system comprise an application program layer, a framework layer (FWK) and a kernel layer from top to bottom.

The application layer may include a series of applications, among others. As shown in fig. 5, the application layer of the AP system may include applications of music, dials, etc., and the application layer of the MCU system may include applications of heart rate, pedometer, sports health, music, sleep, dials, etc.

The framework layer is used to provide an application programming interface (application programming interface, API) and programming framework for the application programs of the application layer. As shown in fig. 5, the framework layer of the AP system may provide a music framework, a dial framework, etc. for the upper layer AP application, and the framework layer of the MCU system may provide a heart rate framework, a pedometer framework, a sports health framework, a music framework, a sleep framework, a dial framework, etc. for the upper layer MCU application.

The kernel layer is a layer between hardware and software. The kernel layer may contain hardware-corresponding drivers, such as the storage driver and one or more sensor drivers shown in FIG. 5. Hardware such as memory (e.g., eMMC) and one or more sensors as shown in fig. 5.

The memory (e.g., eMMC) shown in fig. 5 may be used to store AP-related data and MCU-related data, where the AP-related data is, for example, AP system data, AP application data for implementing different functions, etc., and the MCU-related data is, for example, sensor hub (sensorhub) system data, sensorhub application data, sensor module-related data (e.g., exercise, health data, etc.), etc., and the embodiments of the present application are not limited specifically. The sensor shown in fig. 5 may include, but is not limited to, one or more of a speed sensor, a gyroscopic sensor, a magnetic sensor and gravity sensor, a bone conduction sensor, etc., and the sensor may be used to measure one or more of heart rate data, sleep data, pedometer data, sports health data, etc.

Of course, the specific hardware included in the terminal device is not limited in the embodiment of the present application, for example, the terminal device may further include one or more hardware such as a camera, a display screen (touch screen), a camera, a microphone, and correspondingly, the kernel layers of the AP system and the MCU system of the terminal device may further include one or more drivers such as a camera driver, a display driver, and a microphone driver.

In some embodiments, as shown in FIG. 5, the kernel layer may also contain a file system associated with file storage. The file system is mainly responsible for managing and storing file information, such as organizing and managing files stored on a memory. For example, a file system may be used to store meta-information for one or more data in memory, such as inode number, file size, access rights, creation time, modification time, location of data in memory, etc., and for another example, a file system may be used to store directory entries for one or more data in memory, such as names of data, inode pointers, and hierarchical associations with other directory entries, etc.

In some embodiments, as shown in fig. 5, the kernel layer may further include a Virtual File System (VFS) for abstracting details of the file system as an interface layer between the file system and the upper service framework such that different file systems appear to be identical to other processes running in the upper system core and the system. For example, the VFS may define a set of data structures and standard interfaces that are supported by all file systems.

It should be noted that fig. 5 is merely an example of a software architecture diagram of a terminal device, where only the layers and software modules related to the solution of the present application are simply listed. In practical applications, the software system of the terminal device, such as the AP system or the MCU system, may also comprise other levels and each level may also comprise other software modules for implementing one or more functions or services. The embodiment of the present application is not particularly limited.

In some embodiments, when a certain processor has a need to access memory, as shown in fig. 6 or fig. 7, when an application a in the first processor has a need to access memory, the application a may initiate a service request for accessing memory to the file system 1 of the first processor. Upon receiving a service request from application A, file system 1 may invoke storage drive 1 to obtain details of other processors (e.g., second processor) accessing memory, such as whether other processors (e.g., second processor) are accessing memory. If no processor is accessing the memory, the first processor starts to access the memory in response to the service request of the application A, and if other processors (such as a second processor) are accessing the memory, the first processor does not respond to the service request of the application A temporarily, does not access the memory temporarily, until no processor accesses the memory.

Likewise, when an application B in the second processor shown in fig. 6 or fig. 7 has a need to access the memory, the application B may initiate a service request to access the memory to the file system 2 of the second processor. Upon receiving a service request from application B, file system 2 may invoke storage drive 2 to obtain details of other processors (e.g., first processor) accessing memory, such as whether other processors (e.g., first processor) are accessing memory. If no processor is accessing the memory, the second processor starts to access the memory in response to the service request of the application B, and if other processors (such as the first processor) are accessing the memory, the second processor does not respond to the service request of the application B for a while, does not access the memory for a while, until no processor is accessing the memory.

As one possible implementation, the storage drive of the processor may obtain directly from the storage drive of the other processor whether the other processor is accessing the memory.

For example, as shown in FIG. 6, the storage drive 1 of the first processor may fetch whether the second processor is accessing memory directly from the storage drive 2 of the second processor. For example, pins are respectively arranged on the storage drive 1 of the first processor and the storage drive 2 of the second processor, for example, a first pin is arranged on the storage drive 1 of the first processor, a second pin is arranged on the storage drive 2 of the second processor, and the first pin is connected with the second pin. Based on this, the first processor may obtain the state of the second pin by obtaining the state of the first pin, thereby determining whether the second processor is accessing the memory. For example, assuming that the second processor is accessing the memory, the state of the second pin is typically a third level, and the state of the first pin of the first processor connected to the second pin is a first level when the state of the second pin is the third level, based on this, if the state of the first pin is the first level, the first processor may determine that the state of the second pin is the third level and thus determine that the second processor is accessing the memory. For another example, assuming that the second processor does not access the memory, the state of the second pin is typically a fourth level, and when the state of the second pin is the fourth level, the state of the first pin of the first processor connected to the second pin is a second level, based on which, if the state of the first pin is the second level, the first processor may determine that the state of the second pin is the fourth level and thus determine that the second processor does not access the memory.

Likewise, as shown in FIG. 6, the storage drive 2 of the second processor may fetch whether the first processor is accessing memory directly from the storage drive 1 of the first processor. For example, a third pin is provided on the memory driver 1 of the first processor, and a fourth pin is provided on the memory driver 2 of the second processor, and the third pin is connected to the fourth pin. Based on this, the second processor may obtain the state of the third pin by obtaining the state of the fourth pin, thereby determining whether the first processor is accessing the memory. For example, assuming that the first processor is accessing the memory, the state of the third pin is typically a third level, and the state of the fourth pin of the second processor connected to the third pin is a first level when the state of the third pin is the third level, based on this, if the state of the fourth pin is the first level, the second processor may determine that the state of the third pin is the third level and thus determine that the first processor is accessing the memory. For another example, assuming that the first processor does not access the memory, the state of the third pin is typically a fourth level, and when the state of the third pin is the fourth level, the state of a fourth pin of the second processor connected to the third pin is a second level, based on which, if the state of the fourth pin is the second level, the second processor may determine that the state of the third pin is the fourth level and thus determine that the first processor does not access the memory.

As an example, a first level, such as a high level, a second level, such as a low level, or a first level, such as a low level, a second level, such as a high level.

As an example, a third level, such as a high level, a fourth level, such as a low level, or a fourth level, such as a low level, a third level, such as a high level.

As an example, the first pin, the second pin, the third pin, or the fourth pin may be other pins, such as a general purpose input/output (GPIO) pin, although the embodiments of the present application are not limited in detail.

As a possible implementation, as shown in fig. 7, a state storage unit may be included in the terminal device, for storing a state flag bit for each processor to access the memory, such as storing a state flag bit for identifying whether each processor is accessing the memory.

For example, in the process that the first processor writes data to the memory through the storage drive 1 or reads data from the memory in response to the service request of the application a, the state storage unit may store a first flag, where the first flag is used to identify that the first processor is accessing the memory. For example, the storage drive 1 of the first processor may write the first flag to the state storage unit when starting to access the memory and delete the first flag when ending to access the memory. Based on this, in the process that the first processor accesses the memory, when the application B in the second processor has a need to access the memory, the second processor may determine that the first processor is accessing the memory according to the first flag acquired from the state storage unit.

Likewise, during the writing of data to or reading of data from memory by the storage drive 2 in response to a service request by the second processor by the application B, a second flag may be stored in the state storage unit, the second flag being used to identify that the second processor is accessing the memory. For example, the storage drive 2 of the second processor may write the second flag to the state storage unit when starting to access the memory and delete the second flag when ending to access the memory. Based on this, in the process that the second processor accesses the memory, when the application a in the first processor has a need to access the memory, the first processor may determine that the second processor is accessing the memory according to the second flag acquired from the state storage unit.

The following embodiments specifically describe a method for accessing a memory provided by the embodiments of the present application by taking, as an example, a manner in which a storage driver of a first processor directly obtains whether or not a second processor is accessing the memory from a storage driver of another processor, such as a second processor.

As an example, please refer to fig. 8, fig. 8 illustrates an interactive procedure architecture diagram when accessing a memory provided by an embodiment of the present application, taking a terminal device including an AP and an MCU, and the memory is eMMC as an example. As shown in fig. 8, the AP may acquire the state of pin B of the MCU through the state of pin a to determine whether the MCU is accessing eMMC, and the MCU may acquire the state of pin a of the AP through the state of pin B to determine whether the AP is accessing eMMC. Illustratively, the pin a or the pin B may be a GPIO pin or the like, and is not particularly limited. When deciding to access the eMMC based on the determined whether the MCU processor is accessing the eMMC, the AP may write data to the eMMC, read data from the eMMC, or modify data in the eMMC through the input-output interface a, and when deciding to access the eMMC based on the determined whether the AP processor is accessing the eMMC, the MCU may write data to the eMMC, read data from the eMMC, or modify data a in the eMMC through the input-output interface B. Illustratively, the input-output interface a or the input-output interface B, such as an SDIO interface, etc., are not particularly limited.

It should be noted that fig. 8 only takes, as an example, a pin a that can be used for both the AP to obtain information whether the MCU is accessing eMMC and a pin that can be used to indicate to other processors (e.g., the MCU) whether the AP is accessing eMMC, but the present application is not limited to whether both are characterized by the status of the same pin. For example, in some embodiments, the AP may include a first pin for the AP to obtain information whether the MCU is accessing eMMC and a third pin for indicating to other processors (e.g., the MCU) whether the AP is accessing eMMC.

Likewise, the MCU may obtain information on whether the AP is accessing eMMC through pin B, and indicate to other processors (e.g., AP) whether the MCU is accessing eMMC through pin B. Or in some embodiments, the MCU may include a second pin and a fourth pin, where the fourth pin is used by the MCU to obtain information whether the AP is accessing eMMC, and the second pin is used to indicate to other processors (e.g., the AP) whether the MCU is accessing eMMC.

As an example, referring to fig. 9, fig. 9 illustrates a flowchart of a method for accessing a memory provided by an embodiment of the present application, taking a first processor and a second processor in a terminal device sharing the same memory as an example. As shown in fig. 9, the method may be implemented based on S901-S903:

And S901, the first processor receives a service request of an application, wherein the service request is used for requesting to access a memory.

The first processor may be any one of a plurality of processors of the terminal device, such as a main processor or a coprocessor. Taking a terminal device including an AP and an MCU as an example, the first processor may be the AP or the MCU.

In some embodiments, the service request may be an application initiated request in the first processor. As an example, the application may include, but is not limited to, any one or more of music, heart rate, pedometer, sports health, music, sleep, dial, etc., and the embodiment of the present application is not particularly limited, and may depend on the specific application installed in the first processor, the specific functions and specific usage scenarios of each application, etc.

The first processor is an AP for example, applications such as music, dials and the like for initiating the service request, and the first processor is an MCU for example, applications such as heart rate, pedometer, sports health, music, sleep, dials and the like for initiating the service request.

In some embodiments, the purpose of an application to access memory through a service request may include, but is not limited to, one or more of reading data in memory, writing data to memory, modifying data in memory, and the like, as embodiments of the present application are not limited in detail and may depend on the specific function and specific use scenario of the application, and the like.

In some embodiments, the purpose of an application to access memory through a service request may include, but is not limited to, accessing a partition corresponding to a first processor and not corresponding to a second processor (i.e., an exclusive partition of the first processor), and/or a partition corresponding to the first processor and the second processor (i.e., a shared partition of the first processor and the second processor).

Wherein the exclusive partition of the first processor is configured to store data from the first processor and may support the first processor to read data stored in the exclusive partition of the first processor, the exclusive partition of the first processor being incapable of storing data from other processors (e.g., the second processor) and being incapable of supporting the other processors to read data stored in the exclusive partition of the first processor. The shared partition may store data from the first processor and support the first processor to read data stored in the shared partition, but may also store data from other processors (e.g., the second processor) and support other processors to read data stored in the shared partition.

In some embodiments, the memory may also include an exclusive partition of the second processor. Wherein the exclusive partition of the second processor is configured to store data from the second processor and may support the second processor to read data stored in the exclusive partition of the second processor, the exclusive partition of the second processor being incapable of storing data from other processors (e.g., the first processor) and being incapable of supporting the other processors to read data stored in the exclusive partition of the second processor.

S902, the first processor acquires the condition that the second processor accesses the memory.

In some embodiments, the first processor may obtain second information, where the second information is used to characterize a situation in which the second processor accesses memory, such as whether the second processor is accessing memory.

As a possible implementation, as shown in fig. 9, the first processor may obtain, from the second processor, a case where the second processor accesses the memory, e.g., obtain, from the second processor, second information indicating whether the second processor accesses the memory.

As an example, the first processor includes a first pin and the second processor includes a second pin, the first pin being connected to the second pin, the first processor may obtain the second information by obtaining a state of the first pin, i.e., obtaining whether the second processor is accessing the memory. Wherein the state of the first pin is used to characterize whether the second processor is accessing memory. For example, the state of the first pin may be represented by a level, such as the state of the first pin including a first level and a second level.

For example, if the state of the first pin is at a first level, it is determined that the second processor is accessing the memory, and if the state of the first pin is at a second level, it is determined that the second processor is not accessing the memory. The first level is, for example, a high level, the second level is, for example, a low level, or the first level is, for example, a low level, and the second level is, for example, a high level, which is not particularly limited.

It will be appreciated that, assuming that the second processor does not access the memory, the second processor may set the state of the second pin to a fourth level, and the state of the first pin of the first processor connected to the second pin is a second level when the state of the second pin is the fourth level, based on which, if the state of the first pin is the second level, the first processor may determine that the state of the second pin is the fourth level and thus determine that the second processor does not access the memory. And assuming that the second processor is accessing the memory, the second processor may set the state of the second pin to a third level, and the state of the first pin of the first processor connected to the second pin is a first level when the state of the second pin is the third level, based on which, if the state of the first pin is the first level, the first processor may determine that the state of the second pin is the third level and thus determine that the second processor is accessing the memory. The third level is, for example, a high level, the fourth level is, for example, a low level, or the third level is, for example, a low level, the fourth level is, for example, a high level, which is not particularly limited.

As another possible implementation manner, the first processor may directly obtain from the storage driver of the other processor of the terminal device such as the second processor whether the other processor is accessing the memory, or the first processor may obtain from another module independent of the first processor and the second processor, such as the state storage unit, whether the other processor is accessing the memory.

As an example, as shown in fig. 9, a state storage unit may be included in the terminal device, where the state storage unit is configured to store a state flag bit for each processor to access the memory, e.g., store a state flag bit for identifying whether each processor is accessing the memory, and the first processor may obtain, from the state storage unit, a case where the second processor accesses the memory, e.g., obtain, from the state storage unit, second information indicating whether the second processor accesses the memory.

For example, during a second processor writing data to the memory or reading data from the memory in response to a service request of an application, a second flag may be stored in the state storage unit, wherein the second flag is used to identify that the second processor is accessing the memory, based on which during the second processor accessing the memory, the first processor may obtain the state flag bit from the state storage unit and determine that the second processor is accessing the memory based on the state flag bit (e.g., the second identification). Or when the second processor accesses the memory, the second flag is not saved in the state storage unit to indicate that the second processor does not access the memory, and based on this, the first processor may obtain the state flag bit from the state storage unit and determine that the second processor does not access the memory according to the state flag bit (e.g., excluding the second flag).

With respect to the specific manner and specific procedure of the case where the first processor acquires the second processor access to the memory at S902, embodiments of the present application are not particularly limited.

In addition, embodiments of the present application are not limited to a particular form of information that characterizes the case where the second processor accesses memory. For example, in some examples, the information (e.g., the second information) used to characterize the condition of the second processor accessing the memory may be in a plaintext form such as a direct indication, and in other examples, the information (e.g., the second information) used to characterize the condition of the second processor accessing the memory may be in a implicit form such as a parameter characterization such as a level indication, a preset action (e.g., no reply) characterization, etc., and embodiments of the present application are not limited in detail.

In some embodiments, the result of the execution of S902 is that the second processor does not access memory (e.g., the second information characterizes that the second processor does not access memory), for which case the first processor executes S903 shown in fig. 9.

The first processor accesses the memory in response to the service request S903.

Wherein the specific operation of the first processor to access the memory in response to the service request is related to the purpose of the application to access the memory via the service request. For example, assuming that the purpose of an application accessing the memory via a service request is to read first data in the memory, the first processor reads the first data that the application wants to read from the memory in response to the service request. As another example, assuming that the purpose of the application accessing the memory via the service request is to write second data to the memory, the first processor writes the second data that the application wants to write to the memory in response to the service request. As another example, assuming that the purpose of the application accessing the memory via the service request is to modify the third data in the memory, the first processor modifies the third data in the memory in response to the service request.

In some embodiments, the first processor may set the state of the third pin such that the state of the third pin is a fifth level when the first processor accesses the memory, wherein the state of the third pin is the fifth level used to characterize the first processor as accessing the memory. As one possible implementation, after determining that the second processor does not access the memory based on the execution result of S902, before the first processor accesses the memory, the first processor may adjust the state of the third pin from the sixth level to the fifth level, where the state of the third pin is the sixth level to indicate that the first processor does not access the memory. Based on the method, other processors can conveniently know that the first processor is accessing the memory, so that conflicts caused by the fact that a plurality of processors access the memory simultaneously are prevented, and more scientific and ordered sharing of the memory is realized.

In some embodiments, after S903 is performed, that is, after the first processor finishes accessing the memory, the first processor may reset the state of the third pin such that the state of the third pin is a sixth level when the first processor does not access the memory. Based on this, it may be convenient for other processors to know that the first processor does not access memory, to achieve a more scientific, ordered sharing of memory.

In some embodiments, the result of the execution of S902 is that the second processor is accessing memory (e.g., the second information characterizes that the second processor is accessing memory), for which case the first processor temporarily does not access memory and acquires the second processor again to access memory after a period of time has elapsed, and when the second processor does not access memory, S903 shown in fig. 10 is executed. The first processor may acquire the second processor access to the memory again through S1001 shown in fig. 10:

s1001, the first processor acquires the condition that the second processor accesses the memory.

In some embodiments, the first processor may obtain first information, where the first information is used to characterize a situation in which the second processor accesses memory, such as whether the second processor is accessing memory.

As a possible implementation, as shown in fig. 10, the first processor may obtain, from the second processor, a case where the second processor accesses the memory, e.g., obtain, from the second processor, first information indicating whether the second processor accesses the memory.

As an example, the first processor may obtain the second information by obtaining the state of the first pin, i.e. obtaining whether the second processor is accessing the memory. For example, if the state of the first pin is at the second level, the first processor may determine that the second processor is not accessing the memory, and if the state of the first pin is at the first level, the first processor may determine that the second processor is accessing the memory. The first level is, for example, a high level, the second level is, for example, a low level, or the first level is, for example, a low level, and the second level is, for example, a high level, which is not particularly limited.

As another possible implementation manner, as shown in fig. 10, a state storage unit may be included in the terminal device, where the state storage unit is configured to store a status flag bit for each processor to access the memory, for example, to store a status flag bit for identifying whether each processor is accessing the memory, and the first processor may obtain, from the state storage unit, a case where the second processor accesses the memory, for example, obtain, from the state storage unit, first information indicating whether the second processor accesses the memory.

For example, if the status flag bit includes a second identification, the first processor may determine that the second processor is accessing memory, and if the status flag bit does not include the second identification, the first processor may determine that the second processor is not accessing memory.

It should be noted that embodiments of the present application are not limited to a specific form of information for characterizing the case where the second processor accesses the memory. For example, in some examples, the information (e.g., the first information) used to characterize the condition of the second processor accessing the memory may be in a plaintext form such as a direct indication, and in other examples, the information (e.g., the first information) used to characterize the condition of the second processor accessing the memory may be in a implicit form such as a parameter characterization such as a level indication, a preset action (e.g., no reply) characterization, etc., and embodiments of the present application are not limited in detail.

As a possible implementation, if the second processor is accessing the memory as a result of the execution of S902 (e.g., the second information indicates that the second processor is accessing the memory), the first processor may temporarily not access the memory, and periodically obtain the first information at a certain period T (e.g., every 100 ms), e.g., obtain the first information from the second processor or the state storage unit. Based on this, when the second processor finishes accessing the memory, the first processor may determine that the second processor does not access the memory based on the acquired first information, and then S903 is performed, or when the second processor does not finish accessing the memory, the first processor determines that the second processor is accessing the memory based on the acquired first information, and then continues to acquire the first information from the second processor according to the period T and periodicity.

As another possible implementation, if the result of the execution of S902 is that the second processor is accessing the memory (e.g., the second information indicates that the second processor is accessing the memory), the first processor may instruct the second processor to notify the first processor after ending the access to the memory. For example, the first processor may turn on the interrupt monitoring function, wherein after the interrupt monitoring function is turned on, the second processor actively notifies the first processor after ending access to the memory. It can be appreciated that, compared to an implementation manner in which the first processor periodically acquires the first information, the implementation manner can avoid waste of power consumption, processing resources and the like caused by the fact that the first processor continuously acquires the first information to the terminal device.

As another possible implementation, if the second processor is accessing the memory as a result of the execution of S902 (e.g., the second information indicates that the second processor is accessing the memory), the first processor may wait for a period of time, e.g., wait for a preset period of time (e.g., 5 ms), and then acquire the first information, e.g., acquire the first information from the second processor or the state storage unit. Based on this, when the second processor finishes accessing the memory, the first processor may determine that the second processor does not access the memory based on the acquired first information, and then S903 is performed, or when the second processor does not finish accessing the memory, the first processor determines that the second processor is accessing the memory based on the acquired first information, and then continues to acquire the first information from the second processor according to the period T and periodicity. It can be appreciated that, compared to an implementation manner in which the first processor periodically acquires the first information, the implementation manner can avoid waste of power consumption, processing resources and the like caused by the fact that the first processor continuously acquires the first information to the terminal device.

With respect to the specific manner and specific procedure of the case where the first processor acquires the second processor access to the memory at S1001, the embodiment of the present application is not particularly limited.

It should be noted that fig. 9 and fig. 10 only take the terminal device including the first processor and the second processor as an example, and the embodiment of the present application does not limit the number of processors sharing the same memory in the terminal device. For example, in some embodiments, the terminal device includes a third processor that is different from the first processor and the second processor, in which case the first processor would acquire the third processor access to memory in addition to the second processor access to memory. Further, the first processor executes S903 shown in fig. 9 when none of the other processors, such as the second processor and the third processor, access the memory, and the first processor temporarily does not access the memory when there is a processor in the other processors until it is determined that none of the other processors, such as the second processor and the third processor, access the memory based on the execution result of S1001 shown in fig. 10, and executes S903 shown in fig. 10.

As an example, referring to fig. 11, fig. 11 is a flowchart illustrating a process of accessing a memory by a first processor according to an embodiment of the present application. As shown in fig. 11, the process of accessing the memory may include S1101-S1108:

s1101, the first processor receives a service request to access the memory.

In some embodiments, the service request may be a request initiated by an application in the first processor, such as an application including, but not limited to, any one or more of music, heart rate, pedometer, sports health, music, sleep, dial, and the like.

In some embodiments, the purpose of the service requester may include, but is not limited to, one or more of reading data in the memory, writing data to the memory, modifying data in the memory, and embodiments of the present application are not specifically limited. For example, the purpose of the service requester may include, but is not limited to, one or more of reading data in an exclusive partition of the first processor in memory, reading data in a shared partition in memory, writing data in an exclusive partition of the first processor in memory, writing data in a shared partition in memory, modifying data in an exclusive partition of the first processor in memory, modifying data in a shared partition in memory.

S1102, the first processor triggers file operation.

As an example, the first processor triggers a file operation to trigger a specific access operation, such as a write, read, etc.

As an example, if the purpose of the service request is a read, the first processor may trigger a read operation, such as the first processor may invoke a read instruction, and if the purpose of the service request is a write, the first processor may trigger a read and write operation, such as the first processor may invoke a write instruction.

S1103 the first processor invokes a storage drive.

As one example, a first processor invokes a storage drive to obtain access to memory from other processors (e.g., a second processor).

In some embodiments, the first processor includes a first pin on a memory driver, the state of the first pin being used to characterize whether a memory (e.g., a second processor) to which a second pin coupled to the first pin belongs is accessing the memory. Based on this, the first processor may invoke the memory driver to fetch the state of the first pin to fetch whether other processors (e.g., the second processor) are accessing memory based on the state of the first pin.

As an example, the first pin or the second pin, such as a GPIO pin, although the first pin or the second pin may be other pins, embodiments of the present application are not limited in detail.

Of course, embodiments of the present application are not limited to the particular manner in which a first processor invokes a storage drive to obtain access to memory from other processors (e.g., a second processor). For example, in some embodiments, a first processor invokes a storage drive to fetch status flag bits from a status storage unit that characterize whether other processors (e.g., second processors) are accessing memory, to fetch whether other processors (e.g., second processors) are accessing memory based on the status flag bits.

The example of fig. 11 of the present application only takes the way in which the first processor invokes the memory driver to acquire the state of the first pin, to acquire whether other processors are accessing memory based on the state of the first pin as an example.

The first processor determines whether the state of the first pin is the second level S1104.

As an example, the first processor may determine that the state of the second pin is at a third level and thus determine that the second processor is accessing the memory, or the first processor may determine that the state of the second pin is at a fourth level and thus determine that the second processor is not accessing the memory.

In some examples, the first processor determines that the state of the first pin is at the second level at S1104, thereby determining that the second processor does not access memory. In this case, the first processor may normally access the memory, so that in order to facilitate the other processor (e.g., the second processor) to know that the first processor is accessing the memory during the process of accessing the memory by the first processor, the first processor may inform the other processor (e.g., the second processor) of its accessing the memory by setting the pin state. For example, when the first processor determines that the state of the first pin is the second level at S1104, the first processor performs the following S1105-S1108:

S1105 the first processor sets the state of the third pin to a fifth level.

In some embodiments, a third pin is included on the memory drive of the first processor, the state of the third pin being used to characterize the condition of the first processor accessing memory, such as to characterize whether the first processor is accessing memory. Based on this, the first processor may set the state of the third pin to a state that characterizes the first processor is accessing memory prior to accessing memory.

As an example, the state of the third pin is a sixth level to indicate that the first processor is not accessing memory, and the state of the third pin is a fifth level to indicate that the first processor is accessing memory. Based on the method, after determining that the second processor does not access the memory and before the first processor accesses the memory, the first processor can adjust the state of the third pin from the sixth level to the fifth level, so that other processors can know that the first processor is accessing the memory, and conflicts caused by simultaneous access of a plurality of processors to the memory are prevented, and more scientific and ordered sharing of the memory is realized.

S1106, the first processor judges whether the state of the first pin is the second level.

In some embodiments, to avoid a conflict caused by the second processor starting to access the memory after the first processor determines that the state of the first pin is at the second level based on S1104, and further determines that the second processor does not access the memory, the first processor may determine whether the state of the first pin is at the second level again to confirm that the second processor does not access the memory again.

S1107, the first processor accesses the memory.

S1108, the first processor sets the state of the third pin to a sixth level.

The third pin is in a sixth level and used for representing that the first processor does not access the memory, based on the sixth level, other processors can conveniently know that the first processor does not access the memory, so that the other processors can access the memory in time when the memory access requirement exists, and more scientific and ordered memory sharing is achieved.

It should be noted that the above embodiment takes only the first processor determining that the state of the first pin is the second level based on S1104, and further determining that the second processor does not access the memory as an example. In other examples, as shown in fig. 11, if the first processor determines that the state of the first pin is not the second level, such as the first level, based on S1104, the first processor may perform the subsequent processing in any one of the following three manners (manners 1-3):

mode 1 re-executing S1104 and executing S1105-S1108 when the state of the first pin is the second level.

For example, the first processor may periodically perform S1104 at a certain period T (e.g., every 100 ms) until S1105-S1108 are performed after determining the state of the first pin to be the second level.

Based on this, the first processor may temporarily not access the memory, and access the memory again by re-executing S1104 when it is ensured that the other second processors do not access the memory, so as to prevent conflicts caused by simultaneous access of multiple processors to the memory, thereby realizing more scientific and orderly sharing of the memory.

Mode 2S 1104 to S1108 are re-executed after S1109 to S1110 are executed.

Wherein, S1109-S1110 are specifically as follows:

The first processor initiates an interrupt monitoring function S1109.

After the interrupt monitoring function is started, the second processor actively notifies the first processor after the access to the memory is finished. For example, the second processor may notify the first processor that the second processor has finished accessing the memory by adjusting the state of the second pin to the fourth level after finishing the access to the memory. Or the second processor may notify the first processor that the second processor has finished accessing the memory by sending a reminder or the like after finishing accessing the memory. The embodiment of the application is not limited to a specific mode.

The interrupt detection function prompts the state of the first pin to be at the second level S1110.

Based on the method, the first processor can temporarily not access the memory, and access the memory when other second processors do not access the memory is ensured by starting the interrupt monitoring function, and the conflict caused by that a plurality of processors access the memory simultaneously is prevented when the service request is responded to access the memory in time, so that more scientific and ordered memory sharing is realized.

And, compared with the mode 1, the mode 2 can avoid the waste of power consumption, processing resources and the like brought to the terminal equipment by the condition that the first processor continuously acquires the second processor to access the memory.

Mode 3S 1104-S1108 are re-executed after S1111-S1112 are executed.

Wherein, S1111-S1112 are specifically as follows:

S1111, first processor start-up latency.

Illustratively, the wait time is, for example, a wait for a preset duration, for example, 5 milliseconds.

S1112, waiting for more than a preset time period.

Based on the method, the first processor can temporarily not access the memory, and access the memory again when other second processors are not accessed to the memory is ensured in a mode of waiting for judging again after the preset time period is exceeded, so that conflicts caused by simultaneous access of a plurality of processors to the memory are prevented, and more scientific and ordered sharing of the memory is realized.

And, compared with the mode 1, the mode 3 can avoid the waste of power consumption, processing resources and the like brought to the terminal equipment by the condition that the first processor continuously acquires the second processor to access the memory.

In addition, it should be noted that the above embodiment takes only the first processor determining that the state of the first pin is the second level based on S1106, and further determining that the second processor does not access the memory as an example. In other examples, as shown in fig. 11, if the first processor determines that the state of the first pin is not the second level, such as the first level, based on S1106, the first processor may perform the subsequent processing in any of the above-described modes 1 to 3, which is not repeated here.

It can be understood that, based on the method for accessing a memory provided by the present application, as shown in fig. 9 and fig. 10, multiple processors (such as a first processor and a second processor) of a terminal device can ensure that any processor can normally perform data storage, modification or reading of stored data, etc. under any use scenario by sharing the same memory. For example, compared with an architecture in which the MCU stores MCU-related data by means of a memory configured for the AP, even if the AP and the memory configured for the AP are powered down in a low power mode, the storage of MCU-related data and the normal reading, modification, deletion, etc. of stored data can be performed normally. And any one of the plurality of processors (such as the first processor) can realize exclusive access of the plurality of processors to the memory based on the acquired condition that other processors access the memory, such as the condition that whether the other processors are accessing the memory, so as to realize more scientific and ordered sharing of the memory.

And the scheme that the plurality of processors (such as the first processor and the second processor) of the terminal equipment share the same memory can also reduce the production cost of the terminal equipment and provide support for the miniaturization of the terminal equipment.

In addition, since the multiple processors (such as the first processor and the second processor) of the terminal device share the same memory, when one processor writes one data (such as the data of music a) into the memory, the other processor knows that the data has been written into the memory, and when the other processor receives a service request for writing the same data into the memory, the processor can not repeatedly write the same data but normally feed back a message of successful writing to the application. Based on this, the problem of repeated writing of data of some applications related to a plurality of processors (e.g., AP and MCU) can be avoided.

The embodiment of the present application is not limited to the specific processor manner adopted when the first processor determines that the state of the first pin is not at the second level based on S1104, and the first processor may perform the subsequent processing in any of the above-described manners 1 to 3, and the embodiment of the present application is not limited to the specific processor manner adopted when the first processor determines that the state of the first pin is not at the second level based on S1106, and the first processor may perform the subsequent processing in any of the above-described manners 1 to 3, depending on the specific device capability, power consumption requirement, service requirement, usage scenario, and the like.

And, it should be noted that the above embodiment takes the first processor executing S1106 after S1105 is executed, executing S1107-S1108 based on the execution result of S1106, executing S1107-S1108 based on the execution result of S1109-S1110, or executing S1111-S1112 based on the execution result of S1106 as an example. The present application is not limited to whether the first processor performs S1106 after S1105 is performed, that is, S1106 is not an essential step, for example, in some embodiments, the first processor may directly perform S1107-S1108 after S1105 is performed.

It is to be understood that the various aspects of the embodiments of the application may be used in any reasonable combination, and that the explanation or illustration of the various terms presented in the embodiments may be referred to or explained in the various embodiments without limitation.

It should also be understood that, in various embodiments of the present application, the sequence numbers of the foregoing processes do not mean the order of execution, and the order of execution of the processes should be determined by the functions and internal logic thereof, and should not constitute any limitation on the implementation process of the embodiments of the present application.

It will be appreciated that, in order to implement the functions of any of the above embodiments, a terminal device or the like includes corresponding hardware structures and/or software modules that perform the respective functions. Those of skill in the art will readily appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as hardware or combinations of hardware and computer software. Whether a function is implemented as hardware or computer software driven hardware depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.

The embodiment of the application can divide the functional modules of the terminal equipment and the like, for example, each functional module can be divided corresponding to each function, and two or more functions can be integrated in one processing module. The integrated modules may be implemented in hardware or in software functional modules. It should be noted that, in the embodiment of the present application, the division of the modules is schematic, which is merely a logic function division, and other division manners may be implemented in actual implementation. It should also be understood that each module in the terminal device and the like may be implemented in software and/or hardware, which is not particularly limited. In other words, the terminal device or the like is presented in the form of a functional module. A "module" herein may refer to an application specific integrated circuit ASIC, an electronic circuit, a processor and memory that execute one or more software or firmware programs, an integrated logic circuit, and/or other devices that can provide the described functionality.

In an alternative, when data transmission is implemented using software, it may be implemented wholly or partly in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the processes or functions described in the embodiments of the present application are fully or partially implemented. The computer may be a general purpose computer, a special purpose computer, a computer network, or other programmable apparatus. The computer instructions may be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another computer-readable storage medium, for example, the computer instructions may be transmitted from one website, computer, server, or data center to another website, computer, server, or data center by wired (e.g., coaxial cable, fiber optic, digital subscriber line ((digital subscriber line, DSL)), or wireless (e.g., infrared, wireless, microwave, etc.), the computer-readable storage medium may be any available medium that can be accessed by the computer or a data storage device such as a server, data center, etc., that contains an integration of one or more available media, the available media may be magnetic media, (e.g., floppy disk, hard disk, tape), optical media (e.g., digital versatile disk (digital video disk, DVD)), or semiconductor media (e.g., solid state disk Solid STATE DISK (SSD)), etc.

The steps of a method or algorithm described in connection with the embodiments disclosed herein may be embodied in hardware or in software instructions executed by a processor. The software instructions may be comprised of corresponding software modules that may be stored in random access memory (random access memory, RAM), flash memory, read Only Memory (ROM), erasable Programmable Read Only Memory (EPROM), electrically erasable read only memory (ELECTRICALLY ERASABLE PROGRAMMABLE READ-only memory, EEPROM) memory, registers, hard disk, a removable disk, a compact disc read only memory (compact disc read-only memory, CD-ROM), or any other form of storage medium known in the art. An exemplary storage medium is coupled to the processor such the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium may be integral to the processor. The processor and the storage medium may reside in an Application Specific Integrated Circuit (ASIC). In addition, the ASIC may reside in a terminal device. The processor and the storage medium may reside as discrete components in the case of a processor.

From the foregoing description of the embodiments, it will be apparent to those skilled in the art that, for convenience and brevity of description, only the above-described division of functional modules is illustrated, and in practical application, the above-described functional allocation may be implemented by different functional modules according to needs, i.e. the internal structure of the apparatus is divided into different functional modules to implement all or part of the functions described above.

Claims

1. A method of accessing a memory, the method being applied to a first processor in a terminal device, the terminal device further comprising a second processor and a memory, the first processor and the second processor sharing the memory, the method comprising:

receiving a service request of an application, wherein the service request is used for requesting to access the memory;

obtaining first information from the second processor, the first information being used to characterize whether the second processor is accessing the memory;

And accessing the memory in response to the service request when the first information characterizes that the second processor does not access the memory.

2. The method of claim 1, wherein the first processor includes a first pin, the first pin being coupled to a second pin of the second processor, the obtaining first information from the second processor comprising:

The state of the first pin is obtained and used for representing whether the second processor is accessing the memory.

3. The method of claim 2, wherein the state of the first pin comprises a first level and a second level, the method further comprising:

if the state of the first pin is a first level, determining that the second processor is accessing the memory;

if the state of the first pin is the second level, determining that the second processor does not access the memory.

4. The method of claim 3, wherein the step of,

When the state of the second pin is a third level, the state of the first pin is a first level;

when the state of the second pin is the fourth level, the state of the first pin is the second level.

5. The method of any of claims 1-4, wherein the first processor further comprises a third pin, a state of the third pin being indicative of whether the first processor is accessing the memory.

6. The method of claim 5, wherein the step of determining the position of the probe is performed,

The state of the third pin is a fifth level when the first processor accesses the memory, and the state of the third pin is a sixth level when the first processor does not access the memory.

7. The method of claim 6, wherein the method further comprises:

the state of the third pin is adjusted from the sixth level to the fifth level before the first processor accesses the memory.

8. The method of claim 7, wherein said adjusting the state of the third pin from the sixth level to the fifth level comprises:

After receiving the service request, obtaining second information from the second processor, the second information being used to characterize whether the second processor accesses the memory;

When the second information characterizes that the second processor does not access the memory, the state of the third pin is adjusted from the sixth level to the fifth level.

9. The method of claim 8, wherein the obtaining first information from the second processor comprises:

And when the second information represents that the second processor is accessing the memory, acquiring the first information from the second processor after waiting for a preset time period.

10. The method of any of claims 1-9, wherein the service request is to request access to one or more partitions in the memory that correspond to the first processor and that do not correspond to the second processor, partitions that correspond to the first processor and the second processor.

11. The method of claim 10, wherein the memory further comprises a partition corresponding to the second processor and not corresponding to the first processor.

12. The method according to any one of claims 1 to 11, wherein,

The first processor accesses the memory for one or more of reading data in the memory, writing data to the memory, and modifying data in the memory.

13. The method according to any one of claims 1 to 12, wherein,

The first processor is an Application Processor (AP), and the second processor is a micro program controller (MCU), or the first processor is an MCU, and the second processor is an AP;

wherein, the memory is an embedded multimedia memory card eMMC.

14. A chip, the chip comprising: a processing module and one or more pins for supporting the chip to implement the method of any one of claims 1-13.

15. A terminal device, characterized in that it comprises a first processor, a second processor and a memory, the first processor and the second processor sharing the memory, the first processor or the second processor being adapted to implement the method according to any of claims 1-13.

16. A computer readable storage medium, characterized in that it has stored thereon computer program instructions which, when executed by a processing circuit, implement the method according to any of claims 1-13.

17. A computer program product comprising instructions which, when run on a computer, cause the computer to perform the method of any of claims 1-13.