CN113904970B

CN113904970B - Transmission system and method of semiconductor test equipment

Info

Publication number: CN113904970B
Application number: CN202111500720.0A
Authority: CN
Inventors: 晏佳; 白静
Original assignee: Wayne Testing Technology Wuhan Co ltd
Current assignee: Wayne Testing Technology Wuhan Co ltd
Priority date: 2021-12-09
Filing date: 2021-12-09
Publication date: 2022-03-01
Anticipated expiration: 2041-12-09
Also published as: CN113904970A

Abstract

The application discloses a transmission system and a method of semiconductor test equipment, which relate to the technical field of automatic test equipment ATE data transmission, wherein the transmission system comprises a communication board, a PCIe optical fiber board card at the upstream of the communication board and a plurality of backplanes at the downstream of the communication board; the communication board is integrated with a plurality of different communication modules, the different communication modules are provided with a plurality of test channels and support different maximum bandwidths, and each communication module communicates independently or communicates with each other on the board; meanwhile, the PCIe fiber board card is connected with the selected communication module, and each backboard is connected with each test channel in the selected communication module and has bandwidth matching; if the number of the selected communication modules is one, the communication modules independently communicate; and if two communication modules are selected, the two communication modules are communicated with each other. The application provides a transmission system and a transmission method of semiconductor test equipment, which aim to solve the technical problems that in the related technology, the transmission capability of a system frame of ATE equipment is single, and different transmission bandwidths cannot be met.

Description

Transmission system and method of semiconductor test equipment

Technical Field

The present disclosure relates to the field of ATE data transmission technologies, and in particular, to a transmission system and method for a semiconductor test device.

Background

With the continuous development and improvement of chip technology, the capability of automatic Test equipment (ate) to Test chips needs to be improved. In general, the system architecture, transmission bandwidth, and the like of ATE devices vary greatly according to the test objects.

At present, the demand of ATE equipment for high-speed transmission is increasing, however, the system framework of the conventional ATE equipment mainly has a PC end and an ATE equipment host.

If the PC and the ATE device host use PCI buses, and the bandwidth of the ordinary PCI bus is about 132MB/s (when the clock is 33 MHz) or 264MB/s (when the clock is 66 MHz), it is difficult to meet the bandwidth requirement in some scenarios with large data volume, and the transmission capability is also limited.

If a certain distance exists between the PC end and the ATE equipment host, the parallel cable is independently used as a connecting bridge, and the possibility of generating data error codes is caused due to the fact that the anti-interference capability of a long-distance parallel bus is weak, so that the test is inaccurate.

It can be seen that the transmission capability of the system framework of the existing ATE device is limited, and certain defects exist in the accuracy of testing or the satisfaction of different transmission bandwidths. How to design a new ATE equipment system framework can meet different transmission bandwidths to meet the test requirements of multiple functions, multiple test channels and the like of future chip tests.

Disclosure of Invention

Embodiments of the present application provide a transmission system and method for semiconductor test equipment, so as to solve the technical problems that in the related art, the transmission capability of a system framework of ATE equipment is limited, and different transmission bandwidths and high-speed transmission cannot be satisfied.

In a first aspect, a transmission system of semiconductor test equipment is provided, which includes a communication board, a PCIe fiber board card upstream of the communication board, and a plurality of backplanes downstream of the communication board;

the communication board is integrated with a plurality of different communication modules, the different communication modules are provided with a plurality of test channels and support different maximum bandwidths, and each communication module communicates independently or communicates with each other on the board;

meanwhile, the PCIe fiber board card is connected with the selected communication module, and each backboard is connected with each test channel in the selected communication module and is matched with the bandwidth so as to distribute larger bandwidth data to each backboard or gather smaller bandwidth data on each backboard; wherein,

if the number of the selected communication modules is one, the communication modules independently communicate;

and if two communication modules are selected, the two communication modules are communicated with each other.

In some embodiments, if the PCIe fiber board has a high-speed interface, one communication module is an optical communication module, and the communication module supports high-speed serial transmission; and/or

If the PCIe optical fiber board card has a parallel interface, one communication module is an LVDS communication module, and the communication module supports parallel transmission.

In some embodiments, if the backplane has a high-speed interface, all of the high-speed interfaces of the backplane are configured to connect to the optical communication module;

if the backplane has parallel interfaces, all the parallel interfaces of the backplane are configured to be connected to the LVDS communication module.

In some embodiments, an ARM core for porting an operating system is further integrated on the optical communication module.

In some embodiments, the PCIe fiber board card is inserted into a PCI-E X8 slot on the PC side, and the communication board is provided on the ATE device host.

In some embodiments, the PC terminal iteratively reads configuration spaces of all PCIe fiber boards in an operating processor system according to a PCIe bus number, a device name, and a function number through a PCIe driver during a boot process, where the configuration spaces are located in an XDMA core of the PCIe fiber boards; comparing the Vendor ID field and the Device ID field in the configuration space with the Vendor ID and the Device ID of the PCIe optical fiber board card to be searched, and if the two fields are equal, successfully searching; initializing the base address register space of the PCIe optical fiber board card after the PCIe optical fiber board card is searched successfully; and after the initialization is completed, data transmission is carried out.

In some embodiments, the communication module takes an FPGA chip as a core; and/or the backboard also takes the FPGA chip as a core.

In some embodiments, a plurality of functional boards are inserted in the backplane, and the functional boards are communicatively connected to the backplane through a standard LVDS interface.

In some embodiments, the communication board further has integrated thereon a system power supply and a clock generator; and/or

And a system monitoring and power control module is further integrated on the communication board and is configured to monitor the operation condition of the ATE equipment host and control the system power supply.

In a second aspect, there is also provided a transmission method of the transmission system of the semiconductor test equipment, including the following steps:

according to the test requirement, a communication module is selected to be in adaptive connection with a part or all of the back boards at the downstream, and a communication module is selected to be in adaptive connection with the PCIe optical fiber board card at the upstream;

if one communication module is selected, the communication module independently communicates and distributes the larger bandwidth data of the PCIe optical fiber board card to each backboard or gathers the smaller bandwidth data on each backboard to the PCIe optical fiber board card;

and if two communication modules are selected, the two communication modules are communicated with each other, and the larger bandwidth data of the PCIe optical fiber board card is distributed to each backboard or the smaller bandwidth data on each backboard is gathered to the PCIe optical fiber board card.

The beneficial effect that technical scheme that this application provided brought includes:

different communication modules are modularly arranged on the communication board, so that the communication board can distribute and gather transmission data to take different transmission bandwidths of the different communication modules into consideration, and can selectively use one or more communication modules to perform communication connection according to the data transmission requirement, so that the communication board can take difference of upstream and downstream communication modes into consideration, meet different transmission bandwidth requirements and overcome the test capability limitation of ATE equipment.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.

Fig. 1 is a block diagram of a transmission system of a semiconductor test apparatus according to an embodiment of the present disclosure;

fig. 2 is a second block diagram of a transmission system of a semiconductor test apparatus according to an embodiment of the present disclosure;

fig. 3 is a schematic diagram of a specific architecture of a communication board;

fig. 4 is a schematic diagram of a connection architecture of a backplane and a functional board;

FIG. 5 is a schematic diagram of the architecture of a PCIe fiber board;

FIG. 6 is a logical schematic block diagram of an FPGA chip of a PCIe fiber board card;

FIG. 7 is a block diagram of a RTX real-time system based PCIe driven architecture;

FIG. 8 is a flowchart illustrating DMA read and write operations performed by a computer according to an embodiment.

The implementation, functional features and advantages of the objectives of the present application will be further explained with reference to the accompanying drawings.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some embodiments of the present application, but not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

The flow diagrams depicted in the figures are merely illustrative and do not necessarily include all of the elements and operations/steps, nor do they necessarily have to be performed in the order depicted. For example, some operations/steps may be decomposed, combined or partially combined, so that the actual execution sequence may be changed according to the actual situation.

The embodiment of the application provides a transmission system of semiconductor test equipment, different communication modules are modularly arranged on a communication board, so that the communication board can distribute and gather transmission data to take different transmission bandwidths of the different communication modules into consideration, and a single or a plurality of communication modules can be selectively used for communication connection according to the data transmission requirement, so that the communication board can take difference of upstream and downstream communication modes into consideration, different transmission bandwidth requirements are met, and the limitation of test capability of ATE (automatic test equipment) equipment is overcome.

Some embodiments of the present application will be described in detail below with reference to the accompanying drawings. The embodiments described below and the features of the embodiments can be combined with each other without conflict.

As shown in fig. 1, an embodiment of the present application provides a transmission system of a semiconductor test device, including a communication board, a PCIe fiber board card upstream of the communication board, and a plurality of backplanes downstream of the communication board;

According to the transmission system of the semiconductor test equipment, a communication module is selected to be in adaptive connection with a part or all of the downstream back plates supporting lower bandwidth, and a communication module is selected to be in adaptive connection with the upstream PCIe optical fiber board card supporting higher bandwidth according to actual test requirements; if one communication module is selected, the communication module independently communicates and distributes the larger bandwidth data of the PCIe optical fiber board card to each backboard or gathers the smaller bandwidth data on each backboard to the PCIe optical fiber board card device; and if two communication modules are selected, the two communication modules are communicated with each other, and the larger bandwidth data of the PCIe optical fiber board card is distributed to each backboard or the smaller bandwidth data on each backboard is gathered to the PCIe optical fiber board card.

Different communication modules are set as a first communication module and a second communication module with different communication modes, and the backboard is provided with a first backboard and a second backboard. The first communication module can be in communication connection with both the first backplane and the second backplane, and the second communication module can also be in communication connection with both the first backplane and the second backplane.

It is worth noting that the data transmission capability of a single backplane at the downstream of the communication board is limited, when the data transmission capability is improved, if the cost of the data transmission capability of the single board card is high and the research and development difficulty is high, and a plurality of test channels are arranged in each communication module to adapt to the bandwidth of the conventional backplane, the high bandwidth on the communication board is not wasted, and the requirement that a plurality of backplanes supporting lower bandwidth are tested at the same time can be met.

It is noted that the backplane and the communication module are communicatively connected through the same communication interface.

In a specific embodiment, the communication module has four test channels, and each test channel is interfaced with a corresponding interface on the backplane by one communication interface.

Preferably, if the PCIe fiber board has a high-speed interface, one communication module is an optical communication module, and the communication module supports high-speed serial transmission; and/or

Furthermore, the communication module takes an FPGA chip as a core; and/or the backboard also takes the FPGA chip as a core. The FPGA chip with stronger transmission capability is selected, the speed is greatly improved, and the speed improvement can be realized by basically making small correction on FPGA control logic, so that the embodiment of the application has strong plasticity.

The communication board is integrated with an optical communication module and an LVDS communication module, wherein both the optical communication module and the LVDS communication module can communicate with upstream and downstream devices. In this embodiment, the four test channels of the optical communication module are respectively connected with the four backplanes one by one through high-speed interfaces, an FPGA chip is adopted, and the Tranceiver rate of the chip is 12.5Gbps/Lane at the lowest.

Or the four testing channels of the LVDS communication module are respectively connected with the four backplanes one by one through parallel interfaces to realize that the LVDS communication module and the backplanes communicate through the LVDS technology, an FPGA core is adopted, and the Tranceiver rate of the chip is 12.5Gbps/Lane at the lowest.

Further, if the backplane has a high-speed interface, all of the high-speed interfaces of the backplane are configured to be connected to the optical communication module;

Specifically, as shown in fig. 2 and 3, the PCIe fiber board card is inserted into a PCI-E X8 slot on the PC side, and the communication board is provided on the ATE device host.

In this embodiment, the communication board is located on the ATE device host, and connects the upstream PCIe fiber board card and the downstream four backplanes, where the PCIe fiber board card is at the PC end. The PCIe optical fiber board card is a PCIe3.0 optical fiber card, the external interface of the PCIe3.0 optical fiber card is an optical fiber interface QSFP +, namely a high-speed interface, the optical fiber interface supports 40Gbps bandwidth, and optical fibers matched with the data transmission rate are connected to the optical fiber interface QSFP + of the optical communication module for physical interconnection.

If the optical communication module is connected with the high-speed interface of the PCIe optical fiber board card at the upstream and connected with the high-speed interfaces of the four backplanes at the downstream, and the LVDS communication module is in an idle state, the optical communication module distributes 40Gbps light data to the four backplanes, the speed of one backplane and the communication board can reach 10Gbps, and meanwhile, the data on the four backplanes can be gathered and transmitted back to the PCIe optical fiber board card through optical fibers to be acquired by a PC end. It can be seen that the maximum transmission bandwidth of the whole transmission system is parallel four-way 10Gbps, and the total bandwidth is 40 Gbps.

The parallel interface of the PCIe optical fiber board card is connected to the LVDS communication module, and the LVDS communication module is connected to the parallel interface of the backplane, and the transmission principle of the LVDS optical fiber board card is similar to that of the optical communication module in independent communication, which is not described in detail herein.

It is worth noting that the distance between the PC end and the ATE equipment host may be very close or very far, if the data transmission is long-distance transmission, a high-speed interface of a PCIe optical fiber board card is preferably adopted for data transmission, so that the problem of poor anti-interference capability of cable connection in long-distance data transmission is avoided, and the quality of data transmission is ensured; if the transmission is in a short distance, on the premise that the bandwidth meets the test requirement, the parallel interface of the PCIe optical fiber board card is preferentially adopted for transmission, so that the test cost can be reduced.

Certainly, the LVDS communication module in the communication board may be connected to other upstream devices besides the PCIe fiber board card, for example, an old PCI bus may also be applicable, so that the transmission system has a more universal capability.

From the above description, it can be seen that the PCIe optical fiber board card on the upstream of the communication board has a high-speed interface and a parallel interface, and the backplane on the downstream also has a high-speed interface and a parallel interface, and if the interfaces on the upstream and the downstream are different, the optical communication module on the communication board further interconnects and communicates with the LVDS communication module, for example, a transmission path is: the PCIe optical fiber board card comprises a high-speed interface, an optical communication module, an LVDS communication module and a backboard.

Preferably, an ARM core for transplanting an operating system is further integrated on the optical communication module. After the ARM core transplants the operating system, board-level online data processing can be performed on the communication board, so that the processed data can be transmitted to the PC end, data transmission can be reduced, and transmission distortion is avoided.

As shown in fig. 4, a plurality of functional boards are inserted into the backplane, and the functional boards are communicatively connected to the backplane through a standard LVDS interface.

In this embodiment, functional boards with different functions can be inserted into one backplane, and the communication between the functional boards and the backplane adopts the LVDS communication technology at 1Gbps, so that the backplane can interact with more functional boards, and the function upgrade of the transmission system is accelerated.

In one embodiment, the backplane uses an FPGA chip as a control core and has a Hspeed Conn interface and an LVDS Conn interface, wherein the rate of the Hspeed Conn interface can reach 10Gbps and the LVDS Conn interface can reach 8Gbps, and if the two interfaces are used, the two interfaces are selected. The on-board Clock Generator on the back board provides a synchronous Clock for each function board besides providing a necessary working Clock for the FPGA chip on the board.

The communication modules on the communication board adopt a modularized design, and are flexibly configured according to the upstream and downstream board cards, so that the compatibility with the old board cards is realized, and the test cost is saved; the FPGA is adopted as a control core, so that the transmission system has high matching performance and design consistency in design, and the development time can be effectively reduced. Meanwhile, the number of connected back plates of the test channels on the communication module can be selected according to actual needs in actual use, so that different functional board cards are added, and flexible configuration of the test capability of the ATE equipment is realized.

The operation of the PCIe fiber board is described in detail below.

As shown in fig. 5, the PCIe fiber board channel type is PCI-E X8, the FPGA chip is used as a core, the FPGA chip has an external high-speed interface (i.e., fiber interface QSFP +) in fig. 5 and a parallel interface (i.e., Local Bus CN in fig. 5), and is externally connected to an internal memory (i.e., DDR4 in fig. 5) for data caching, where the parallel interface is connected to a Program Logic portion of the FPGA through an isolation chip, so that the FPGA chip is well protected and level conversion is completed.

The FPGA chip is integrated with a PCIe hard core, development software of the FPGA chip is provided with a plurality of PCIe IP implementation methods, and an XDMA core is adopted to realize PCIe protocol and DMA transmission. The FPGA chip realizes PCIe protocol and DMA transmission through an XDMA core, the XDMA core comprises an M _ AXI interface and an M-AXI-Lite interface, the M _ AXI interface is used for transmitting DMA data, and the M-AXI-Lite interface is used for accessing register data.

Referring to fig. 6, the user interface of the XDMA core is divided into an M _ AXI interface, which is transferring DMA data, and an M-AXI-Lite interface, which is accessing register data. The Register data is cached by a Register BRAM and is exchanged with the subsequent logic, and in addition, some control instructions of the subsequent logic are also generated by the Register data.

In order to fully utilize the advantages of high speed of serial data transmission and low time delay of parallel data transmission, the FPGA chip is connected with a high-speed interface or a parallel interface through a register switching communication link so as to realize high-speed serial transmission or parallel transmission.

When the high-speed interface is connected, DMA data enters a memory for caching, Register data is cached in a Register BRAM, and the DMA data or the Register read-write data is selected for data processing through a high-speed transmission control mechanism.

In this embodiment, when the optical fiber interface QSFP + is connected, in order to ensure that the Data rate of PCIe DMA Data and the optical fiber interface QSFP + is matched, the DMA Data may first enter the DDR4 for buffering, the Register Data may be buffered in the Register BRAM, and the DMA Data or the Register read-write Data is selected to be processed with the Data Process through a control mechanism of a High Speed Transmission Controller, where the processing of the Data Process is to perform packaging and unpacking processing according to a self-defined Data structure, so as to use an Aurora Transmission protocol, and finally, the Data is output from the optical fiber interface QSFP +.

When the parallel interface is connected, DMA data or register read-write data are selected to carry out data processing through a parallel transmission control mechanism.

In this embodiment, when the parallel interface Local Bus CN is connected, DMA Data or register read/write Data is selected to perform Data processing by the control mechanism of the Local Bus Transmission Controller. The Data Process is a parallel transmission interface which converts the transmitted Data and control signals into a parallel interface with Local Bus. The Local Bus interface is composed of 32-bit data lines, 24-bit address lines, and necessary control lines.

Preferably, the PC side iteratively reads configuration spaces of all PCIe fiber board cards in a running processor system according to PCIe bus numbers, device names and function numbers through a PCIe drive in the process of starting the computer, wherein the configuration spaces are positioned in an XDMA core of the PCIe fiber board cards; comparing the Vendor ID field and the Device ID field in the configuration space with the Vendor ID and the Device ID of the PCIe optical fiber board card to be searched, and if the two fields are equal, successfully searching; initializing the base address register space of the PCIe optical fiber board card after the PCIe optical fiber board card is searched successfully; and after the initialization is completed, data transmission is carried out.

In this embodiment, the computer controls the PCIe fiber board card based on the FPGA through the PCIe driver based on the RTX real-time system. The computer system is Windows, and since Windows is a non-real-time system and is realized based on PCIe drive of RTX real-time system, firstly, Windows can be reformed into a hard real-time operating system with definite response. The Windows-based RTX real-time extension subsystem developed by Ardence corporation is the first choice, mainly because the RTX is seamlessly compatible with the Windows operating system, and can utilize various advantages of the Windows system, including a large number of standard API functions, an efficient memory management mechanism, and various universal resources under Windows. As a complete Windows extension system, RTX does not make any encapsulation and modification to the Windows system architecture. Compared with the PCIe driver based on Windows, the implementation process of the PCIe driver based on RTX is simple and clear due to the API function provided by RTX. A schematic diagram of a PCIe driver based on the RTX real-time system is shown in fig. 7. The method comprises the steps of firstly searching a PCIe optical fiber board card, initializing a base address register space of the searched PCIe optical fiber board card after the PCIe optical fiber board card is successfully searched, and transmitting data after the initialization is completed. If the PCIe optical fiber board card is searched for unsuccessfully, exiting; and if the initialization fails, exiting.

The specific implementation of finding the PCIe fiber board card is that the configuration space of all PCIe fiber board cards is read iteratively in a running processor system according to PCIe bus numbers, Device names and function numbers, the Vendor ID field and the Device ID field in the configuration space are compared with the Vendor ID and the Device ID of the PCIe fiber board card to be found, if the two fields are equal, the two fields exist, and if the two fields are not equal, the finding fails, and the program exits.

When the XDMA IP core is configured, the FPGA of the PCIe fiber board card can change the Vendor ID field and the Device ID field of the PCIe Device, and when the Vendor ID fields and the Device ID fields of a plurality of PCI devices are consistent, the search fails.

The step of initializing the searched basic address register space of the PCIe optical fiber board card comprises the following steps:

and distributing the address space of the basic address register of the PCIe fiber board card in a PCIe bus domain.

In this embodiment, before data transmission of the PCIe fiber board card, the system software needs to initialize the BAR0-5 register of the PCIe fiber board card. The system software completes the initialization of the registers, namely the address space of the devices in the PCIe bus domain is distributed when the PCIe bus passes through. After the registers are initialized, the PCIe fiber board card can use the PCIe bus address to transmit data.

Addresses in the BAR (base address register) in the PCIe fabric are PCIe bus addresses, and these addresses have images in the memory domain of the processor system, and if the BAR space of one PCIe fabric is not imaged in the memory domain, the processor will not be able to access the BAR space of the PCIe fabric.

The processor isolates the PCIe bus domain from the memory domain through the HOST bridge. When the processor accesses the address control of the PCIe fiber board, it needs to access the address space of the device in the memory domain first, and after converting the address space of the memory domain into the address space of the PCIe bus domain through the HOST bridge, send the data to the designated PCIe fiber board using PCIe bus transaction.

Firstly, the address of the BAR space is converted into a physical address which can be directly accessed by the CPU, then the converted physical address is mapped to a virtual address which can be accessed by an application program, and after the converted physical address is mapped to the virtual address space, a user can normally read and write the memory space or the I/O space of the PCIe optical fiber board card.

If the communication board is connected with the communication board through the parallel interface, the step of transmitting data comprises the following steps:

the computer accesses the M-AXI-Lite interface user register of the XDMA core of the PCIe optical fiber board card and then accesses the LVDS communication module through the parallel interface.

In this embodiment, an application program in the computer accesses an M-AXI-Lite interface user register of the XDMA in the board card through a PCIe driver based on RTX, and then accesses the LVDS communication module through a Local Bus parallel interface, and thus, low latency is achieved in hardware, thereby ensuring real-time performance of the entire transmission link.

If the communication board is connected with the communication board through the high-speed interface, the step of transmitting data comprises the following steps:

the computer selects a transmission interface of the PCIe optical fiber board card as a high-speed interface, applies for a section of continuous memory space for DMA data transmission; creating a section of continuous memory space according to the size of the descriptor, and writing a descriptor base address; the DMA transfer is turned on.

As shown in fig. 8, a section of continuous memory space is applied for DMA data transmission; then, a section of continuous memory space is created according to the size of the descriptor; writing a descriptor base address, and starting DMA transmission; detecting whether the transmission is finished or not, and if not, continuing the transmission; if the DMA operation is finished, the DMA operation is stopped.

The PCIe optical fiber board fully utilizes a high-speed transmission interface and a parallel interface of the FPGA, takes the advantages of high-speed serial transmission and parallel transmission into account, provides two different external transmission modes, and ensures high speed and high real-time performance of transmission.

As shown in fig. 3, preferably, the communication board further integrates a system monitoring and power control module, which monitors the operation status of the ATE device host and controls the system power supply. The system monitoring and power control module detects whether the fan is abnormal or not and whether an emergency stop button is pressed or not after the ATE is started up, and the pneumatic control channel switching device feeds back necessary information to be displayed on the LED. In the running process of the ATE equipment host, the abnormality of the fan and the pressing of the emergency stop button enable signals on a Power Control interface Power Control CN to be effective, so that the system Power is turned off.

Still further, a System Power and Clock Generator is integrated on the communication board, and the System Power and Clock Generator provides Power for all modules on the communication board and also provides working clocks for all communication modules.

The embodiment of the application also provides a transmission method of the transmission system of the semiconductor test equipment, which comprises the following steps:

It should be noted that, as is clear to those skilled in the art, for convenience and brevity of description, the specific embodiment of the method may refer to the corresponding process in the foregoing system embodiment, and details are not described herein again.

In the description of the present application, it should be noted that the terms "upper", "lower", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, which are only for convenience in describing the present application and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed in a specific orientation, and operate, and thus, should not be construed as limiting the present application. Unless expressly stated or limited otherwise, the terms "mounted," "connected," and "connected" are intended to be inclusive and mean, for example, that they may be fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meaning of the above terms in the present application can be understood by those of ordinary skill in the art as appropriate.

It is noted that, in the present application, relational terms such as "first" and "second", and the like, are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.

The above description is merely exemplary of the present application and is presented to enable those skilled in the art to understand and practice the present application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the application. Thus, the present application is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A transmission system of semiconductor test equipment is characterized by comprising a communication board, a PCIe optical fiber board card on the upstream of the communication board, and a plurality of backplanes on the downstream of the communication board;

if two communication modules are selected, the two communication modules are communicated with each other;

if the PCIe optical fiber board card has a high-speed interface, one communication module is an optical communication module, and the communication module supports high-speed serial transmission; and/or

2. The transmission system of semiconductor test equipment as recited in claim 1,

if the backplane has high-speed interfaces, the high-speed interfaces of all the backplanes are configured to be connected with the optical communication module;

3. The transmission system of semiconductor test equipment according to claim 1, wherein an ARM core for porting an operating system is further integrated on the optical communication module.

4. The transport system for semiconductor test equipment according to claim 1, wherein the PCIe fiber board card is inserted into a PCI-E X8 slot on the PC side, and the communication board is provided on an ATE equipment host.

5. The transmission system of semiconductor test equipment according to claim 4, wherein:

in the starting process, the PC terminal iteratively reads configuration spaces of all PCIe optical fiber board cards in an operating processor system according to PCIe bus numbers, equipment names and function numbers through a PCIe driver, wherein the configuration spaces are positioned in an XDMA core of the PCIe optical fiber board cards; comparing the Vendor ID field and the Device ID field in the configuration space with the Vendor ID and the Device ID of the PCIe optical fiber board card to be searched, and if the two fields are equal, successfully searching; initializing the base address register space of the PCIe optical fiber board card after the PCIe optical fiber board card is searched successfully; and after the initialization is completed, data transmission is carried out.

6. The transmission system of semiconductor test equipment according to claim 1, wherein the communication module has an FPGA chip as a core; and/or the backboard also takes the FPGA chip as a core.

7. The transmission system of semiconductor test equipment according to claim 1, wherein a plurality of functional boards are inserted on the backplane, and the functional boards are communicatively connected to the backplane through a standard LVDS interface.

8. The transmission system of semiconductor test equipment as recited in claim 1,

a system power supply and a clock generator are further integrated on the communication board; and/or

9. A method for transferring a transfer system of a semiconductor test apparatus according to any one of claims 1 to 8, comprising the steps of: