CN113363266B - Array substrate and pixel driving circuit - Google Patents

Abstract

The invention discloses an array substrate and a pixel driving circuit. The array substrate includes a plurality of pixel circuits distributed in an array and a first signal line electrically connected to each pixel circuit. The pixel circuit includes a drive transistor, the drive transistor includes an active layer, a source-drain layer and a gate layer, the source-drain layer includes a source and a drain that are insulated from each other, and the first signal line is arranged on the gate layer away from the active layer. On the side, a first capacitance is formed between the source and the first signal line, and by increasing the overlapping area between the source and the first signal line, the capacitance of the first capacitance is increased, and the gate of the driving transistor and the driving transistor are reduced. The potential difference between the sources of the driving transistor avoids a large potential difference between the gate of the driving transistor and the source of the driving transistor for a long time, thereby avoiding the residual image caused by the existence of the previous screen when switching screens, and improving the display The display effect of the panel.

Description

Array substrate and pixel driving circuit

technical field

The invention belongs to the technical field of electronic products, and in particular relates to an array substrate and a pixel driving circuit.

Background technique

With the development and innovation of the optoelectronic display field, digital display devices have been widely used. Among them, the display panel is an indispensable human communication interface in the display device, especially the organic light emitting diode (Organic Light Emitting Diode, OLED) display panel. Due to the advantages of light emission, energy saving, consumption reduction, bendability, and good flexibility, it is widely used in terminal products such as smartphones and computer monitors. However, the current display panel often has a certain delay when displaying black and white dynamic images, that is, the brightness of the screen needs to be adjusted before it gradually stabilizes, and its macroscopic manifestations are switching from black screen to white screen and smearing when scrolling black and white screens. Phenomenon.

Therefore, there is an urgent need for a new array substrate and pixel driving circuit.

Contents of the invention

Embodiments of the present invention provide an array substrate and a pixel driving circuit. The array substrate reduces jump voltages when black and white images are switched, improves smear of a display panel, and improves display effect.

On the one hand, an embodiment of the present invention provides an array substrate, including a plurality of pixel circuits distributed in an array and a first signal line electrically connected to each of the pixel circuits; the pixel circuit includes a driving transistor, and the driving transistor includes an active layer and a source-drain layer and a gate layer that are insulated on the active layer, the source-drain layer includes a source and a drain that are insulated from each other, and the first signal line is arranged on the gate The pole layer is away from the side of the active layer, and the projected area of the source on the first signal line is larger than the projected area of the drain on the first signal line.

According to an aspect of the present invention, in the extending direction along the first signal line, the orthographic projection of the source on the active layer and the orthographic projection of the gate layer on the active layer The maximum distance between them is greater than the maximum distance between the orthographic projection of the drain electrode on the active layer and the orthographic projection of the gate layer on the active layer.

According to an aspect of the present invention, in the extending direction along the first signal line, the orthographic projection of the source on the active layer and the orthographic projection of the gate layer on the active layer The maximum distance between them is 20 μm to 60 μm.

According to an aspect of the present invention, the first signal line includes a high-level power signal line or a low-level power signal line.

According to one aspect of the present invention, it further includes a first insulating layer and a second insulating layer, and in a direction perpendicular to the extending direction of the first signal line and perpendicular to the active layer, the first insulating layer is set Between the active layer and the gate layer, the second insulating layer is disposed between the gate layer and the first signal line.

According to one aspect of the present invention, the overlapping portion of the orthographic projection of the source on the active layer and the orthographic projection of the first signal line on the active layer is at least one of a rectangle and a T shape. kind.

According to one aspect of the present invention, in a direction perpendicular to the extension direction of the first signal line and parallel to the active layer, the length of the orthographic projection of the source on the first signal line is greater than the The length of the orthographic projection of the drain on the first signal line; and/or, the width of the orthographic projection of the source on the first signal line is greater than the orthographic projection of the drain on the first signal line width.

According to an aspect of the present invention, the active layer includes a channel portion, the channel portion is provided in the space between the source and the drain, and the channel portion is in the first The orthographic projection on the signal line and the orthographic projection of the gate layer on the first signal line are at least partially coincident.

According to an aspect of the present invention, the extending track of the orthographic projection of the channel portion on the first signal line is one of a straight line and a broken line.

The embodiment of the present invention also provides a pixel driving circuit, including: a light emitting element; a driving module, configured to provide a driving current to the light emitting element; a storage module, connected to the driving module, configured to maintain the The potential of the control terminal; the data writing module is connected with the driving module and the storage module, and is used to write the data signal into the control terminal of the driving module; the light-emitting control module is connected with the light-emitting element and the driving module And the power supply voltage input terminal is used to control the light emitting element to emit light; the initialization module is connected to the driving module and the light emitting element, and is used to initialize the control terminal of the driving module and the light emitting element; The difference reduction module is connected with the driving module and the lighting control module, and is used to reduce the difference between the input terminal of the driving module and the control terminal of the driving module under the action of the power supply voltage signal at the input terminal of the power supply voltage. Potential difference. Compared with the prior art, the array substrate provided by the embodiment of the present invention includes a plurality of pixel circuits distributed in an array and a first signal line electrically connected to each pixel circuit. The pixel circuit includes a drive transistor, the drive transistor includes an active layer, a source-drain layer and a gate layer, the source-drain layer includes a source and a drain that are insulated from each other, and the first signal line is arranged on the gate layer away from the active layer. On the side, a first capacitor is formed between the source and the first signal line, and by increasing the overlapping area between the source and the first signal line, the capacitance of the first capacitor is increased, and the gate of the drive transistor and the drive transistor are reduced. The potential difference between the sources of the driving transistor avoids a large potential difference between the gate of the driving transistor and the source of the driving transistor for a long time, thereby avoiding the residual image caused by the existence of the previous screen when switching screens, and improving the display The display effect of the panel.

Description of drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following will briefly introduce the accompanying drawings required in the embodiments of the present invention. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For Those of ordinary skill in the art can also obtain other drawings based on these drawings without making creative efforts.

FIG. 1 is a schematic structural diagram of an array substrate provided by an embodiment of the present invention;

Fig. 2 is a sectional view along the A-A direction in Fig. 1;

3 is a schematic structural diagram of another array substrate provided by an embodiment of the present invention;

FIG. 4 is a schematic structural diagram of another array substrate provided by an embodiment of the present invention;

FIG. 5 is a schematic structural diagram of another array substrate provided by an embodiment of the present invention;

FIG. 6 is a schematic structural diagram of a pixel driving circuit provided by an embodiment of the present invention;

FIG. 7 is a circuit diagram of a pixel driving circuit provided by an embodiment of the present invention;

FIG. 8 is a timing diagram of a pixel driving circuit provided by an embodiment of the present invention.

Detailed ways

Features and exemplary embodiments of various aspects of the invention will be described in detail below. In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. It will be apparent, however, to one skilled in the art that the present invention may be practiced without some of these specific details. The following description of the embodiments is only to provide a better understanding of the present invention by showing examples of the present invention.

It should be noted that in this article, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply that there is a relationship between these entities or operations. There is no such actual relationship or order between them. Furthermore, the term "comprises", "comprises" or any other variation thereof is intended to cover a non-exclusive inclusion such that a process, method, article, or apparatus comprising a set of elements includes not only those elements, but also includes elements not expressly listed. other elements of or also include elements inherent in such a process, method, article, or device. Without further limitations, an element defined by the statement "comprising..." does not exclude the presence of additional identical elements in the process, method, article or device that includes the element.

In order to better understand the present invention, the array substrate and the pixel driving circuit according to the embodiment of the present invention will be described in detail below with reference to FIGS. 1 to 8 .

Please refer to FIG. 1 and FIG. 2, an embodiment of the present invention provides an array substrate, the array substrate includes a plurality of pixel circuits distributed in an array and a first signal line 1 electrically connected to each pixel circuit; the pixel circuit includes a driving transistor , the drive transistor includes an active layer 2 and a source-drain layer 3 and a gate layer 4 that are insulated on the active layer 2, the source-drain layer 3 includes a source 31 and a drain 32 that are insulated from each other, and the first signal line 1 is disposed on the side of the gate layer 4 facing away from the active layer 2, and the projected area of the source 31 on the first signal line 1 is larger than the projected area of the drain 32 on the first signal line 1.

It should be noted that the first signal line 1 is arranged on the side of the gate layer 4 away from the active layer 2, so that a first capacitance C1 is formed between the source electrode 31 and the first signal line 1. When the display panel switches between black and white images, , the discharge of the first capacitor C1 provides a voltage for the source 31 of the driving transistor, reduces the potential difference between the gate of the driving transistor and the source 31 of the driving transistor, and avoids the potential difference between the gate of the driving transistor and the source 31 of the driving transistor. Keep a large potential difference for a long time, so as to avoid image sticking caused by the existence of the previous screen when switching screens, and improve the display effect of the display panel. For this reason, in the embodiment of the present invention, the first signal line 1 is arranged on the gate layer 4 On the side away from the active layer 2, the projected area of the source 31 on the first signal line 1 is larger than the projected area of the drain 32 on the first signal line 1. By increasing the projected area between the source 31 and the first signal line 2 and increasing the capacitance of the first capacitor C1, the potential difference between the gate of the driving transistor and the source 31 of the driving transistor is further reduced, thereby Improved the smear of the display panel and improved the display effect.

According to the capacitance calculation formula, the capacitance of the first capacitor C1 is proportional to the dielectric constant of the medium between the plates and the area of the plates, and inversely proportional to the distance between the plates. Therefore, on the premise that the dielectric constant of the medium between the plates and the distance between the plates are a certain value, by increasing the relative overlapping area between the source electrode 31 and the first signal line 1, the capacitance of the first capacitor C1 can be increased. . That is, increasing the capacitance of the first capacitor C1 can further increase the potential on the source 31 of the driving transistor and reduce the potential difference between the gate of the driving transistor and the source 31 of the driving transistor when the first capacitor C1 is discharged.

In order to increase the overlapping area of the source electrode 31 and the first signal line 2, please refer to FIG. The maximum distance between the projection and the orthographic projection of the gate layer 4 on the active layer 2 is greater than the distance between the orthographic projection of the drain electrode 32 on the active layer 2 and the orthographic projection of the gate layer 4 on the active layer 2 maximum distance. Therefore, when the relative distance between the source 31 and the drain 32 in a single drive transistor is constant, by adjusting the position of the gate 41 relative to the source 31 and the drain 32, the gate 41 is set in a direction away from the source 31 By forming an asymmetric driving transistor structure, the effect of increasing the relative area between the source electrode 31 and the first signal line 2 can be achieved, thereby increasing the capacitance of the first capacitor C1.

Optionally, the maximum distance between the orthographic projection of the source electrode 31 on the active layer 2 and the orthographic projection of the gate layer 4 on the active layer 2 is 20 μm˜60 μm. Its specific size can be adjusted according to the actual structure of the driving transistor, and is not specifically limited here.

In order to further illustrate the specific structure of the array substrate, please refer to FIG. 2. The driving transistor of the array substrate includes an active layer 2, a source and drain layer 3, and a gate layer 4. The active layer 2 is the semiconductor layer where the driving transistor is located, and the source and drain The electrode layer 3 includes a source 31 and a drain 32 insulated from each other. The source-drain layer 3 is a metal conductive layer where the source 31 and the drain 32 of the driving transistor are located, and the gate layer 4 is where the gate 41 of the driving transistor is located. metal conductive layer. The drive transistor also includes an interlayer insulating layer 5, the interlayer insulating layer 5 includes a first insulating layer 51 and a second insulating layer 52, the first insulating layer 51 is arranged between the active layer 2 and the gate layer 4, and is perpendicular to In the extending direction of the first signal line 1 and perpendicular to the direction of the active layer 2 , the second insulating layer 52 is disposed between the gate layer 4 and the first signal line 1 . The gate 41 of the driving transistor is generally used to receive a control signal, so that the driving transistor 31 is turned on or off under the control of the control signal. The source 31 of the drive transistor is connected to the first signal line, and the drain 32 is connected to the light-emitting element. When the gate 41 receives the control signal for conducting, the gate 41 controls the active layer 2 to conduct, and the source 31 and the drain 32 to form a passage, so as to realize the light emitting element.

1 and 2, the orthographic projection of the source electrode 31 on the active layer 2 and the orthographic projection of the first signal line 1 on the active layer 2 partially overlap, that is, the source electrode 31 and the first signal line 1 are formed are the upper and lower plates, and the interlayer insulating layer 5 is the first capacitor C1 as the medium between the plates. When the display panel switches between black and white images, the first capacitor C1 can supply power to the source 31 and reduce the potential difference between the gate 41 and the source 31 . When the projected area of the source 31 on the first signal line 1 is increased, the capacitance of the first capacitor C1 will also increase, further reducing the potential difference between the gate 41 and the source 31, and avoiding the display panel The bad smear phenomenon.

Optionally, the active layer 2 may be a single crystal silicon active layer or a polysilicon active layer, and the polysilicon active layer may be a low temperature polysilicon (Low Temperature Poly-Silicon, LTPS). Materials of the source 31 , the drain 32 and the gate 41 may include one or a combination of molybdenum, titanium, aluminum, copper, and the like.

Wherein, the first signal line includes a power signal line or a ground signal line. Specifically, when the driving transistor is a PMOS transistor, the source 31 is connected to the high-level power signal line, ie, the VDD signal line, the drain 32 is connected to the light-emitting element, and the first capacitor C1 is formed between the source 31 and the VDD signal line. When the driving transistor is an NMOS transistor, the source 31 is connected to the low-level power signal line, that is, the VSS signal line, and the first capacitor C1 is formed between the low-level power signal line and the source 31 .

In some optional embodiments, the overlapping portion of the orthographic projection of the source electrode 31 on the active layer 2 and the orthographic projection of the first signal line 1 on the active layer 2 is at least one of a rectangle and a T shape. Please refer to Fig. 1 and Fig. 4, the overlapping part of the orthographic projection of the source 31 on the active layer 2 in Fig. 1 and the orthographic projection of the first signal line 1 on the active layer 2 is T-shaped, and the source in Fig. The overlapping portion of the orthographic projection of 31 on the active layer 2 and the orthographic projection of the first signal line 1 on the active layer 2 is rectangular.

It can be understood that the capacitance of the first capacitor C1 can be increased by changing the projected area of the source electrode 31 on the first signal line 1 . It is necessary to adjust the shape of the overlapped part by comprehensively considering the preparation process and specific structure of the array substrate, as long as the capacitance of the first capacitor C1 can be increased. Specifically, the line width of the first signal line 1 is 1.5 μm to 25 μm, the length of the first signal line 1 is 1.5 μm to 25 μm, and the projected area of the source 31 on the first signal line 1 is 2.5 μm ² to 500 μm ² Compared with the prior art, the projected area of the source electrode 31 on the first signal line 1 can be increased to be greater than 5 μm ² , effectively increasing the capacitance of the first capacitor C1.

In some optional embodiments, in a direction perpendicular to the extending direction of the first signal line 1 and parallel to the active layer 2, the length of the orthographic projection of the source 31 on the first signal line 1 is longer than that of the drain 32 The length of the orthographic projection on the first signal line 1 ; and/or, the width of the orthographic projection of the source 31 on the first signal line 1 is greater than the width of the orthographic projection of the drain 32 on the first signal line 1 . Specifically, the projected area of the source electrode 31 on the first signal line 1 can be increased by adjusting at least one of the length and width of the orthographic projection of the source electrode 31 on the first signal line 1 .

In addition, in order to further facilitate the conduction of the source electrode 31 and the drain electrode 32 and improve the response speed of the light-emitting element, please refer to FIG. 1, FIG. 2, FIG. 5 and FIG. 6, the active layer 2 includes a channel part 6, the channel part 6 is arranged in the interval between the source electrode 31 and the drain electrode 32, and the orthographic projection of the channel part 6 on the first signal line 1 and the projection of the gate layer 4 on the first signal line 1 The orthographic projections are at least partially coincident. By disposing the channel part 6 in the active layer 2 opposite to the gate layer 4, the conduction between the gate layer 4 and the active layer 2 can be facilitated, and the response speed of the light-emitting element can be improved.

Optionally, the extending track of the orthographic projection of the channel portion 6 on the first signal line 1 is one of a straight line and a broken line. Similarly, the specific extension track of the channel portion 6 can also be adjusted according to the preparation process and specific structure of the array substrate, and its specific shape and size are not specifically limited here.

Please refer to FIG. 6 to FIG. 7, the embodiment of the present invention also provides a pixel driving circuit, the pixel driving circuit includes a light emitting element D1, a driving module P11, a storage module P12, a data writing module P13, a light emitting control module P14, an initialization module P15 and potential difference reduction module P16. Wherein, the light emitting element D1 can be selected according to the type of the display panel, for example, the light emitting element D1 can specifically be a light emitting diode (Light Emitting Diode, LED) or an organic light emitting diode (Organic Light Emitting Diode, OLED), which is not limited herein. Specifically, the cathode of the light emitting element D1 is connected to the second power supply voltage input terminal VSS.

The driving module P11 can be used to provide driving current to the light emitting element D1. Specifically, whether the driving current can flow to the light-emitting element D1 through the driving module P11 can be controlled by controlling the driving module P11 to be turned on and off.

The storage module P12 is connected with the drive module P11 and has the function of storing electric energy. The storage module P12 can be used to maintain the potential of the control terminal of the driving module P11. Specifically, the storage module P12 can be charged during the charging phase of the pixel driving circuit driving the pixel unit. In the read-write and light-emitting phase of the driving process, the storage module P12 can use the voltage charged in the charging phase to maintain the potential of the control terminal of the driving module P11.

The data writing module P13 is connected with the driving module P11 and the storage module P12, and is used for writing data signals into the control terminal of the driving module P11. Specifically, the data writing module P13 is connected to the data signal terminal VDATA and the first scan signal terminal S1. The data signal terminal VDATA is used to provide data signals. The first scan signal terminal S1 is used for providing a first scan signal. In the charging phase of the driving process, the data writing module P13 uses the data signal to charge the storage module P12 through the driving module P11 under the control of the first scan signal. In the read-write and light-emitting stage of the driving process, the storage module P12 uses the voltage charged in the charging stage to maintain the potential of the control terminal of the drive module P11, which is equivalent to writing data signals into the control terminal of the drive module P11.

The light emitting control module P14 is connected with the light emitting element D1, the driving module P11 and the input terminal of the power supply voltage, and is used for controlling the light emitting element D1 to emit light. Specifically, the light emission control module P14 is connected to the light emission control signal terminal EM and the first power supply voltage input terminal VDD. The light emission control signal terminal EM is used for providing light emission control signals. The first power supply voltage input terminal VDD is used to provide a high level signal. In the read-write and light-emitting stage of the driving process, the light-emitting control module P14 is turned on under the control of the light-emitting control signal, and can transmit the driving current generated by the high-level signal to the light-emitting element D1 to make the light-emitting element D1 emit light.

The initialization module P15 is connected with the driving module P11 and the light emitting element D1, and is used for initializing the control terminal of the driving module P11 and the anode of the light emitting element D1 respectively. Specifically, the initialization module P15 is connected to the reference voltage signal terminal VREF and the second scan signal terminal S2. The reference voltage signal terminal VREF is used to provide a reference voltage signal, and the reference voltage signal is used as an initialization signal. In some examples, the voltage of the reference voltage signal is negative. The second scan signal terminal S2 is used for providing a second scan signal. In the initialization stage of the driving process, the initialization module P15 is turned on under the control of the second scanning signal. On the one hand, the reference voltage signal is used to initialize the control terminal of the driving module P11, and on the other hand, the voltage of the reference voltage signal is charged into the storage module P12 and the anode of the light emitting element D1 to initialize the anode of the light emitting element D1.

The potential difference reduction module P16 is connected to the drive module P11 and the power supply voltage input terminal, and is used to reduce the control between the input terminal of the drive module P11 and the drive module P11 under the action of the high-level signal output by the first power supply voltage input terminal VDD. terminal potential difference.

Specifically, please refer to FIG. 6 and FIG. 7, the driving module P11 includes a first transistor T1, the first transistor T1 is the driving transistor in the pixel driving circuit; the storage module P12 includes a second capacitor C2; the data writing module P13 includes a second The second transistor T2 and the third transistor T3; the light emission control module P14 includes the fourth transistor T4 and the fifth transistor T5; the initialization module P15 includes the sixth transistor T6 and the seventh transistor T7.

The control terminal of the first transistor T1 is connected with the first terminal of the second capacitor C2, the second terminal of the second transistor T2, and the second terminal of the sixth transistor T6. The first end of the first transistor T1 is connected to the second end of the third transistor T3, the second end of the fourth transistor T4, and the first end of the first capacitor C1. The second terminal of the first transistor T1 is connected with the first terminal of the second transistor T2 and the first terminal of the fifth transistor T5. The first terminal of the first transistor T1 is the input terminal of the driving module P11, and the second terminal of the first transistor T1 is the output terminal of the driving module P11.

The control end of the second transistor T2 is connected to the first scan signal end S1. The first terminal of the second transistor T2 is connected with the first terminal of the fifth transistor T5. The second terminal of the second transistor T2 is connected with the first terminal of the second capacitor C2 and the second terminal of the sixth transistor T6.

The control terminal of the third transistor T3 is connected to the first scan signal terminal S1. The first terminal of the third transistor T3 is connected to the data signal terminal VDATA. The second terminal of the third transistor T3 is connected with the first terminal of the first capacitor C1 and the second terminal of the fourth transistor T4.

The control terminal of the fourth transistor T4 is connected to the light emission control signal terminal EM. The first terminal of the fourth transistor T4 is connected with the first power supply voltage input terminal VDD and the second terminal of the second capacitor C2. The second end of the fourth transistor T4 is connected to the first end of the first capacitor C1.

The control terminal of the fifth transistor T5 is connected to the light emission control signal terminal EM. The second end of the fifth transistor T5 is connected to the anode of the light emitting element D1.

The control terminal of the sixth transistor T6 is connected to the second scan signal terminal S2. The first terminal of the sixth transistor T6 is connected with the reference voltage input terminal VREF and the first terminal of the seventh transistor T7. The second end of the sixth transistor T6 is connected to the first end of the second capacitor C2.

The control end of the seventh transistor T7 is connected to the second scan signal end S2. The first terminal of the seventh transistor T7 is connected to the reference voltage signal terminal VREF. The second end of the seventh transistor T7 is connected to the anode of the light emitting element D1. The second terminal of the seventh transistor T7 is the first output terminal of the initialization module P15. The second end of the first capacitor C1 is connected to the second end of the seventh transistor.

The second terminal of the second capacitor C2 is connected to the first power supply voltage input terminal VDD.

The cathode of the light emitting element D1 is connected to the second power supply voltage input terminal VSS. The second power supply voltage input terminal VSS is used to provide a low-level signal. In some examples, the second power supply voltage input terminal may be a ground terminal, which is not limited herein.

Taking FIG. 3 as an example, the driving sequence of the pixel circuit between two frames includes three phases, an initialization phase, a data writing phase and a light emitting phase.

In the initialization phase T1, the second scan signal S2 is at a high level, and the emission control signal EM and the first scan signal S1 are at a low level. The light emission control signal EM controls the fourth transistor T4 and the fifth transistor T5 to turn off; the second scan signal S2 controls the second transistor T2 and the third transistor T3 to turn off; the first scan signal S1 controls the sixth transistor T6 to turn on, and the initial voltage VREF initializes the gate of the first transistor T1; the first scan signal S1 controls the seventh transistor T7 to turn on, and the initial voltage VREF initializes the anode of the light emitting device D1. At the same time, the first capacitor C1 is used as a potential difference reduction module to reduce the potential difference between the input terminal of the driving module P11 and the control terminal of the driving module P11 under the action of the power supply voltage signal. Specifically, compared with the control terminal of the driving module P11 in the prior art, the input terminal of the driving module P11 is at a high level. In this embodiment, under the action of the first capacitor C1, the first transistor T1 The potential of the input terminal, that is, the source, is greater than the potential of the control terminal, that is, the gate of the first transistor T1, so that the first transistor T1 is in a conduction state. For example, in the initialization phase T1 between two frames from a black picture to a white picture in the prior art, the source voltage of the first transistor T1 is -4V, the gate voltage is -3V, and the first transistor T1 is in an off state , while in the initialization phase T1 between two frames from the white picture to the white picture in the prior art, the voltage of the source of the first transistor T1 is 0V, the voltage of the gate is -3V, and the first transistor T1 is in the conduction state , the state of the first transistor T1 is different between two frames from a black picture to a white picture and between two frames from a white picture to a white picture, the time required to complete the display is prone to problems such as smearing.

In the embodiment of the present invention, in the initialization phase T1 between two frames from the black picture to the white picture, the voltage of the source of the first transistor T1 is 3V, the voltage of the gate is -3V, and the first transistor T1 is in the conduction state. and between two frames from the white picture to the white picture, the voltage of the source of the first transistor T1 is 3V, the voltage of the gate is -3V, the first transistor T1 is in the conduction state, and the black picture to the white picture The state of the first transistor T1 is the same between the two frames of the white picture and the white picture to the white picture, which has display consistency and avoids the problem of smear.

In the data writing phase T2, the data signal VDATA corresponding to the light emitting brightness of the light emitting device D1 is provided. The emission control signal EM and the first scan signal S1 are at high level, and the second scan signal S2 is at low level. The light emission control signal EM controls the fourth transistor T4 and the fifth transistor T5 to turn off; the first scan signal S1 controls the sixth transistor T6 and the seventh transistor T7 to turn off; the second scan signal S2 controls the second transistor T2 and the third transistor T3 is turned on to write the data signal VDATA into the gate of the first transistor T1 through the source and drain of the first transistor T1 . The gate voltage of the first transistor T1 increases gradually, and when it reaches VDATA+Vth, the data writing phase is completed.

In the light-emitting phase T3, the first scan signal S1 and the second scan signal S2 are at high level, and the light-emitting control signal EM is at low level. The first scan signal S1 controls the sixth transistor T6 and the seventh transistor T7 to turn off; the second scan signal S2 controls the second transistor T2 and the third transistor T3 to turn off; the light emission control signal EM controls the fourth transistor T4 and the fifth transistor T5 When it is turned on, the gate voltage of the first transistor T1 is VDATA+Vth, and the source voltage is applied to the first power supply VDD, thereby generating a driving current and flowing into the anode of the light emitting device D1 to drive the light emitting device D1 to emit light.

The above are only specific implementations of the present invention, and those skilled in the art can clearly understand that for the convenience and brevity of description, the specific working process of the above-described systems, modules and units can be referred to in the foregoing method embodiments The corresponding process will not be repeated here. It should be understood that the protection scope of the present invention is not limited thereto. Any person skilled in the art can easily think of various equivalent modifications or replacements within the technical scope disclosed in the present invention, and these modifications or replacements should cover all Within the protection scope of the present invention.

It should also be noted that the exemplary embodiments mentioned in the present invention describe some methods or systems based on a series of steps or devices. However, the present invention is not limited to the order of the above steps, that is, the steps may be performed in the order mentioned in the embodiment, or may be different from the order in the embodiment, or several steps may be performed simultaneously.

Claims (9)

1. An array substrate is characterized by comprising a plurality of pixel circuits distributed in an array and a first signal line electrically connected with each pixel circuit;

the pixel circuit comprises a driving transistor, the driving transistor comprises an active layer, a source drain electrode layer and a grid electrode layer, the source drain electrode layer and the grid electrode layer are arranged on the active layer in an insulating mode, the source drain electrode layer comprises a source electrode and a drain electrode which are mutually insulated, the first signal line is arranged on one side, away from the active layer, of the grid electrode layer, and the projection area of the source electrode on the first signal line is larger than the projection area of the drain electrode on the first signal line;

the maximum distance between the orthographic projection of the source electrode on the active layer and the orthographic projection of the gate electrode on the active layer is larger than the maximum distance between the orthographic projection of the drain electrode on the active layer and the orthographic projection of the gate electrode on the active layer along the extending direction of the first signal line, and a first capacitor is formed between the source electrode and the first signal line.

2. The array substrate of claim 1, wherein a maximum distance between an orthographic projection of the source electrode on the active layer and an orthographic projection of the gate electrode on the active layer in an extending direction along the first signal line is 20 μm to 60 μm.

3. The array substrate of claim 1, wherein the first signal line comprises a high level power signal line or a low level power signal line.

4. The array substrate according to claim 1, further comprising a first insulating layer and a second insulating layer, the first insulating layer being disposed between the active layer and the gate layer in a direction perpendicular to an extending direction of the first signal line and perpendicular to the active layer, the second insulating layer being disposed between the gate layer and the first signal line.

5. The array substrate according to claim 1, wherein a portion of the active layer where the source electrode is projected forward and the first signal line is projected forward is at least one of rectangular and T-shaped.

6. The array substrate according to claim 5, wherein a length of orthographic projection of the source electrode on the first signal line is longer than a length of orthographic projection of the drain electrode on the first signal line in a direction perpendicular to an extending direction of the first signal line and parallel to the active layer;

and/or the width of orthographic projection of the source electrode on the first signal line is larger than the width of orthographic projection of the drain electrode on the first signal line.

7. The array substrate according to claim 1, wherein the active layer includes a channel portion, the channel portion is disposed in a space between the source and the drain, and an orthographic projection of the channel portion on the first signal line and an orthographic projection of the gate layer on the first signal line at least partially overlap.

8. The array substrate according to claim 7, wherein an extended trace of the orthographic projection of the channel portion on the first signal line is one of a straight line and a broken line.

9. A pixel driving circuit, comprising:

a light emitting element;

a driving module for supplying a driving current to the light emitting element;

the storage module is connected with the driving module and used for maintaining the potential of the control end of the driving module;

the data writing module is connected with the driving module and the storage module and is used for writing data signals into the control end of the driving module;

the light-emitting control module is connected with the light-emitting element, the driving module and the power supply voltage input end and used for controlling the light-emitting element to emit light;

the initialization module is connected with the driving module and the light-emitting element and used for initializing the control end of the driving module and the light-emitting element;

the potential difference reducing module is connected with the driving module and the light-emitting control module and is used for reducing the potential difference between the input end of the driving module and the control end of the driving module under the action of a power voltage signal of the power voltage input end, and the potential difference reducing module is a first capacitor in the array substrate according to any one of claims 1 to 8.

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