CN113345496A

CN113345496A - Memory array

Info

Publication number: CN113345496A
Application number: CN202110559579.5A
Authority: CN
Inventors: 孙作金; 薛庆华; 王海力
Original assignee: Jingwei Qili Beijing Technology Co ltd
Current assignee: Jingwei Qili Beijing Technology Co ltd
Priority date: 2021-05-21
Filing date: 2021-05-21
Publication date: 2021-09-03

Abstract

The present application relates to the technical field of integrated circuits, and provides a memory array, each column of memory cells includes: a plurality of memory cells arranged in a column according to the arrangement direction, and the first edge region of each memory cell is provided with bit line contacts and complementary bit line contacts, the plurality of memory cells includes a memory cell pair formed by being divided into a first memory cell and a second memory cell in an adjacent relationship, and the respective second edge regions of the first memory cell and the second memory cell are connected to form a connection area, the connection area is located between the respective first edge areas of the first storage unit and the second storage unit; two bit lines are respectively connected with the respective bit line contacts of the first storage unit and the second storage unit in a one-to-one correspondence; The two complementary bit lines are respectively connected to the respective complementary bit line contacts of the first storage unit and the second storage unit in a one-to-one correspondence. With the technical solutions provided by the embodiments of the present application, the load on the bit line can be reduced, and the running speed of the FPGA including the memory array can be improved.

Description

Memory array

Technical Field

The present application relates to the field of integrated circuit technology, and more particularly, to a memory array.

Background

In the FPGA, since there are many functional modules and the number of devices is large, metal wiring resources are relatively tight. The memories are indispensable modules, and are usually distributed in the whole FPGA by being divided into a plurality of columns, so that a lot of wiring resources are occupied.

Currently, in a memory, each column of configuration bits corresponds to one column of bit lines (occupying a vertical routing resource), and as the number of bits of each column of memory cell pair is more, the load of the bit lines is heavier. Taking a column of 132-bit memory cell pairs as an example, there are two bit lines, each with 132 memory cells.

However, the more the bit line is loaded, the slower the operation speed is, and the functional failure may be caused after the 28nm process design is entered.

Disclosure of Invention

The embodiment of the application provides a memory array, wherein a bit line contact and a complementary bit line contact are arranged on two sides of a connecting area of two memory units, so that the two memory units are connected with different bit lines and complementary bit lines, the load on each bit line is reduced by half, the operating speed of a memory unit pair is increased, and the function and the performance of the memory unit pair are guaranteed; the word lines are reduced by half, so that the wiring resources in the word line routing direction are saved by half.

In a first aspect, an embodiment of the present application provides a memory array, including:

the memory cell array comprises a plurality of memory cells, a first edge region of each memory cell is provided with a bit line contact and a complementary bit line contact, the memory cells comprise memory cell pairs which are divided into a first memory cell and a second memory cell according to adjacent relation, second edge regions of the first memory cell and the second memory cell are connected to form a connecting region, and the connecting region is positioned between the first edge regions of the first memory cell and the second memory cell;

the two bit lines are respectively connected with the respective bit line contacts of the first storage unit and the second storage unit in each storage unit pair in a one-to-one correspondence mode;

the two complementary bit lines are respectively connected with the complementary bit line contacts of the first memory cell and the second memory cell in each memory cell pair in a one-to-one correspondence mode;

each memory cell is connected with a word line, and the first memory cell and the second memory cell in the memory cell pair share one word line.

In the embodiment of the application, the bit line contact and the complementary bit line contact are arranged on two sides of the connecting area of the two memory units, so that the two memory units are connected with different bit lines and complementary bit lines, the load on each bit line is reduced by half, the operating speed of the memory unit pair is increased, and the function and the performance of the memory unit pair are guaranteed. The word lines are reduced by half, so that the wiring resources in the word line routing direction are saved by half.

In one possible embodiment, the plurality of memory cells are arranged in a row in the arrangement direction in such a way that a first memory cell, a second memory cell and a first memory cell are arranged;

the first edge regions of two adjacent first memory cells in the plurality of memory cells are connected, so that the two adjacent first memory cells share the bit line contact and the complementary bit line contact;

the first edge regions of two adjacent second memory cells of the plurality of memory cells are connected such that the two adjacent second memory cells share the bit line contact and the complementary bit line contact.

In the embodiment of the application, the bit line contact and the complementary bit line contact are shared by two adjacent memory cells, so that the splicing area is reduced, and the length of the memory array in the column direction is reduced.

In one possible embodiment, the storage unit comprises:

the transistor array comprises a plurality of transistors, a plurality of storage units and a plurality of control units, wherein the transistors at least comprise two transmission transistors, two pull-down transistors and two pull-up transistors which are symmetrically arranged with a target central line, and the target central line is a central line of a column of storage units along the arrangement direction;

the connection region at least comprises two pull-up transistors and an active region of one side, far away from the transmission transistor, of active regions on two sides of polycrystalline silicon in the two pull-down transistors; the first edge area at least comprises active areas on two sides of polycrystalline silicon in the two transmission transistors, wherein the active areas are far away from one side of the connection area; the active region of one pass transistor in the first edge region provides a bit line contact and the active region of the other pass transistor provides a complementary bit line contact.

In one possible embodiment, the storage unit comprises:

the memory cell includes:

the 1 st to Nth metal layers are arranged on the transistors from bottom to top, the second metal layer is provided with two bit lines and two complementary bit lines, and N is a positive integer greater than 1;

the 1 st to Nth insulating layers are arranged between the plurality of transistors and the first metal layer and between the adjacent two metal layers;

the insulating layer of the first edge region is provided with an interlayer via hole so that the bit line is connected to the bit line contact and the complementary bit line is connected to the complementary bit line contact.

In one possible implementation, the two bit lines and the two complementary bit lines of the first memory cell and the second memory cell in the connection region are respectively connected;

two bit lines are located on one side of the target centerline and two complementary bit lines are located on the other side of the target centerline.

In one possible implementation mode, the polycrystalline silicon in the pull-up transistor above the target central line is connected to the active regions on two sides of the polycrystalline silicon in the pull-down transistor below the target central line, wherein the active regions are close to the active region on one side of the transmission transistor;

and the polycrystalline silicon in the pull-up transistor below the target central line is connected to the active regions at two sides of the polycrystalline silicon in the pull-down transistor above the target central line, which are close to the active region at one side of the transmission transistor, through the self-locking line in the second metal layer.

In the embodiment of the application, a self-locking structure is formed by interconnection of two pull-up transistors and two pull-down transistors, so that data is cached.

In one possible implementation, the polysilicon in the pass transistor of each memory cell away from the target centerline is provided with a word line contact;

the word line contacts of the first memory cell and the second memory cell in the memory cell pair are respectively connected with the same word line.

In one possible embodiment, each of the plurality of memory cells is provided with a ground contact and a power supply line contact;

the column memory cell includes:

a ground line connected to the ground contact provided for each memory cell;

a power supply line connected to a power supply line contact provided for each memory cell;

the first memory cell and the second memory cell in the memory cell pair share a ground contact arranged in an active region of a pull-down transistor and a power supply contact arranged in an active region of a pull-up transistor in a connection region; the insulating layer of the connection region is provided with interlayer vias to connect the power supply line to the power supply line contact and the ground line to the ground line contact.

In one possible implementation mode, the power supply line is arranged on the second to ith metal layers, the ground line is arranged on the second metal layer, the word line is arranged on the second to jth metal layers, and i and j are positive integers greater than 2;

the power supply lines in the second to ith metal layers are connected to the power supply line contact through interlayer through holes arranged on the 1 st to ith-1 st insulating layers of the connecting region; word lines in the second to jth metal layers are connected to the word line contacts through interlayer through holes arranged in the 1 st to jth insulating layers; the word lines, the power supply lines, and the ground lines of the first memory cells and the second memory cells in the connection region are connected, respectively.

In one possible embodiment, i is 4 and/or j is 5;

the ground line is arranged on one side of the two bit lines and/or the two complementary bit lines far away from the target central line;

the power line of the second metal layer is vertical to the bit line, and the power line of the fourth metal layer is parallel to the bit line;

the word lines in the second metal layer are parallel to the bit lines, and the word lines in the fifth metal layer are perpendicular to the bit lines and located in the connection area.

In the embodiment of the application, word lines are arranged through the second to fifth metal layers, and power lines are arranged through the second to fourth metal layers, so that the word lines and the power lines are shared.

In a second aspect, embodiments of the present application provide an FPGA including a memory array as in any one of the first aspects.

According to the FPGA provided by the embodiment of the application, the bit line contact and the complementary bit line contact are arranged on two sides of the connecting area of the two storage units, so that the two storage units are connected with different bit lines and complementary bit lines, the load on each bit line is reduced by half, the running speed of the storage unit pair is increased, and the function and the performance of the storage unit pair are guaranteed; the word lines are reduced by half, so that the wiring resources in the word line routing direction are saved by half.

Drawings

In order to more clearly illustrate the embodiments or prior art solutions of the present application, the drawings needed for describing the embodiments or prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments described in the present application, and that other drawings can be obtained by those skilled in the art without inventive exercise.

Fig. 1 is a layout design of a memory array provided in an embodiment of the present application (omitting second to fifth metal layers);

FIG. 1a is a layout design of the transistor of FIG. 1;

FIG. 1b is a layout design of the first metal layer in FIG. 1;

FIG. 2 is a layout design of the second metal layer omitted from FIG. 1;

FIG. 3 is a layout design of the third metal layer omitted from FIG. 1;

FIG. 4 is a layout design of a fourth metal layer omitted from FIG. 1;

FIG. 5 is a layout design of the fifth metal layer omitted from FIG. 1;

FIG. 6 is a schematic diagram of a 64 × 2bit single decoding memory according to the present application;

wherein, in the figures, the respective reference numerals:

100-a memory cell; 101-a semiconductor substrate; 102-an active region; 103-polycrystalline silicon; 104-edge area; 104 a-a bit line contact; 104 b-complementary bit line contact; 105-a connecting region; 105 a-ground contact; 105 b-power line contacts; 110-memory cell pair; 111-a first storage unit; 112-a second storage unit; a PG-pass transistor; PGa-storage nodes; PGb-word line contact; a PD-pull-down transistor; PU-pull-up transistor; PUa-active area contacts; PUb-self-locking contacts; l1-center line of the column memory cells along the alignment direction; l2-reference direction; m1 — first metal layer; m2 — second metal layer; m2 a-self-locking wire; m3 — third metal layer; m4 — fourth metal layer; m5-fifth metal layer.

Detailed Description

In order to make the objects, technical solutions and advantages of the present application more apparent, the technical solutions of the present application will be described in detail and completely with reference to the following embodiments and accompanying drawings. It should be apparent that the described embodiments are only some of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicit indication of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. The terms "comprising," "including," "having," and variations thereof mean "including, but not limited to," unless expressly specified otherwise.

In a first aspect, an embodiment of the present invention provides a memory array, where each row memory cell in the memory array is connected to a word line, and each column memory cell in the memory array is connected to two bit lines, two complementary bit lines, a ground line, and a power line. In practical applications, the memory array may include a plurality of columns of memory cells, which is not specifically limited in the embodiments of the present application, and needs to be determined in combination with actual requirements. Fig. 1 provides a layout design of a memory array according to an embodiment of the present application. Referring to fig. 1, any column of memory cells in the memory array includes a plurality of memory cells 100, and the plurality of memory cells 100 are arranged in a column in the direction indicated by L1. The plurality of memory cells 100 includes a pair of memory cells 110 divided into a first memory cell 111 and a second memory cell 112 in an adjacent relationship. The first memory cell 111 is connected to one bit line and one complementary bit line, and the second memory cell 112 is connected to another bit line and another complementary bit line, in other words, one bit line and one complementary bit line are connected to the first memory cell 111 in each memory cell pair 100, and another bit line and another complementary bit line are connected to the second memory cell 112 in each memory cell pair 100, so that the load on each bit line is reduced by half, thereby increasing the operating speed of the memory cell pair and ensuring the function and performance thereof. Each memory cell 100 is connected to a word line, and the first memory cell 111 and the second memory cell 112 share one word line, in other words, two rows of memory cells where the first memory cell 111 and the second memory cell 112 are located share one word line, so that the wiring resources in the word line routing direction are saved by half. The first memory cell 111 and the second memory cell 112 in the memory cell pair 100 share one power supply line, and two ground lines are respectively connected, in other words, one power supply line is connected to each memory cell 100, and two ground lines are respectively connected to each memory cell 100.

The operation of the memory array will now be explained:

when writing operation is performed on the memory array, one word line is selected through the row address decoder, at least two memory cells 100 connected with the word line are selected through the column address decoder, at least two read-write circuits connected with the at least two memory cells 100 are controlled to be in a write state, and data of an input end and a data of an output end are written into the at least two memory cells 100 through the at least two read-write circuits.

When the memory array is read, a word line is selected by the row address decoder, at least two memory units 100 connected with the word line are selected by the column address decoder, at least two read-write circuits connected with the at least two memory units 100 are controlled to be in a read state, and data in the at least two memory units 100 connected with the at least two read-write circuits are read to the input end and the output end by the at least two read-write circuits.

It should be understood that when one of the word lines is selected by the address decoder, the word line is at a high level, all the memory cell pairs connected to the word line are turned on, and then the bit line and the complementary bit line are read and written by the read and write circuit pair to which the turned-on memory cell pair is connected.

Fig. 6 is a schematic structural diagram of a 64 × 2bit single decoding memory according to the present application, including: 6-64 line address decoders, memory arrays, and read and write controls.

When reading the memory, the address codes of six bits a0 to a5 are supplied to an address decoder, a word line is selected, and then transistors of the first memory cell 111 and the second memory cell 112 connected to the word line are turned on. The read/write circuit is then controlled to a read state, and data in the first memory cell 111 and the second memory cell 112 connected to the selected word line is sent out to I/O1 to I/O2.

When writing to the memory, the address code of six bits a 0-a 5 is sent to the address decoder, one word line resource is selected, and then the transistors of the first memory cell 111 and the second memory cell 112 connected to the word line are turned on. The read/write circuits are then controlled to a write state, and data at the I/O1-I/O2 terminals are written into the first memory cell 111 and the second memory cell 112 connected to the selected word line.

It should be noted that, in the embodiment of the present invention, a read/write mode of an FPGA configuration memory with a single decoding structure is described, which should not be construed as a limitation to the present invention. The present application is equally applicable to address decoding memories for dual decoding architectures.

In the embodiment of the application, because two rows of storage units share one word line, a large amount of transverse wiring resources are saved; meanwhile, the first storage unit 111 and the second storage unit 112 in the storage unit pair are connected with different bit lines, so that the load of the bit lines is reduced, and the storage speed of the memory array is higher and the reliability is higher.

Each memory cell pair 110 has the same structure, and the overall structure of the memory cell pair 110 will be described below by way of specific embodiments. For convenience of description, two bit lines are provided as BL0 and BL1, two complementary bit lines are provided as BLB0 and BLB1, two ground lines are VSSD0 and VSSD1, power supply lines are VC, and word lines are WL, and the following description will be given by taking BL0, BL1, BLB0, BLB1, VSSD0, VSSD1, VC, and WL as examples. The BL0 and the BLB0 are simultaneously provided to be connected to the first memory cell 111, and the BL1 and the BLB1 are provided to be connected to the second memory cell 112.

Fig. 1a is a layout design of a transistor of a memory cell according to an embodiment of the present application, and fig. 1a does not show the 1 st to nth metal layers and the 1 st to nth insulating layers in order to clarify the features of the present application. For convenience of description, the following will be described in more detail by taking the reference direction L2 and the center line L1 of the column memory cells in the arrangement direction as an example.

Referring to fig. 1a, the first memory cell 111 at least includes an edge region 104 and a connecting region 105; the second memory cell 112 includes at least an edge region 104 and a connection region 105. The first storage unit 111 and the second storage unit 112 are connected together by the connection region 105. It is to be understood that the first memory cell 111 and the second memory cell 112 share an active region in the connection region 105; the connection region 105 may be understood as a region located on the opposite side of the edge region 104 of the memory cell 100, in other words, the connection region 105 and the edge region 104 are located on both sides of the center line of the memory cell 100 in the direction of L2.

In one possible embodiment, in order to realize that the first memory cell 111 and the memory cell 20 are connected to different bit lines and complementary bit lines, the active regions in the edge region 104 of the respective first memory cell 111 and second memory cell 112 are provided with a bit line contact 104a and a complementary bit line contact 104 b. Wherein the bit line contact 104a in the edge region 104 of the first memory cell 111 is connected to BL0 and the complementary bit line contact 104b is connected to BLB 0; the bit line contact 104a in the second edge region 104 of the second memory cell 112 is connected to BL1 and the complementary bit line contact 104b is connected to BLB1, so that the load of one bit line connection is reduced by half, thereby increasing the operating speed of the memory cell pair and ensuring the function and performance thereof.

In order to reduce the area of the tiling while ensuring that the first memory cell 111 and the second memory cell 112 can connect different bit lines, referring to fig. 1, in one possible implementation, the plurality of memory cells 100 are arranged in a column in the direction indicated by L1 according to the arrangement of the first memory cell 111, the second memory cell 112, and the first memory cell 111, two adjacent first memory cells 111 share the bit line contact 104a and the complementary bit line contact 104b disposed on the active region to which they are connected, and two adjacent second memory cells 112 share the bit line contact 104a and the complementary bit line contact 104b disposed on the active region to which they are connected.

In order to ensure the separation of the bit lines while reducing the length of the column memory cells in the longitudinal direction, a ground line contact 105a and a power line contact 105b are provided on the active region of the connection region 105. First memory cell 111 and second memory cell 112 share ground contact 105a, first memory cell 111 is connected to VSSD0 and VSSD1 through ground contact 105a, and second memory cell 112 is also connected to VSSD0 and VSSD1 through ground contact 105a, thereby separating the bit line and complementary bit line of the two memory cells while enabling the connection of VSSD0 and VSSD1 of the two memory cells. The first memory cell 111 and the second memory cell 112 share the power line contact 105b, the first memory cell 111 is connected to VC through the power line contact 105b, and the second memory cell 112 is also connected to one VC through the power line contact 105b, further ensuring that the bit lines and complementary bit lines of the two memory cells can be separated while achieving the connection of VC of the two memory cells.

In the embodiment of the application, the bit line contact and the complementary bit line contact are arranged on two sides of the connection area of the two storage units, so that the two storage units are connected with different bit lines and complementary bit lines, the load on each bit line is reduced by half, the operation speed of the storage unit pair is further improved, and the function and the performance of the storage unit pair are guaranteed. The word lines are reduced by half, so that the wiring resources in the word line routing direction are saved by half. The bit line contact and the complementary bit line contact are shared by two adjacent memory cells, so that the splicing area of the memory cell pair is reduced, and the length of the column memory cells in the column direction is reduced.

The above is a description of the memory cell pair 110 in the present application. Since the first memory cell 111 and the second memory cell 112 are similar in structure, differing only in the connected bit line and the complementary bit line, the first memory cell 111 referred to in the present application will be described in detail based on the memory cell pair 110 described above in fig. 1 a.

Fig. 1a shows the layout of active area 102 and polysilicon 103. The active region 102 is a rectangular region filled with a diagonal ("\") pattern in fig. 1a, and the polysilicon 103 is a rectangular region perpendicular to L1 and filled with a grid pattern in fig. 1 a. Referring to fig. 1a, the first memory cell 111 includes: the semiconductor device includes a semiconductor substrate 101, a pass transistor PG, a pull-down transistor PD formed on the semiconductor substrate 101, and first to nth metal layers (the first to nth metal layers are not shown in fig. 1 a) stacked from bottom to top on the pass transistor PG, and the pull-down transistor PD. Where the semiconductor substrate 101 comprises silicon, other exemplary compositions include, but are not limited to, silicon germanium, silicon carbide, gallium arsenide, indium phosphide, silicon germanium carbide, gallium arsenide phosphide, gallium indium phosphide, germanium, and/or other suitable materials. The metal layer is usually for better metal wiring, and the size of N specifically needs to be set in combination with actual wiring requirements, alternatively, N is 5, and the following description will take N as 5 as an example. Pass transistor PG, pull-down transistor PD, and pull-up transistor PU are each symmetrically distributed at L1. It should be understood that the connection region refers to an active region shared by the first and

second memory cells

111 and 112 and first to nth metal layers connected together; the first edge region refers to an active region on the left side of the polysilicon in the two pass transistors PG in the first memory cell 111 and the first to nth metal layers connected together.

Fig. 1b shows the structure of the first metal layer M1 in fig. 1. With continuing reference to FIG. 1b in addition to FIG. 1a, pass transistor PG, pull-down transistor PD, and pull-up transistor PU of first memory cell 111 above L1 are described.

The active region between the polysilicon 103 in the pass transistor PG and the pull-down transistor PD is shared; the active region on the left side of the polysilicon in the pull-up transistor PU is connected to the active region shared between the pass transistor PG and the pull-down transistor PD through a first metal layer M1. Of course, in practical applications, the active region may also be connected through another metal layer other than the first metal layer M1, which is not specifically limited in this embodiment of the present application and specifically needs to be determined in combination with actual requirements. It should be understood that the pull-up transistor PU performs heavy P-type doping, N-well and high P-type threshold voltage pipe recognition to fabricate an electrode, and the pull-down transistor PD and the pass transistor PG performs heavy N-type doping and high N-type threshold voltage pipe recognition to fabricate an electrode.

The pass transistor PG is connected to BL0, and is provided with a bit line contact 104a, a storage node PGa, and a word line contact PGb. Wherein the bit line contact 104a is disposed in the active area to the left of the polysilicon in pass transistor PG. It should be appreciated that the active area to the left of the polysilicon in pass transistor PG is made with a drain. In other words, BL0 is connected to the drain of pass transistor PG through bit line contact 104a and first metal layer M1. The storage node PGa is disposed in the active region of the pass transistor PG at the right side of the polysilicon. The word line contact PGb is disposed on the polysilicon outside the active region in the pass transistor PG. It should be understood that pass transistor PG is fabricated with a gate on polysilicon. In other words, WL is connected to the gate of pass transistor PG through word line contact PGb and first metal layer M1.

Pull-down transistor PD is connected to VSSD0 and is provided with ground contact 105 a. Ground contact 105a is disposed in the active region to the right of the polysilicon in pull-down transistor PD. It should be appreciated that the active area to the right of the polysilicon in the pull-down transistor PD is made active. In other words, VSSD0 is connected to the source of pull-down transistor PD through ground contact 105a and first metal layer M1.

The pull-up transistor PU is connected to the VC and is provided with a power line contact 105b, an active area contact PUa and a self-locking contact PUb. Wherein the power supply line contact 105b is provided in the active area to the right of the polysilicon in the pull-up transistor PU. It should be appreciated that the active area to the right of the polysilicon in pull-up transistor PU makes the active source. In other words, VC is connected to the source of pull-up transistor PU through power supply line contact 105b and first metal layer M1. An active area contact PUa is provided to the active area to the left of the polysilicon in the pull-up transistor PU. The active region to the left of the polysilicon in pull-up transistor PU is connected to the active region common to pass transistor PG and pull-down transistor PD through an active region contact PUa and a first metal layer M1. Self-locking contact PUc is disposed on the polysilicon in pull-up transistor PU. It should be understood that the pull-up transistor PU has a gate fabricated on the polysilicon.

It should be understood that the pass transistor PG, the pull-down transistor PD, and the pull-up transistor PU of the first memory cell 111 below and above L1 are identical in structure, except that the pass transistor PG in the first memory cell 111 below L1 is provided with a complementary bit line contact 104b, the BLB0 is connected to the drain of the pass transistor PG through the complementary bit line contact 104b and the first metal layer M1, and the pull-down transistor PD below L1 is connected to VSSD 1. The arrangement of the pass transistor PG, the pull-down transistor PD, and the pull-up transistor PU of the first memory cell 111 and the second memory cell 112 are the same, except that the bit line contact 104a provided in the right-side active region of polysilicon in the pass transistor PG above L1 in the second memory cell 112 is connected to BL1, and the complementary bit line contact 104b provided in the right-side active region of polysilicon in the pass transistor PG above L1 is connected to BLB 1.

In practical applications, the two pull-down transistors PD and the two pull-up transistors PU in the first memory unit 111 form a self-locking structure, so as to implement data caching. In one possible embodiment, referring to fig. 1a and 1b, the polysilicon in the pull-up transistor PU above L1 is connected to the active region on the left side of the polysilicon in the pull-down transistor PD below L1 through the self-locking contact PUb thereon and the first metal layer M1; fig. 2 shows the layout design of the second metal layer not shown in fig. 1, and referring to fig. 1a and fig. 2, the polysilicon in the pull-up transistor PU2 below L1 is connected to the active region on the left side of the polysilicon in the pull-down transistor PD above L1 through the self-locking contact PUb above it and the self-locking line M2a in the second metal layer M2. Here, the self-locking wire may also be disposed on another metal layer, which is not specifically limited in this embodiment of the application, and the metal layer on which the self-locking wire is disposed needs to be determined by combining with an actual situation.

It should be noted that the polysilicon in the pull-up transistor PU above L1 and the pull-up transistor PU below L1 are separated by a partition layer in the middle of the same lane (not shown in fig. 1).

Next, the wirings of the first to fifth metal layers and the connection relationship between different metal layers in the first memory cell 111 will be described in more detail.

Fig. 2 to 5 show layout designs of the second metal layer M2 to the fifth metal layer M5, respectively, which are omitted from fig. 1. Referring to fig. 2 to 5, in one possible implementation, VSSD0, BL0, BL1, BLB0, BLB1 and VSSD1 are disposed on the second metal layer M2, WL is disposed on the second metal layer M2 to the fifth metal layer M5, and VC is disposed on the second metal layer M2 to the fourth metal layer M4. Two word lines are disposed in the second metal layer M2 to the fourth metal layer M4, and for convenience of distinction, the two word lines are WL01 and WL02, which will be described below with WL01 and WL02 as examples. Specifically, WL01 in the second metal layer is connected to the polysilicon in pass transistor PG through word line contact PG1 above L1; WL02 is connected to the polysilicon in pass transistor PG by word line contact PG1 below L1.

It should be understood that although fig. 1 to 5 do not show an insulating layer, in practical applications, an insulating layer is disposed between any two adjacent metal layers, the first metal layer and the active region 102, and the insulating layer generally needs to be provided with an interlayer via hole, which is provided with a conductive plug to realize electrical interconnection with each device and between each device on the semiconductor substrate 101. Alternatively, the interconnection of different metal layers is realized by the active region 102, the conductive plug between the polysilicon 103 and the first metal layer, the first metal layer M1, the conductive plug between the first metal layer M1 and the second metal layer M2, the second metal layer M2, the conductive plug between the second metal layer M2 and the third metal layer M3, the third metal layer M3, the conductive plug between the third metal layer M3 and the fourth metal layer M4, the fourth metal layer M4, the conductive plug between the fourth metal layer M4 and the fifth metal layer M5, and the fifth metal layer M5. Although only 5 metal layers are shown in the embodiments, any number of metal layers may be provided in practical applications and used to implement the present application. Each metal layer may comprise a conductive material of aluminum, an aluminum alloy (e.g., aluminum/silicon/copper), copper, a copper alloy, titanium nitride, tantalum nitride, tungsten, a silicide, polysilicon, and/or other suitable conductive materials. In practical applications, damascene and/or dual damascene processes are used to form metal layers. Each insulating layer may comprise tetraethyl orthosilicate (TEOS) oxide, undoped silicate glass, or a suitable dielectric material of MLI structure such as borophosphosilicate glass (BPSG), Fused Silica Glass (FSG), phosphosilicate glass (PSG), doped silicon oxide of boron doped silicon glass (BSG), and/or other suitable dielectric materials insulated from each other. The conductive plugs of the interlayer vias may comprise copper, tungsten, and/or other suitable conductive materials. VSSD, BL, BLB, VC, WL may each be a conductive material including aluminum, aluminum alloys (e.g., aluminum/silicon/copper), copper alloys, titanium nitride, tantalum nitride, tungsten, silicide, polysilicon, and/or other suitable conductive materials.

In some possible implementations, a conductive plug connected to VSSD is disposed on each insulating layer under second metal layer M2 of connection region 105 to enable VSSD0 and VSSD1 in second metal layer M2 to be connected to corresponding ground contact 105 a. It will be appreciated that the lowermost insulating layer below second metal layer M2 provides a conductive plug directly above ground contact 105 a.

Each insulating layer under the fourth metal layer M4 of the connection region 105 is provided with a conductive plug connecting VC to make a VC connection in the second metal layer M2 to the fourth metal layer M4 and connect VC to the power line contact 105 b. It will be appreciated that the conductive plug provided by the lowermost insulating layer below the fourth metal layer M2 is directly above the power line contact 105 b.

Conductive plugs connecting BL0 and BLB0 are provided for each insulating layer under the second metal layer M2 of the edge region 104 to enable connection of BL0 and BLB0 in the second metal layer to the corresponding bit line contact 104a and complementary bit line contact 104 b. Specifically, the conductive plugs of the lowermost insulating layer below second metal layer M2 are disposed directly above bit line contact 104a and complementary bit line contact 104 b; the 2 conductive plugs in the insulating layers of the first metal layer M1 and the second metal layer M2 are disposed one directly below BL0 for connection to BL0 and the other directly below BLB0 for connection to BLB 0. The second memory cell 112 is similar to the first memory cell 111, but the 2 conductive plugs in the insulating layers of the first metal layer M1 and the second metal layer M2 in the second edge region 20 are disposed one directly under BL1 for connection to BL1 and the other directly under BLB1 for connection to BLB 1.

The wiring of each metal layer will be described in detail below.

Referring to fig. 2, the second metal layer M2 is sequentially provided with WL01, VSSD0, BL0, BL1, BLB0, BLB1, VSSD1, WL02 parallel to L1, VC perpendicular to L1, and a self-locking line M2a from top to bottom, where VC is located in the connection region 105.

Referring to fig. 3, the third metal layer M3 is sequentially disposed from top to bottom with WL01, VC, and WL02 perpendicular to L1, wherein WL01, VC, and WL02 are located in the connection region 105.

Referring to fig. 4, the fourth metal layer M4 is sequentially disposed with WL01, VC, and WL02 parallel to L1 from top to bottom, wherein VC is disposed in the middle region of the first memory cell 111, thereby allowing the first memory cell 111 and the second memory cell 112 to share VC.

Referring to fig. 5, the fifth metal layer M5 is provided with a WL perpendicular to the arrangement direction L1, and the WL is located in the connection region 105.

It should be understood that the above-mentioned wiring in the second to fifth metal layers M5 is only one possible implementation manner, and the embodiments of the present application are not intended to limit the wiring manner in the second to fifth metal layers M5, and the specific requirements need to be determined in combination with actual requirements.

The above is a detailed description of the memory cell pair, and by adopting the memory cell pair, bit lines are doubled, the load on each bit line is correspondingly reduced by half, the operation speed is faster than before, and the function and the performance are more guaranteed than before; and the word line is reduced by half, so that the wiring resource in the word line wiring direction is saved by half. Meanwhile, reasonable layout design is adopted, and the size and the running speed of the memory array are considered.

In a second aspect, an embodiment of the present application provides an FPGA. The FPGA includes the memory array of any of the embodiments described above.

The above description is only an example of the present application and is not intended to limit the present application. Various modifications and changes may occur to those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the scope of the claims of the present application.

Claims

1. A memory array, wherein each column of memory cells in the memory array comprises:

a plurality of memory cells arranged in a row in an arrangement direction, a bit line contact and a complementary bit line contact being provided in a first edge region of each of the memory cells, the plurality of memory cells including a pair of memory cells divided into a first memory cell and a second memory cell in an adjacent relationship, second edge regions of the first memory cell and the second memory cell being connected to form a connection region, the connection region being located between the first edge regions of the first memory cell and the second memory cell;

the two complementary bit lines are respectively connected with the complementary bit line contacts of the first storage unit and the second storage unit in each storage unit pair in a one-to-one corresponding mode;

and each memory cell is connected with a word line, and the first memory cell and the second memory cell in the memory cell pair share one word line.

2. The memory array of claim 1, wherein the plurality of memory cells are arranged in a column in an arrangement direction in a manner of a first memory cell, a second memory cell, and a first memory cell;

the first edge regions of two adjacent first memory cells in the plurality of memory cells are connected, so that the two adjacent first memory cells share a bit line contact and a complementary bit line contact;

the first edge regions of two adjacent second memory cells in the plurality of memory cells are connected so that the two adjacent second memory cells share a bit line contact and a complementary bit line contact.

3. The memory array of claim 1, wherein the memory cells comprise:

a plurality of transistors at least including two transmission transistors, two pull-down transistors and two pull-up transistors symmetrically arranged with a target center line, the target center line being a center line of the column of memory cells along the arrangement direction;

the connection region at least comprises two pull-up transistors and an active region on the side, far away from the transmission transistor, of the active regions on the two sides of the polycrystalline silicon in the two pull-down transistors; the first edge area at least comprises active areas on two sides of polycrystalline silicon in the two transmission transistors, wherein the active areas are far away from one side of the connection area; the active region of one pass transistor in the first edge region provides a bit line contact and the active region of the other pass transistor provides a complementary bit line contact.

4. The memory array of claim 3, wherein the memory cells comprise:

the 1 st to Nth metal layers are arranged on the transistors from bottom to top, the second metal layer is provided with the two bit lines and two complementary bit lines, and N is a positive integer greater than 1;

wherein the insulating layer of the first edge region is provided with interlayer vias to connect the bit line to a bit line contact and the complementary bit line to the complementary bit line contact.

5. The memory array of claim 4, wherein two bit lines and two complementary bit lines of the first and second memory cells in the connection region are connected respectively;

the two bit lines are located on one side of the target centerline and the two complementary bit lines are located on the other side of the target centerline.

6. The memory array of claim 4, wherein the polysilicon in the pull-up transistor above the target centerline is connected to the active region on one side of the pass transistor adjacent to the active region on both sides of the polysilicon in the pull-down transistor below the target centerline through a first metal layer;

7. The memory array of claim 4, wherein the polysilicon in the pass transistor of each of the memory cells away from the target centerline is provided with a word line contact;

the word line contacts arranged on the first memory cell and the second memory cell in the memory cell pair are connected with the same word line.

8. The memory array of claim 4, wherein each of the memory cells is provided with a ground contact and a power line contact;

the column memory cell includes:

a ground line connected to a ground contact provided for each of the memory cells;

a power supply line connected to a power supply line contact provided for each of the memory cells;

wherein a first memory cell and a second memory cell of the pair of memory cells share a ground contact provided to an active region of a pull-down transistor and a power supply contact provided to an active region of a pull-up transistor of the connection region; the insulating layer of the connection region is provided with interlayer vias to connect the power line to the power line contact and the ground line to the ground line contact.

9. The memory array of claim 8, the power supply lines are disposed in second through ith metal layers, the ground lines are disposed in the second metal layer, the word lines are disposed in second through jth metal layers, and i and j are positive integers greater than 2;

wherein the power supply lines in the second to ith metal layers are connected to the power supply line contacts through interlayer vias provided in the 1 st to ith-1 st insulating layers of the connection region; word lines in the second to j-th metal layers are connected to the word line contact through interlayer through holes arranged on the 1 st to j-1 st insulating layers; word lines, power supply lines, and ground lines of the first memory cell and the second memory cell in the connection region are respectively connected.

10. The memory array of claim 9, the i being 4 and/or the j being 5;

word lines in the second metal layer are parallel to the bit lines, and word lines in the fifth metal layer are perpendicular to the bit lines and located in the connection area.