CN112765933A - Integrated circuit design method based on population optimization algorithm - Google Patents

Abstract

The invention provides an integrated circuit design method based on a population optimization algorithm, which belongs to the technical field of integrated circuits and includes the following steps: constructing a neural network model describing the mapping relationship between integrated circuit design parameters and performance indicators; constructing according to the requirements of integrated circuit performance indicators The optimization strategy of the integrated circuit design parameters; according to the neural network model and the optimization strategy, the population optimization algorithm is used to iteratively optimize the design parameters of the integrated circuit, and the integrated circuit design based on the population optimization algorithm is completed. Aiming at the problem that the existing integrated circuit research and development relies too much on the experience of designers and has low efficiency, the invention uses a population optimization algorithm to determine and optimize the size parameters of integrated circuit devices according to the formulated integrated circuit design parameter optimization strategy, so as to improve the integrated circuit design efficiency , can be applied to the design and development of integrated circuits.

Description

An Integrated Circuit Design Method Based on Population Optimization Algorithm

technical field

The invention belongs to the technical field of integrated circuits, and in particular relates to an integrated circuit design method based on a population optimization algorithm.

Background technique

Integrated circuits are a strategic, basic and leading industry that supports the development of modern society and safeguards national security, and is the "food" of the information technology industry. one. The development of integrated circuits, especially analog integrated circuits, relies more on the design experience of R&D personnel and repeated iterative simulation verification of software. Designers constantly adjust the size parameters of devices in integrated circuits to obtain the desired performance indicators of circuit modules. This time-consuming and labor-intensive design method reduces the integrated circuit design efficiency, increases the R&D cost, and prolongs the integrated circuit chip development cycle.

In recent years, population optimization methods have developed rapidly, and have been widely used in industrial design and production processes due to their simple structure, easy implementation and fast convergence speed. In addition, the population optimization method is a heuristic optimization method, and there is no restriction that the optimization objective function can be derivable, which can ensure the rationality and validity of the optimization results. Under the framework of the population optimization algorithm, the method of the invention takes the performance index of the integrated circuit as the goal, and proposes a simple and effective intelligent optimization method for the size parameters of the integrated circuit device, which provides an efficient method and approach for developing integrated circuit chips.

SUMMARY OF THE INVENTION

In view of the above deficiencies in the prior art, the present invention provides an integrated circuit design method based on a population optimization algorithm, which solves the problems that the existing integrated circuit research and development relies too much on the experience of designers and has low efficiency.

In order to achieve the above purpose, the technical scheme adopted in the present invention is:

This solution provides an integrated circuit design method based on a population optimization algorithm, including the following steps:

S1. Construct a neural network model that describes the mapping relationship between integrated circuit design parameters and performance indicators;

S2. Construct an optimization strategy for integrated circuit design parameters according to the requirements of integrated circuit performance indicators;

S3. According to the neural network model and the optimization strategy, use the population optimization algorithm to iteratively optimize the design parameters of the integrated circuit, and complete the integrated circuit design based on the population optimization algorithm.

The beneficial effects of the present invention are as follows: the present invention aims at the problem that the existing integrated circuit research and development relies too much on the experience of designers and has low efficiency. According to the formulated integrated circuit design parameter optimization strategy, the population optimization algorithm is used to determine and optimize the size of the integrated circuit device. parameters, improve the efficiency of integrated circuit design, and can be applied to the design and development of integrated circuits. The invention and popularization and application of the method have important engineering significance for reducing the development cost and shortening the development cycle of integrated circuit chips.

Further, the step S1 includes the following steps:

S101, using an orthogonal design method to determine a combination of integrated circuit design parameters, and using integrated circuit simulation software to obtain performance index simulation data corresponding to all design parameters;

S102. Use a back-propagation algorithm to train the performance index simulation data, and construct a neural network model that describes the mapping relationship between integrated circuit design parameters and performance indexes.

Still further, the expression of constructing a neural network model describing the mapping relationship between the integrated circuit design parameters and performance indicators in the step S102 is as follows:

P=g]W ₂ ·g(W ₁ ·U+b ₁ )+b ₂ ]

Among them, g( ) represents the activation function of the neural network model, e- ^x represents the exponential function with the natural constant e as the base, P and U represent the performance indicators and design parameters of the integrated circuit, respectively, and W ₁ and b ₁ represent the neural network, respectively The weight matrix and bias term from the input layer to the hidden layer in the model, W ₂ and b ₂ represent the weight matrix and bias term from the hidden layer to the output layer in the neural network model.

The beneficial effects of the above-mentioned further scheme are: the present invention describes the mapping relationship between the integrated circuit design parameters and the performance indicators by constructing a neural network model, and can accurately and quickly predict the integrated circuit performance indicators according to the design parameters, which is beneficial to the rapid optimization of the integrated circuit design parameters. .

Still further, the expression of the optimization strategy of the integrated circuit design parameters in the step S2 is as follows:

J=α(GG _des ) ² +β(GBW-GBW _des ) ²

Among them, J represents the optimization strategy of integrated circuit design parameters, G represents the gain of the integrated circuit, GBW represents the gain-bandwidth product of the integrated circuit, G _des and GBW _des represent the expected integrated circuit gain and gain-bandwidth product, respectively, α and β represent the Optimized weighting factor for the gain and gain-bandwidth product of an integrated circuit.

The beneficial effects of the above-mentioned further scheme are: the present invention points out the direction for the optimization of the integrated circuit design parameters by constructing an optimization strategy of the integrated circuit design parameters according to the requirements of the integrated circuit performance indicators, which is beneficial to improve the integrated circuit design efficiency.

Still further, the step S3 includes the following steps:

S301. Initialize the parameters of the population optimization algorithm;

S302. According to the design parameters of the integrated circuit, use the constructed neural network model to predict the performance index of the integrated circuit;

S303. According to the constructed optimization strategy and the predicted integrated circuit performance index, use a population optimization algorithm to optimize the design parameters of the integrated circuit;

S304: Determine whether to obtain the optimal integrated circuit design parameters, if yes, complete the integrated circuit design based on the population optimization algorithm, otherwise, return to step S302.

The beneficial effects of the above-mentioned further scheme are: by using the population optimization algorithm to optimize the integrated circuit design parameters, the present invention can efficiently determine the design size parameters of the integrated circuit device, improve the integrated circuit design efficiency, reduce the research and development cost, and shorten the development cycle of the integrated circuit chip.

Description of drawings

FIG. 1 is a flow chart of the method of the present invention.

FIG. 2 is a diagram of a PMOS input differential pair integrated circuit of a resistive load in this embodiment.

FIG. 3 is a schematic diagram of size parameters of integrated circuit devices obtained based on a population optimization algorithm in this embodiment.

FIG. 4 uses Cadence software to simulate experimental results according to the optimized integrated circuit design parameters in this embodiment.

Detailed ways

The specific embodiments of the present invention are described below to facilitate those skilled in the art to understand the present invention, but it should be clear that the present invention is not limited to the scope of the specific embodiments. For those of ordinary skill in the art, as long as various changes Such changes are obvious within the spirit and scope of the present invention as defined and determined by the appended claims, and all inventions and creations utilizing the inventive concept are within the scope of protection.

Example

As shown in FIG. 1 , the present invention provides an integrated circuit design method based on a population optimization algorithm, and its implementation method is as follows:

S1. Construct a neural network model that describes the mapping relationship between integrated circuit design parameters and performance indicators. The implementation method is as follows:

S101, using an orthogonal design method to determine a combination of integrated circuit design parameters, and using integrated circuit simulation software to obtain performance index simulation data corresponding to all design parameters;

S102, using the back-propagation algorithm to train the performance index simulation data, and constructing a neural network model describing the mapping relationship between the integrated circuit design parameters and the performance index, the expression of which is as follows:

P=g[W ₂ ·g(W ₁ ·U+b ₁ )+b ₂ ]

Among them, g( ) represents the activation function of the neural network model, e- ^x represents the exponential function with the natural constant e as the base, P and U represent the performance indicators and design parameters of the integrated circuit, respectively, and W ₁ and b ₁ represent the neural network, respectively The weight matrix and bias term from the input layer to the hidden layer in the model, W ₂ and b ₂ represent the weight matrix and bias term from the hidden layer to the output layer in the neural network model;

S2. Construct an optimization strategy for integrated circuit design parameters according to the requirements of integrated circuit performance indicators;

The expression of the optimization strategy of the integrated circuit design parameters is as follows.

J=α(GG _des ) ² +β(GBW-GBW _des ) ²

Among them, J represents the optimization strategy of integrated circuit design parameters, G represents the gain of the integrated circuit, GBW represents the gain-bandwidth product of the integrated circuit, G _des and GBW _des represent the expected integrated circuit gain and gain-bandwidth product, respectively, α and β represent the Optimized weight coefficients for gain and gain-bandwidth product of integrated circuits;

S3. According to the neural network model and the optimization strategy, use the population optimization algorithm to iteratively optimize the design parameters of the integrated circuit, and complete the integrated circuit design based on the population optimization algorithm. The implementation method is as follows:

S301. Initialize the parameters of the population optimization algorithm;

S302. According to the design parameters of the integrated circuit, use the constructed neural network model to predict the performance index of the integrated circuit;

S303. According to the constructed optimization strategy and the predicted integrated circuit performance index, use a population optimization algorithm to optimize the design parameters of the integrated circuit;

S304: Determine whether to obtain the optimal integrated circuit design parameters, if yes, complete the integrated circuit design based on the population optimization algorithm, otherwise, return to step S302.

The following is an example of designing a PMOS input differential pair circuit with a resistive load, as shown in Figure 2, where Vbias is the bias voltage provided by the external circuit, Vin+ and Vin- are the positive and negative terminals of the differential input signal, Vout+ and Vout - They are the positive and negative terminals of the differential output signal, respectively. The power supply voltage VDD is connected to the source of the transistor M3, the gate of the transistor M3 is connected to the external bias voltage Vbias, and the drain of the transistor M3 is connected to the sources of the transistors M1 and M2 in two ways. The gate of the transistor M1 is connected to the positive terminal Vin+ of the differential input signal, and the drain of the transistor M1 is connected to the positive terminal Vout+ of the differential output signal and one end of the resistor R1 in two ways, and the other end of the resistor R1 is connected to the ground GND; the transistor The gate of M2 is connected to the negative terminal Vin- of the differential input signal, and the drain of the transistor M2 is connected to the positive terminal Vout- of the differential output signal and one end of the resistor R2 is connected to the ground GND respectively.

The implementation details of the integrated circuit intelligent design method involved in the present invention are introduced in detail, and the method includes:

Step 1: Build a neural network model that can accurately describe the mapping relationship between integrated circuit design parameters and performance indicators;

The design parameters of the resistive load PMOS (P-type metal-oxide-semiconductor) transistor input differential pair circuit include the size of the two PMOS input tubes, the size of the tail current source tube and the load resistance value. Its performance indicators mainly include gain and gain-bandwidth product. . The neural network model describing the mapping relationship between circuit design parameters and performance indicators of the PMOS input differential pair of resistive loads is obtained by the Cadence software combined with the orthogonal design method to obtain simulated experimental data, and is established by back-propagation algorithm training. This neural network model includes an input layer. , hidden layer and output layer, the neural network model of resistive load PMOS input differential pair circuit gain G can be expressed as:

U是设计参数向量；W₁ ^G和

表示神经网络模型中输入层到隐含层的权值矩阵和偏置项；

和

表示神经网络模型中隐含层到输出层的权值矩阵和偏置项。Among them, the activation function of the neural network model

U is the design parameter vector; W ₁ ^G and

Represents the weight matrix and bias term from the input layer to the hidden layer in the neural network model;

and

Represents the weight matrix and bias term from the hidden layer to the output layer in the neural network model.

The neural network model of the gain-bandwidth product GBW of the PMOS input differential pair circuit with resistive load can be expressed as:

表示神经网络模型中输入层到隐含层的权值矩阵和偏置项；

和

表示神经网络模型中隐含层到输出层的权值矩阵和偏置项。where W ₁ ^GBW and

Represents the weight matrix and bias term from the input layer to the hidden layer in the neural network model;

and

Represents the weight matrix and bias term from the hidden layer to the output layer in the neural network model.

Step 2: Formulate optimization criteria for integrated circuit design parameters according to performance index requirements;

The performance indicators of the PMOS input differential pair circuit of the resistive load mainly include gain and gain-bandwidth product. The expected gain and gain-bandwidth product are 20dB and 143MHz respectively, and the optimization weight coefficients are respectively taken as 0.5. It can be expressed as:

J=0.5(G-20) ² +0.5(GBW-143) ²

where G _des and GBW _des represent the desired gain and gain-bandwidth product, respectively.

Step 3: Integrate the established neural network model and the formulated optimization criteria into the population optimization algorithm, and iteratively determine and optimize the design parameters of the integrated circuit;

Particle swarm optimization algorithm is a commonly used population optimization algorithm, which has the advantages of simple structure and easy implementation. Integrate the established neural network model and optimization criteria into the particle swarm optimization algorithm, and use the particle swarm optimization algorithm with linearly decreasing inertia weight to optimize the design parameters of the PMOS input differential pair circuit of resistive load, and the particle swarm optimization with linearly decreasing inertia weight. The algorithm can be described as:

v _i (t+1)=wv _i (t)+c ₁ r ₁ ( _{pi -x i (} t))+c ₂ r ₂ (p _{g -xi} (t))

x _i (t+1)=x _i (t)+v _i (t+1)

Where: x _i and v _i represent the position vector and velocity vector of the ith particle, respectively, w represents the inertia weight, pi represents the local optimal position, p _{g represents} the global optimal position, c ₁ and c ₂ are constants, r ₁ and r ₂ are random numbers between [0, 1], iter represents the current number of iterations, iter _max represents the maximum number of iterations, and w _max and w _min represent the maximum and minimum values of inertial weights, respectively. The process of optimizing the design parameters of the resistive-loaded PMOS input differential pair circuit using the particle swarm optimization algorithm with linearly decreasing inertia weights is as follows:

(1) Initialize the parameters of the particle swarm optimization algorithm, as shown in Table 1. Table 1 is the initialization parameters of the particle swarm optimization algorithm.

Table 1

(2) According to the design parameters of the PMOS input differential pair circuit of the resistive load, use the constructed neural network model to predict the performance index of the PMOS input differential pair circuit of the resistive load;

(3) According to the constructed optimization criterion and the performance index of the predicted resistance-loaded PMOS input differential pair circuit, the population optimization algorithm is used to optimize the design parameters of the resistance-loaded PMOS input differential pair circuit;

(4) judging whether the optimal PMOS input differential pair circuit design parameters of the resistive load are obtained, if so, complete the design of the integrated circuit, otherwise return to step (2).

In this embodiment, according to the expected performance index, the design parameters of the PMOS input differential pair circuit of the resistive load are optimized by using the above-mentioned integrated circuit intelligent design method. The optimized input tube size, tail current source tube size (channel width/channel length) and load resistance are 29μm/0.18μm, 33μm/0.18μm and 6KΩ, respectively, as shown in Figure 3. According to the optimized PMOS input differential pair circuit design parameters of resistive load, the experimental results simulated by Cadence software are shown in Figure 4. The gain and gain-bandwidth product of the resistive load PMOS input differential pair circuit are 18.03dB and 141.49MHz, respectively, almost reaching The expected performance index is obtained, which shows that the proposed method can effectively optimize the design parameters of the PMOS input differential pair circuit with resistive load, and obtain an integrated circuit that meets the performance requirements.

From the above results, it can be found that the method proposed by the present invention can simply and effectively optimize the design parameters of the integrated circuit, shorten the research and development cycle of the integrated circuit, and provide a reliable way to realize the efficient design of the integrated circuit.

Claims (5)

1. An integrated circuit design method based on a population optimization algorithm is characterized by comprising the following steps:

s1, constructing a neural network model for describing the mapping relation between the design parameters and the performance indexes of the integrated circuit;

s2, constructing an optimization strategy of integrated circuit design parameters according to the requirements of the integrated circuit performance indexes;

and S3, according to the neural network model and the optimization strategy, iteratively optimizing the design parameters of the integrated circuit by using a population optimization algorithm, and finishing the integrated circuit design based on the population optimization algorithm.

2. The population optimization algorithm-based integrated circuit design method according to claim 1, wherein the step S1 comprises the steps of:

s101, determining an integrated circuit design parameter combination by using an orthogonal design method, and obtaining performance index simulation data corresponding to all design parameters by using integrated circuit simulation software;

and S102, training the performance index simulation data by using a back propagation algorithm, and constructing a neural network model for describing the mapping relation between the design parameters of the integrated circuit and the performance indexes.

3. The population optimization algorithm-based integrated circuit design method according to claim 2, wherein the expression of the neural network model describing the mapping relationship between the integrated circuit design parameters and the performance indicators is constructed in step S102 as follows:

P＝g[W₂·g(W₁·U+b₁)+b₂]

wherein g (-) represents the activation function of the neural network model, e^-xExpressing an exponential function based on a natural constant e, P and U respectively expressing the performance index and design parameter of the integrated circuit, W₁ and b₁Respectively representing the weight matrix and the bias term from the input layer to the hidden layer in the neural network model, W₂ and b₂And representing weight matrixes and bias items from a hidden layer to an output layer in the neural network model.

4. The population optimization algorithm-based integrated circuit design method according to claim 1, wherein the expression of the optimization strategy of the integrated circuit design parameters in step S2 is as follows:

J＝α(G-G_des)²+β(GBW-GBW_des)²

wherein J represents the optimization strategy of the design parameters of the integrated circuit, G represents the gain of the integrated circuit, GBW represents the gain-bandwidth product of the integrated circuit, G_des and GBW_desRepresenting the desired gain and gain-bandwidth product of the integrated circuit, respectively, and alpha and beta represent the optimized weight coefficients of the gain and gain-bandwidth product of the integrated circuit, respectively.

5. The population optimization algorithm-based integrated circuit design method according to claim 1, wherein the step S3 comprises the steps of:

s301, initializing parameters of a population optimization algorithm;

s302, predicting the performance index of the integrated circuit by using the built neural network model according to the design parameters of the integrated circuit;

s303, optimizing design parameters of the integrated circuit by using a population optimization algorithm according to the constructed optimization strategy and the predicted performance index of the integrated circuit;

s304, judging whether to obtain the optimal design parameters of the integrated circuit, if so, finishing the design of the integrated circuit based on the population optimization algorithm, otherwise, returning to the step S302.

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