CN112379715B - Low-noise band-gap reference circuit - Google Patents

Abstract

The invention discloses a low-noise band gap reference circuit, which belongs to the field of analog circuits. The low-noise bandgap reference circuit includes a current source S1, PNP transistors Q1-Q9, PMOS transistors M1-M8, NMOS transistors M9-M11, resistors R1 and R2, wherein PNP transistors Q1, Q2, Q3 and NMOS transistors M9-M11 Constitute the amplifier structure. Through the connection of this structure, the reference voltage V _REF can be independent of temperature and power supply voltage changes, the influence of noise and transistor mismatch voltage can be reduced, and a constant output voltage can be maintained within a certain temperature and bias current range.

Description

A Low Noise Bandgap Reference Circuit

technical field

The invention relates to the technical field of analog circuits, in particular to a low-noise bandgap reference circuit.

Background technique

Bandgap reference circuits provide a constant output reference voltage, and if the output reference voltage V _REF is over a temperature or bias current range, even a small change, say a few hundred millivolts, can be a problem. Therefore, it would be desirable to have a bandgap reference circuit that provides a substantially constant output reference voltage V _REF over a range of temperature and bias current.

Conventional standard CMOS bandgap reference circuits typically include an amplifier containing a pair of P-channel MOS transistors. Excess charge carriers can be trapped in the silicon and silicon dioxide surfaces of MOS transistors, and the excess charge can cause a change in the threshold voltage of the MOS transistors in the differential pair of amplifiers. For example, the threshold voltages of two MOS transistors in a differential pair may differ by more than 5mV. This difference introduces a voltage mismatch into the amplifier in the bandgap reference circuit, which affects the reference voltage _VREF . In addition, the charge trapped on the silicon and silicon dioxide surfaces of the differential pair MOS transistors of the bandgap reference amplifier varies with time, causing _VREF to vary with time, even at constant temperature. Variations in _VREF can cause unwanted 1/f output noise. Additionally, due to the characteristics of MOS transistors, the P-channel MOS transistors in a differential pair may introduce thermal noise at _VREF , which is also undesirable.

Another disadvantage of conventional standard CMOS bandgap reference circuits is that they are sensitive to relatively small changes in the supply voltage V _CC . A small change in V _CC will cause a change in the bias current of the bandgap reference circuit, which will also have an effect on the reference voltage V _REF .

Therefore, we would like to provide a less noisy bandgap reference circuit that provides a constant output reference voltage V _REF over a range of supply voltage and temperature.

SUMMARY OF THE INVENTION

The purpose of the present invention is to provide a low-noise bandgap reference circuit, so as to solve the problem that noise affects the reference voltage _VREF in the conventional CMOS bandgap reference circuit.

In order to solve the above technical problems, the present invention provides a low-noise bandgap reference circuit, comprising a current source S1, PNP transistors Q1-Q9, PMOS transistors M1-M8, NMOS transistors M9-M11, resistors R1 and R2; wherein,

One end of the current source S1 is connected to the power supply voltage V _CC , and the other end is connected to the emitter of the PNP transistor Q3 and the PMOS transistors M1-M8, and the gates of the PMOS transistors M1-M8 are interconnected and connected to the drain of the P-type MOS transistor M5. , forming a current mirror structure;

The drain of the PMOS transistor M1 is connected to the first input end of the resistor R1, the drain of the PMOS transistor M2 is connected to the emitter of the PNP transistor Q4, the drain of the PMOS transistor M3 is connected to the emitter of the PNP transistor Q6, and the drain of the PMOS transistor M4 is connected to the emitter of the PNP transistor Q6. The drain is connected to the emitter of the PNP transistor Q8, the drain of the PMOS transistor M5 is connected to the emitters of the PNP transistors Q1 and Q2, the drain of the PMOS transistor M6 is connected to the emitter of the PNP transistor Q9, and the drain of the PMOS transistor M7 is connected to the emitter of the PNP transistor Q9. The emitter of the PNP transistor Q7 is connected, and the drain of the PMOS transistor M8 is connected to the emitter of the PNP transistor Q5.

Optionally, the base of the PNP transistor Q4 is connected to the first input end of the resistor R1, the base of the PNP transistor Q6 is connected to the emitter of the PNP transistor Q4, the base of the PNP transistor Q8 is connected to the emitter of the PNP transistor Q6, The base of the PNP transistor Q9 is connected to the emitter of the PNP transistor Q7, the base of the PNP transistor Q7 is connected to the emitter of the PNP transistor Q5, the base of the PNP transistor Q5 is connected to the second input of the resistor R1, the PNP transistor Q4, The collectors of Q6, Q8, Q9, Q7, and Q5 are grounded.

Optionally, PNP transistors Q1, Q2, Q3 and NMOS transistors M9-M11 form an amplifier circuit;

The base of the PNP transistor Q1 is connected to the emitter of the PNP transistor Q8, the collector of the PNP transistor Q1 is connected to the drain of the NMOS transistor M9, the base of the PNP transistor Q2 is connected to the emitter of the PNP transistor Q9, and the collector of the PNP transistor Q2 The electrode is connected to the drain of the NMOS transistor M10, the gates of the NMOS transistors M9 and M10 are interconnected and connected to the drain of the NMOS transistor M9 to form a current mirror structure, the sources of the NMOS transistors M9 and M10 are grounded, and the gate of the NMOS transistor M11 The electrode is connected to the drain of the NMOS transistor M10, the drain of the NMOS transistor M11 is connected to the collector of the PNP transistor Q3, the source of the NMOS transistor M11 is grounded, and the base and the collector of the PNP transistor Q3 are interconnected to form a diode structure.

Optionally, the second input end of the resistor R1 is connected to the first input end of the resistor R2, and the second input end of the resistor R2 is grounded.

The low-noise bandgap reference circuit provided by the present invention includes a current source S1, PNP transistors Q1-Q9, PMOS transistors M1-M8, NMOS transistors M9-M11, resistors R1 and R2, among which the PNP transistors Q1, Q2, Q3 and NMOS transistors M9-M11 constitute an amplifier structure. Through the connection of this structure, the reference voltage V _REF can be independent of temperature and power supply voltage changes, reduce the influence of noise and transistor mismatch voltage, and maintain a constant output voltage within a certain temperature and bias current range.

Description of drawings

FIG. 1 is a schematic structural diagram of a low-noise bandgap reference circuit provided by the present invention.

Detailed ways

A low-noise bandgap reference circuit proposed by the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become apparent from the following description and claims. It should be noted that, the accompanying drawings are all in a very simplified form and in inaccurate scales, and are only used to facilitate and clearly assist the purpose of explaining the embodiments of the present invention.

Example 1

The present invention provides a low-noise bandgap reference circuit, the structure of which is shown in FIG. 1, including a current source S1, PNP transistors Q1-Q9, PMOS transistors M1-M8, NMOS transistors M9-M11, resistors R1 and R2; One end of the current source S1 is connected with the power supply voltage V _CC , and the other end is connected with the emitter of the PNP transistor Q3 and the PMOS transistors M1-M8, the gates of the PMOS transistors M1-M8 are interconnected and connected with the drain of the P-type MOS transistor M5 connected to form a current mirror structure; PNP transistors Q1, Q2, Q3 and NMOS transistors M9-M11 constitute an amplifier circuit;

The drain of the PMOS transistor M1 is connected to the first input end of the resistor R1, the drain of the PMOS transistor M2 is connected to the emitter of the PNP transistor Q4, the drain of the PMOS transistor M3 is connected to the emitter of the PNP transistor Q6, and the drain of the PMOS transistor M4 is connected to the emitter of the PNP transistor Q6. The drain is connected to the emitter of the PNP transistor Q8, the drain of the PMOS transistor M5 is connected to the emitters of the PNP transistors Q1 and Q2, the drain of the PMOS transistor M6 is connected to the emitter of the PNP transistor Q9, and the drain of the PMOS transistor M7 is connected to the emitter of the PNP transistor Q9. The emitter of the PNP transistor Q7 is connected, the drain of the PMOS transistor M8 is connected to the emitter of the PNP transistor Q5; the base of the PNP transistor Q4 is connected to the first input end of the resistor R1, and the base of the PNP transistor Q6 is connected to the PNP transistor Q4. The emitter is connected, the base of PNP transistor Q8 is connected to the emitter of PNP transistor Q6, the base of PNP transistor Q9 is connected to the emitter of PNP transistor Q7, the base of PNP transistor Q7 is connected to the emitter of PNP transistor Q5, PNP The base of the transistor Q5 is connected to the second input terminal of the resistor R1, the collectors of the PNP transistors Q4, Q6, Q8, Q9, Q7 and Q5 are grounded; the base of the PNP transistor Q1 is connected to the emitter of the PNP transistor Q8, and the PNP transistor The collector of Q1 is connected to the drain of the NMOS transistor M9, the base of the PNP transistor Q2 is connected to the emitter of the PNP transistor Q9, the collector of the PNP transistor Q2 is connected to the drain of the NMOS transistor M10, and the gates of the NMOS transistors M9 and M10 The electrodes are interconnected and connected to the drain of the NMOS transistor M9 to form a current mirror structure. The sources of the NMOS transistors M9 and M10 are grounded, the gate of the NMOS transistor M11 is connected to the drain of the NMOS transistor M10, and the drain of the NMOS transistor M11 is connected to The collector of the PNP transistor Q3 is connected, the source of the NMOS transistor M11 is grounded, and the base and the collector of the PNP transistor Q3 are interconnected to form a diode structure. The second input end of the resistor R1 is connected to the first input end of the resistor R2, and the second input end of the resistor R2 is grounded.

The low noise bandgap reference circuit receives the supply voltage V _CC from an external voltage source; the bias current source S1 with finite impedance provides a reference current source that outputs a current equal to 15I, for example, 15I represents 150uA at 25°C. The bias current source S1 is proportional to the absolute temperature. Therefore, the temperature change of the low noise bandgap reference circuit or the change of the power supply voltage V _CC will cause the current of the current source S1 to change.

The current of the bias current source S1 is divided by the PMOS transistors M1-M8 and the NMOS transistor M11, wherein the current of the PMOS transistors M1-M8 is divided according to a certain ratio, which is determined by the width-length ratio of the MOS transistors M1-M8 of the PMOS transistors . The ratio of transistors M1:M2:M3:M4:M5:M6:M7:M8 can be 4:1:1:1:1:1:1:1, and the current ratio is 4I:I:I:I:I:I:I :I:I, as shown in Figure 1. The W/L of the NMOS transistor M11 is 8 times that of the NMOS transistors M9 and M10. Other suitable transistor ratios may also be used, if desired, in accordance with the principles of the present invention.

The low-noise bandgap reference circuit also includes PNP transistors Q1 and Q2, which are differential pair transistors in the amplifier. When the base voltages of the PNP transistors Q1 and Q2 are equal, Q1 and Q2 each flow through I/2 current.

The low-noise bandgap reference circuit includes PNP transistors Q4-Q9, the base of the PNP transistor Q2 is connected to the output V _REF of the reference voltage, and its value is as follows:

V _REF =V _R2 +V _{BE_Q9} +V _{BE_Q7} +V _{BE_Q5} (1)

Wherein V _R2 is the voltage drop across the resistor R2, and V _{BE_Q9} , V _{BE_Q7} and V _{BE_Q5} are the BE junction voltages of the PNP transistors Q9, Q7 and Q5.

The base voltage of the PNP transistor Q1 is:

V _Q1 =V _R2 +V _R1 +V _{BE_Q8} +V _{BE_Q6} +V _{BE_Q4} (2)

Among them, V _R1 is the voltage drop across the resistor R1, and V _{BE_Q8} , V _{BE_Q6} and V _{BE_Q4} are the BE junction voltages of the PNP transistors Q8, Q6 and Q4.

The base-emitter junction area of the PNP transistors Q4, Q6 and Q8 is eight times the base-emitter junction area of the PNP transistors Q5, Q7 and Q9. Therefore the base-emitter voltage _VBE of the PNP transistors Q4, Q6 and Q8 is 26mV*ln(8)=54mV greater than the base-emitter voltage of the PNP transistors Q5, Q7 and Q9. So V _{BE_Q8} +V _{BE_Q6} +V _{BE_Q4} is 162mV larger than V _{BE_Q9} +V _{BE_Q7} +V _{BE_Q5} . For example, when resistor R1 is 4.05kΩ, the voltage drop across resistor R1 is 162mV and the current through resistor R1 is 40µA. When the base voltages of the PNP transistors Q1 and Q2 are equal, the low-noise bandgap reference circuit enters a stable state and the output voltage _VREF is constant.

The PNP transistors Q1 and Q2 are used as a differential pair, which will introduce a low offset voltage, which affects the constant of V _REF . The offset voltage of the bipolar transistor is 100-1000 times smaller than that of the MOS transistor. This embodiment uses three emitters. The triode structure provides three times the change in ΔV _BE , further reducing the effect of the offset voltage on the reference value V _REF .

This embodiment also has a certain resistance to small changes in the power supply voltage V _CC . When the power supply voltage V _CC increases, the current of the bias current source S1 increases, and the current through the resistors R1 and R2 also increases slightly, resulting in an increase in the base voltages of the transistors Q1 and Q2. Since the base voltage increment of the transistor Q4 is greater than the base voltage increment of the transistor Q5, the base voltage increment of the transistor Q1 is greater than the base voltage increment of the transistor Q2, so the current flowing through the transistor Q1 will drop, which is smaller than that through the transistor Q1. The current of Q2 causes the gate voltage of M11 to increase, the current flowing through M11 increases, and absorbs the current increase of the current source S1, thereby reducing the current increase of the resistors R1 and R2, forming a negative feedback loop, so that the flow through The currents of the PMOS transistors M1-M8 and the resistors R1 and R2 are kept constant. The NMOS transistor M11 makes the voltage drop on the resistor R2 constant at 162mV, the base voltages of Q1 and Q2 are both equal, and the output voltage V _REF has nothing to do with the first-order small signal change of V _CC .

In the present invention, "connected", "connected", "connected", "connected" and the like refer to words that are electrically connected, and unless otherwise specified, refer to direct or indirect electrical connection. The first port and the second port of all the above resistors are defined according to the flow direction of the current. One end of the current passing through the resistor first is the first port, and the other end is the second port.

The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes and modifications made by those of ordinary skill in the field of the present invention based on the above disclosure all belong to the protection scope of the claims.

Claims (2)

1. A low-noise band-gap reference circuit is characterized by comprising a current source S1, PNP triodes Q1-Q9, PMOS tubes M1-M8, NMOS tubes M9-M11, resistors R1 and R2; wherein,

one end of the current source S1 and the power voltage V_CCThe other end of the PNP triode Q3 is connected with an emitter of a PNP triode Q3 and PMOS tubes M1-M8, and gates of the PMOS tubes M1-M8 are connected with each other and connected with a drain of a P-type MOS tube M5 to form a current mirror structure;

the drain electrode of a PMOS tube M1 is connected with the first input end of a resistor R1, the drain electrode of a PMOS tube M2 is connected with the emitter electrode of a PNP triode Q4, the drain electrode of the PMOS tube M3 is connected with the emitter electrode of a PNP triode Q6, the drain electrode of a PMOS tube M4 is connected with the emitter electrode of the PNP triode Q8, the drain electrode of the PMOS tube M5 is connected with the emitter electrodes of a PNP triode Q1 and a PNP triode Q2, the drain electrode of the PMOS tube M6 is connected with the emitter electrode of the PNP triode Q9, the drain electrode of a PMOS tube M7 is connected with the emitter electrode of the PNP triode Q7, and the drain electrode of the PMOS tube M8 is connected with the emitter electrode of the PNP triode Q5;

the base of the PNP triode Q4 is connected with the first input end of the resistor R1, the base of the PNP triode Q6 is connected with the emitter of the PNP triode Q4, the base of the PNP triode Q8 is connected with the emitter of the PNP triode Q6, the base of the PNP triode Q9 is connected with the emitter of the PNP triode Q7, the base of the PNP triode Q7 is connected with the emitter of the PNP triode Q5, the base of the PNP triode Q5 is connected with the second input end of the resistor R1, and the collectors of the PNP triodes Q4, Q6, Q8, Q9, Q7 and Q5 are grounded;

the PNP triode Q1, the Q2, the Q3 and the NMOS tubes M9-M11 form an amplifier circuit; the base of a PNP triode Q1 is connected with the emitter of a PNP triode Q8, the collector of a PNP triode Q1 is connected with the drain of an NMOS tube M9, the base of the PNP triode Q2 is connected with the emitter of the PNP triode Q9, the collector of a PNP triode Q2 is connected with the drain of an NMOS tube M10, the gates of the NMOS tubes M9 and M10 are connected with each other and with the drain of the NMOS tube M9 to form a current mirror structure, the sources of the NMOS tubes M9 and M10 are grounded, the gate of the NMOS tube M11 is connected with the drain of the NMOS tube M10, the drain of the NMOS tube M11 is connected with the collector of the PNP triode Q3, the source of the NMOS tube M11 is grounded, and the base of the PNP triode Q3 is connected with the collector to form a diode structure.

2. The low noise bandgap reference circuit of claim 1, wherein a second input terminal of the resistor R1 is connected to a first input terminal of a resistor R2, and a second input terminal of the resistor R2 is connected to ground.

Images