CN112199325A - Reconfigurable computing implementation device and reconfigurable computing method for 3DES encryption and decryption algorithm - Google Patents
Reconfigurable computing implementation device and reconfigurable computing method for 3DES encryption and decryption algorithm Download PDFInfo
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- CN112199325A CN112199325A CN202011165615.1A CN202011165615A CN112199325A CN 112199325 A CN112199325 A CN 112199325A CN 202011165615 A CN202011165615 A CN 202011165615A CN 112199325 A CN112199325 A CN 112199325A
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Abstract
The invention provides a reconfigurable computation realization device and a reconfigurable computation method of a 3DES encryption and decryption algorithm, comprising a 3DES encryption and decryption controller, wherein the 3DES encryption and decryption controller controls the execution of an algorithm process through a finite state machine, receives configuration words from a scheduler, and configures an arithmetic unit to form a corresponding computation circuit function; the source data address generating and data distributing module reads the source data from the source data storage unit in sequence and sends the source data to the computing unit; the sub-key generation module is used for processing the initial key to obtain 48 sub-keys required in the triple encryption and decryption calculation round function; the triple encryption and decryption computation module is used for completing the 3DES encryption and decryption operation; the result data address generation and data distribution module receives the calculation results of the algorithm module and stores the calculation results into the result storage unit in sequence; the encryption and decryption S box can be reconstructed, and the mapping of the S box in the algorithm is completed through the ROM according to the requirement of the computing module; and the SRAM storage module stores source data to be calculated and result data after calculation.
Description
Technical Field
The invention relates to a reconfigurable computing implementation device and a reconfigurable computing method for a 3DES encryption and decryption algorithm, belonging to the technical field of hardware implementation of encryption and decryption algorithms in SoC digital circuit design.
Background
3DES is the expansion of DES encryption algorithm, through applying DES encryption 3 times to each data block, expand the effective key length from 56 bits to 168 bits, the very big extension of key space, the security of encrypting improves greatly, so is very wide in the field of the secure encryption.
Reconfigurable computing is a computer architecture that differs from conventional microprocessors in that it has both the flexibility of software and the high-speed computing speed of hardware. Reconfigurable computing allows a computing array to be constructed to perform one operation specifically, at a speed comparable to that of an asic, and to perform another job after one operation is completed.
In the prior art, a 3DES encryption and decryption circuit is usually realized in a mode of an application specific integrated circuit or an FPGA (field programmable gate array), the former circuit cannot be changed after production determination, and the latter circuit has certain flexibility but higher chip cost. The reconfigurable computing is used for realizing the 3DES encryption and decryption circuit, so that the integration level of the 3DES encryption and decryption algorithm and other algorithms can be greatly improved while high computing speed is ensured.
Disclosure of Invention
The purpose of the invention is as follows: one purpose is to provide a reconfigurable computing implementation device for a 3DES encryption and decryption algorithm, which realizes the compatibility of other encryption and decryption algorithms in a reconfigurable mode while ensuring high-efficiency operation, and improves the application range of an encryption and decryption chip. A further purpose is to provide a reconfigurable computing method based on the device.
The technical scheme is as follows: a3 DES encryption and decryption algorithm reconfigurable computing implementation device comprises the following modules:
3DES encryption and decryption controller used for controlling algorithm flow execution;
the source data address generation and data distribution module is used for reading the source data from the source data storage unit in sequence and sending the source data to the computing unit;
a sub-key generation module for processing the initial key and obtaining a sub-key;
the triple encryption and decryption computing module is used for carrying out encryption or decryption operation on the data;
the result data address generation and data distribution module is used for receiving the calculation result of the algorithm module and storing the calculation result into the result storage unit in sequence;
the system comprises a reconfigurable encryption and decryption S box and an SRAM storage module for storing source data to be calculated and result data after calculation.
In a further embodiment, the core of the 3DES encryption and decryption controller is a finite state machine FSM (finite State machine), controls the execution of algorithm flow, receives configuration words from a scheduler, and configures an arithmetic unit to form corresponding calculation circuit functions; starting and controlling reading source data or starting and controlling writing result data according to the algorithm execution stage parameters; the module is connected with a source data address generating and data distributing module, a sub-key generating module, a triple encryption and decryption calculating module and a result data address generating and data distributing module.
In a further embodiment, the source data address generating and data distributing module reads the source data from the source data storage unit in sequence, and the read data is sent to the computing unit; the module is connected with a 3DES encryption and decryption controller, an SRAM storage module, a sub-key generation module and a triple encryption and decryption calculation module.
In a further embodiment, the sub-key generation module processes the initial key to obtain 48 sub-keys required in the triple encryption and decryption calculation round function; the module is connected with a source data address generation and data distribution module and a triple encryption and decryption calculation module.
In a further embodiment, the triple encryption and decryption computation module performs encryption or decryption operation on data; the module is connected with a source data address generating and data distributing module, a triple encryption and decryption computing module, a reconfigurable encryption and decryption S box and a result data address generating and data distributing module.
In a further embodiment, the result data address generation and data distribution module receives the calculation results of the algorithm module and stores the calculation results in the result storage unit in sequence. The module is connected with the triple encryption and decryption calculation module and the SRAM storage module.
In a further embodiment, the reconfigurable encryption and decryption S box completes the mapping of the S box in the algorithm through the ROM according to the requirement of the computing module. The module is connected with the triple encryption and decryption calculation module.
A reconfigurable computing method of a 3DES encryption and decryption algorithm comprises the following steps:
step 2, a source data address generating module receives a source data reading signal from an encryption and decryption controller and generates a reading address and an SRAM storage module enabling signal; the SRAM storage module outputs 64-bit read data and a data effective signal every time and transmits the data and the data effective signal to the source data distribution module; the source data distribution module outputs 64-bit data and encryption and decryption calculation starting signals each time according to the input data effective signals;
and 3, processing the initial key by the sub-key generation module to obtain 48 sub-keys required in the triple encryption and decryption calculation round function.
In a further embodiment, when the sub-key generation module works, the 64-bit initial key removes 8 parity bits of 8, 16, 24, 32, 40, 48, 56 and 64 bits, the remaining 56 bits are subjected to PC-1 replacement, and the obtained new 56-bit data is divided into a left part and a right part according to the high and low 28 bits, and then 16 rounds of iteration are performed. In each iteration, data is circularly moved left according to the number of rounds, and then the 48-bit sub-secret key Ki of each round is obtained through PC-2 compression and replacement. Thus, 3 64-bit initial keys will result in 48 sub-keys;
in a further embodiment, the triple encryption and decryption computation module receives 64-bit source data and a computation start signal each time, in the encryption process, the 64-bit plaintext is initially replaced to obtain new 64-bit data which is disordered according to a certain rule, the new 64-bit data is divided into L0 and R0 according to the high and low 32 bits, and then 48 rounds of iteration are performed. And taking Ri-1 of the previous round as Li of the current round and Li-1 of the previous round as Ri of the current round in each round, and inputting the Ri-1 of the previous round as Ri of the current round into a round function F (Ki-1, Ri-1) for operation to obtain 32-bit output. And after 1-15 rounds of operation, the left and right sides are exchanged, and the left and right sides are not exchanged in the 16 th round. And splicing the obtained two 32-bit results into a 64-bit result, and performing inverse initial replacement to obtain a result of 3DES encryption. And the 48-round iteration is completed by repeatedly calling 1-16-round iteration calculation.
In a further embodiment, the reconfigurable encryption and decryption S box is responsible for completing part of the S function in a round function F (Ki-1, Ri-1) = P (S (E (Ri-1) & ltki)), the computation module outputs S box source data, the reconfigurable encryption and decryption S box generates a read address and a ROM enable signal according to the source data, and then outputs a ROM read result to the triple encryption and decryption computation module, the reconfigurable encryption and decryption S box has 8 parallel paths, and 48-bit address data is divided into 8 pieces of 6-bit address data.
Has the advantages that: the invention provides a reconfigurable computing implementation device and a reconfigurable computing method for a 3DES encryption and decryption algorithm, which have the characteristic of ultrahigh-speed computing of an application-specific integrated circuit, can realize compatibility with other algorithms, particularly a nonlinear S-box encryption and decryption algorithm by adopting a reconfigurable computing mode, and greatly improve the integration level and the application range of a chip.
Drawings
Fig. 1 is a schematic diagram of the overall architecture in a reconfigurable computing implementation of the 3DES encryption and decryption algorithm.
Fig. 2 is a flow chart of the 3DES algorithm implementation in the reconfigurable computing implementation of the 3DES encryption and decryption algorithm.
Fig. 3 is a flow chart of the 3DES algorithm computation in the reconfigurable computation implementation of the 3DES encryption and decryption algorithm, and the encryption process is taken as an example in the figure.
Detailed Description
In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art, that the present invention may be practiced without one or more of these specific details. In other instances, well-known features have not been described in order to avoid obscuring the invention.
Example one
The 3DES encryption and decryption algorithm reconfigurable computing implementation is shown in figure 1 and comprises a 3DES encryption and decryption controller, a source data address generation and data distribution module, a sub-key generation module, a triple encryption and decryption computing module, a result data address generation and data distribution module, a reconfigurable encryption and decryption S box and an SRAM storage module. The 3DES encryption and decryption controller is respectively connected with the source data address generation and data distribution module, the sub-key generation module, the triple encryption and decryption calculation module and the result data address generation and data distribution module to realize the overall control of the calculation process; the source data address generating and data distributing module is connected with the 3DES encryption and decryption controller, the SRAM storage module, the sub-key generating module and the triple encryption and decryption computing module to realize reading and distributing of source data; the sub-key generation module is connected with the source data address generation and data distribution module and the triple encryption and decryption calculation module, and calculates a sub-key required by the 3DES calculation process according to the initial key; the triple encryption and decryption computing module is connected with the source data address generating and data distributing module, the triple encryption and decryption computing module, the reconfigurable encryption and decryption S box and the result data address generating and data distributing module, receives the source data and the sub-secret key, and performs encryption and decryption computation on the source data; the result data address generating and data distributing module is connected with the triple encryption and decryption calculating module and the SRAM storage module, and the calculated data are stored in the SRAM storage module according to a certain address in sequence; the reconfigurable encryption and decryption S box is connected with the triple encryption and decryption computing module, reads data from the ROM according to the requirements of the computing module and returns the data; the SRAM storage module is connected with the source data address generation and data distribution module, and the result data address generation and data distribution module is responsible for storing source data and result data.
Example two
The reconfigurable calculation implementation of the 3DES encryption and decryption algorithm comprises the following steps:
(1) the 3DES encryption and decryption controller receives a calculation start signal, an encryption and decryption selection signal, a grouping mode configuration signal and a data total length parameter from the scheduler and outputs a source data reading signal. The packet mode configuration signal may select two packet modes of the source data: using an Electronic Code Book (ECB) and a Cipher Block Chaining (CBC);
(2) the source data address generating module receives a source data reading signal from the encryption and decryption controller and generates a reading address and an SRAM storage module enabling signal; the SRAM storage module outputs 64-bit read data and a data effective signal every time and transmits the data and the data effective signal to the source data distribution module; the source data distribution module outputs 64-bit data and encryption and decryption calculation starting signals each time according to the input data effective signals;
(3) and the sub-key generation module processes the initial key to obtain 48 sub-keys required in the triple encryption and decryption calculation round function. The 64-bit initial key firstly removes 8 parity bits of 8, 16, 24, 32, 40, 48, 56 and 64 bits, and carries out PC-1 replacement on the remaining 56 bits to obtain new 56-bit data which is divided into a left part and a right part according to the high and low 28 bits, and then the 16-round iteration is carried out. In each iteration, data is circularly moved left according to the number of rounds, and then the 48-bit sub-secret key Ki of each round is obtained through PC-2 compression and replacement. Thus, 3 64-bit initial keys will result in 48 sub-keys;
(3) the triple encryption and decryption calculation module receives 64-bit source data and a calculation start signal each time, a basic iterative algorithm process of the module is shown in fig. 3, taking an encryption process as an example, 64-bit plaintext is initially replaced to obtain new 64-bit data which is disordered according to a certain rule, the new 64-bit data is divided into L0 and R0 according to the high and low 32 bits, and then 48 rounds of iteration are performed. And taking Ri-1 of the previous round as Li of the current round and Li-1 of the previous round as Ri of the current round in each round, and inputting the Ri-1 of the previous round as Ri of the current round into a round function F (Ki-1, Ri-1) for operation to obtain 32-bit output. And after 1-15 rounds of operation, the left and right sides are exchanged, and the left and right sides are not exchanged in the 16 th round. And splicing the obtained two 32-bit results into a 64-bit result, and performing inverse initial replacement to obtain a result of 3DES encryption. And the 48-round iteration is completed by repeatedly calling 1-16-round iteration calculation.
As shown in fig. 3, this is a schematic diagram of a 3DES calculation flow, and its main structure is that 8-way parallel S-box partial calculation modules in a round function F (Ki-1, Ri-1) = P (S (E (Ri-1) = Ki)) output S-box source data, and a reconfigurable encryption/decryption S-box generates a read address and a ROM enable signal from the source data, and then outputs a ROM read result to a triple encryption/decryption calculation module.
As noted above, while the present invention has been shown and described with reference to certain preferred embodiments, it is not to be construed as limited thereto. Various changes in form and detail may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (9)
1. A3 DES encryption and decryption algorithm reconfigurable computing implementation device is characterized by comprising the following modules:
3DES encryption and decryption controller used for controlling algorithm flow execution;
the source data address generation and data distribution module is used for reading the source data from the source data storage unit in sequence and sending the source data to the computing unit;
a sub-key generation module for processing the initial key and obtaining a sub-key;
the triple encryption and decryption computing module is used for carrying out encryption or decryption operation on the data;
the result data address generation and data distribution module is used for receiving the calculation result of the algorithm module and storing the calculation result into the result storage unit in sequence;
the system comprises a reconfigurable encryption and decryption S box and an SRAM storage module for storing source data to be calculated and result data after calculation.
2. The device for realizing 3DES encryption and decryption algorithm reconfigurable computing according to claim 1, wherein the 3DES encryption and decryption controller is in communication connection with the source data address generation and data distribution module, the sub-key generation module, the triple encryption and decryption computing module, and the result data address generation and data distribution module, respectively.
3. The reconfigurable computing implementation device of the 3DES encryption and decryption algorithm according to claim 2, wherein the core of the 3DES encryption and decryption controller is a Finite State Machine (FSM), and the 3DES encryption and decryption controller is further used for controlling the execution of the algorithm flow, receiving configuration words from a scheduler, configuring an arithmetic unit, and forming corresponding computing circuit functions; and starting and controlling reading source data or starting and controlling writing result data according to the algorithm execution stage parameters.
4. The reconfigurable computing implementation device for the 3DES encryption and decryption algorithm according to claim 1, wherein the source data address generation and data distribution module is in communication connection with the 3DES encryption and decryption controller, the SRAM storage module, the sub-key generation module and the triple encryption and decryption computation module respectively; the source data address generating and data distributing module reads source data from the source data storage unit in sequence, and the read data are sent to the computing unit;
the sub-key generation module is in communication connection with the source data address generation and data distribution module and the triple encryption and decryption calculation module; and the sub-key generation module is used for processing the initial key to obtain the sub-key required in the triple encryption and decryption calculation round function.
5. The 3DES encryption and decryption algorithm reconfigurable computing implementation device of claim 1, wherein the triple encryption and decryption computation module is in communication connection with the source data address generation and data distribution module, the triple encryption and decryption computation module, the reconfigurable encryption and decryption S box, and the result data address generation and data distribution module, respectively;
the result data address generation and data distribution module is further used for receiving the calculation results of the algorithm module and storing the calculation results into a result storage unit in sequence; the result data address generating and data distributing module is in communication connection with the triple encryption and decryption computing module and the SRAM storage module;
the reconfigurable encryption and decryption S box finishes S box mapping in an algorithm through a ROM according to the requirements of the computing module; and the reconfigurable encryption and decryption S box is in communication connection with the triple encryption and decryption computing module according to the computing module.
6. A3 DES encryption and decryption algorithm reconfigurable computing method is characterized by comprising the following steps:
step 1, 3DES encryption and decryption controller receives calculation start signal, encryption and decryption selection signal and grouping mode configuration signal from scheduler and total length parameter of data, and outputs source data reading signal; the packet mode configuration signal selects two packet modes of the source data: using a codebook and cipher block chaining;
step 2, a source data address generating module receives a source data reading signal from an encryption and decryption controller and generates a reading address and an SRAM storage module enabling signal; the SRAM storage module outputs 64-bit read data and a data effective signal every time and transmits the data and the data effective signal to the source data distribution module; the source data distribution module outputs 64-bit data and encryption and decryption calculation starting signals each time according to the input data effective signals;
and 3, processing the initial key by the sub-key generation module to obtain 48 sub-keys required in the triple encryption and decryption calculation round function.
7. The 3DES encryption/decryption algorithm reconfigurable computing method according to claim 6, wherein the step 3 further comprises:
3-1, removing parity check bits from the initial key, then performing PC-1 replacement to obtain new data, dividing the new data into a left part and a right part according to the height, and performing iteration;
and 3-2, in each iteration, circularly moving the data to the left according to the turns, and then compressing and replacing by using the PC-2 to obtain the sub-secret key Ki.
8. The 3DES encryption and decryption algorithm reconfigurable computing method according to claim 7, wherein in an iteration process, a plaintext subjected to initial replacement is divided into Li and Ri according to high and low bits, the Li and Ri are input into a round function F (Ki-1, Ri-1) for iteration, and finally two obtained results are spliced to perform inverse initial replacement to obtain a 3DES encryption result.
9. The 3DES encryption and decryption algorithm reconfigurable computing method according to claim 8, wherein the reconfigurable encryption and decryption S box is responsible for completing a part of an S function in a round function F (Ki-1, Ri-1) = P (S (E (Ri-1) = Ki)), the computing module outputs S box source data, the reconfigurable encryption and decryption S box generates a read address and a ROM enable signal according to the source data, then the ROM read result is output to the triple encryption and decryption computing module, and the reconfigurable encryption and decryption S box has 8 paths in parallel.
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