CN112039745B

CN112039745B - CAN bus communication control system and communication system

Info

Publication number: CN112039745B
Application number: CN202010991480.8A
Authority: CN
Inventors: 刘锴; 宋宁; 崔明章; 杜金凤
Original assignee: Gowin Semiconductor Corp
Current assignee: Gowin Semiconductor Corp
Priority date: 2020-09-17
Filing date: 2020-09-17
Publication date: 2021-06-22
Anticipated expiration: 2040-09-17
Also published as: CN112039745A

Abstract

The invention provides a CAN bus communication control system and a communication system, wherein the communication system is based on an SoC framework composed of an MCU core and an FPGA core integrated in the same system on a chip, a CAN bus controller module, an MCU bus mapping module and a CAN bus interrupt signal mapping module are set based on logic resources in the FPGA core, CAN buses between the MCU and external CAN equipment outside the chip are integrated in the chip and CAN dynamically configure the number of the CAN buses, and priority classification control of the MCU core on each CAN bus controller module is realized, so that the expansibility and the usability of the MCU are improved, the design and application complexity of the MCU to mount the external CAN equipment is reduced, the rapid application of the CAN buses by users is facilitated, the dependence of the CAN bus priorities on CAN equipment nodes is reduced, and the controllability of the MCU on the CAN equipment node priorities is enhanced. The invention also provides a method for dynamically configuring the priority of each equipment node of the CAN bus.

Description

CAN bus communication control system and communication system

Technical Field

The invention relates to the technical field of CAN communication, in particular to a CAN bus communication control system, a communication system and a method for dynamically configuring the priority of each equipment node of a CAN bus.

Background

A Controller Area Network (CAN) is a serial communication Network that effectively supports distributed control or real-time control, is a multi-master bus, CAN be connected to external devices only through two lines, namely, a low-level CAN system bus CAN _ L and a high-level CAN system bus CAN _ H, and inherits an error detection and management module inside. The CAN is widely used in the fields of automotive computer control systems and embedded industrial control local area networks, and is generally used as an external device of an MCU (Micro-controller Unit) to communicate with an off-chip CAN bus in series in the field of MCU (Micro-controller Unit) single-chip microcomputers.

A System-on-a-Chip (SoC) having an MCU and an FPGA (Field Programmable Gate Array) simultaneously means that the MCU, a memory, an external device, and the like are connected to an FPGA core through the FPGA to form an SoC architecture of the MCU core and the FPGA core. Based on the programmable characteristic of the FPGA, the system-on-chip architecture has good expansibility.

In a traditional system on chip only having an MCU kernel, limited by cost, the MCU model capable of supporting more than two paths of CAN peripherals is limited or cost is too high, and the MCU CAN not well control the priority of each device node of a CAN bus.

Disclosure of Invention

The invention aims to provide a CAN bus communication control system, a communication system and a method for dynamically configuring the priority of each equipment node of a CAN bus, which CAN realize the classification control of the priority of each equipment node of the CAN bus by an MCU (microprogrammed control Unit), so that the functions and data of CAN equipment CAN be dynamically configured.

In order to solve the technical problem, the invention provides a CAN bus communication control system, which comprises an MCU core and an FPGA core integrated in the same system on a chip, wherein logic resources of the FPGA core are provided with a CAN bus interrupt signal mapping module, an MCU bus mapping module and a plurality of CAN bus controller modules; each CAN bus controller module is used for realizing a CAN bus standard protocol based on the logic resource of the FPGA kernel and connecting corresponding external CAN equipment positioned outside the system on chip, and the MCU bus mapping module is used for mapping one path of CAN system bus of the MCU kernel into a plurality of paths of CAN subsystem buses with dynamically configurable quantity.

Optionally, the CAN bus interrupt signal mapping module is connected to each CAN bus controller module, and the CAN bus interrupt signal mapping module is configured to map the interrupt signal of each CAN bus controller module into an interrupt vector table of the MCU core according to a specified priority, so as to implement control of the MCU core on the priority of each CAN bus controller module.

Optionally, the MCU bus mapping module extends to the FPGA core through an internal boundary of the FPGA core, and is connected to the corresponding CAN bus controller module, so as to realize interaction between the MCU core and the external CAN device.

Optionally, each path of the CAN subsystem bus is used for connecting a corresponding one of the CAN bus controller modules; each of the CAN bus controller modules includes:

the CAN bus function control module is used for realizing a CAN bus standard protocol based on the logic resource of the FPGA kernel;

the CAN bus external interface is connected with the CAN bus function control module and corresponding external CAN equipment so as to realize the communication interaction between the CAN bus function control module and a CAN bus of the external CAN equipment;

and the CAN bus internal interface is connected with the CAN bus function control module, the MCU bus mapping module and the CAN bus interrupt signal mapping module and is used for realizing the interaction of the CAN bus function control module, the MCU bus mapping module and the CAN bus interrupt signal mapping module.

Optionally, each CAN bus controller module further includes a general register set, where the general register set includes a control register, a status register, a read data register, and a write data register; and each register in the general register group is connected with a corresponding pin of the CAN bus function control module.

Optionally, the MCU bus mapping module is further configured to decode a peripheral address space of the MCU core, and map a register of the corresponding CAN bus controller module in the peripheral address space of the MCU core, so as to implement reading, writing, and controlling of the MCU core and the external CAN device.

Optionally, the CAN bus function control module includes: the device comprises a clock pin, a reset pin, a control pin, a state pin, a data reading pin and a data writing pin; the clock pin is externally connected with a clock signal of the MCU kernel, the reset pin is externally connected with a reset signal of the MCU kernel, the control pin is connected with the control register, the state pin is connected with the state register, the data reading pin is connected with the data reading register, and the data writing pin is connected with the data writing register.

Based on the same invention concept, the invention also provides a communication system which comprises the CAN bus communication control system and at least one external CAN device connected with the CAN bus communication control system, wherein each external CAN device is connected with a corresponding CAN bus controller module in the CAN bus communication control system.

Optionally, the external CAN device includes an external CAN transceiver, and the external CAN transceiver and the CAN bus communication control system are integrated in the same system on chip, or are disposed outside the system on chip where the CAN bus communication control system is located.

Based on the same inventive concept, an embodiment of the present invention further provides a method for dynamically configuring priorities of each device node of a CAN bus, including the following steps:

firstly, mapping one path of CAN system bus of an MCU into a plurality of paths of CAN subsystem buses with dynamically configurable quantity by utilizing the logic resource of an FPGA;

then, mounting the CAN bus controller of each external CAN device on the corresponding CAN subsystem bus;

and then, setting an interrupt signal of each CAN bus controller, and mapping the interrupt signal of each CAN bus controller into an interrupt vector table of the MCU according to a specified priority, so as to realize the priority classification control of the MCU on the node where each external CAN device is located.

Compared with the prior art, the technical scheme provided by the invention has at least one of the following beneficial effects:

1. the design is based on an SoC framework composed of an MCU core and an FPGA core integrated in the same system on chip, and a CAN bus between the MCU and an external CAN device outside the chip is realized based on logic resources in the FPGA core, so that the CAN subsystem bus realized in the FPGA CAN be used as the external device of the MCU, and the expansibility of the MCU is improved.

2. Based on the programmable characteristic of FPGA, the number of CAN bus controller modules realized by logic resources in an FPGA kernel and the number of CAN subsystem buses mapped by an MCU bus mapping module CAN be dynamically adjusted, so that the design has good expansibility, a user CAN dynamically configure the number of the CAN bus controller modules outside the MCU, and further dynamically configure the accessed external CAN equipment by the CAN bus controller modules, so that the purpose of dynamically configuring functions and data of the external CAN equipment is achieved, the expansibility and the usability of the MCU are improved, the design and application complexity of the MCU for hanging and loading the external CAN equipment is reduced, and the rapid application of the CAN bus by the user is facilitated.

3. Because the CAN bus interrupt signal mapping module maps the interrupt signals of the CAN bus controller module into the interrupt vector table of the MCU kernel according to the specified priority, the classification control of the MCU kernel on the priority of the CAN bus controller module CAN be realized, the dependency of the CAN bus priority on CAN equipment nodes is reduced, the controllability of the MCU on the CAN equipment node priority is enhanced, and the expansibility and the usability of the CAN equipment outside the MCU are improved.

Drawings

Fig. 1 is a block diagram of a CAN bus communication control system according to an embodiment of the present invention.

Fig. 2 is a schematic structural diagram of a CAN bus controller module according to an embodiment of the present invention.

Fig. 3 is a schematic diagram of a mapping process of the MCU bus mapping module according to an embodiment of the present invention.

Fig. 4 is a flowchart of a method for dynamically configuring the priority of each device node of the CAN bus according to an embodiment of the present invention.

Detailed Description

The technical solution proposed by the present invention will be further described in detail with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.

Referring to fig. 1, an embodiment of the present invention provides a CAN bus communication control system, which is implemented based on MCU and FPGA SoC architectures, and specifically includes an MCU core 13 and an FPGA core 10 integrated in a same SoC. The MCU core 13 has at least one CAN system bus, and each CAN system bus has two lines, a low level CAN system bus CAN _ L and a high level CAN system bus CAN _ H. The logic resources inside the FPGA core 10 mainly include Logic Control Block (LCB) resources, clock network resources, clock processing resources, Block random access memory (Block RAM), digital signal processing resources (DSP core), and interface resources. The logic control block resources include display look-up tables, adders, registers, multiplexers, etc. In this embodiment, the logic resource of the FPGA core 10 is provided with an MCU bus mapping module 11, a CAN bus interrupt signal mapping module 12, and n CAN bus controller modules 1 to n, where n is not less than 2 and is an integer.

Each CAN bus controller module 1-n is used for realizing a CAN bus standard protocol based on logic resources of the FPGA kernel 10 and is connected with corresponding external CAN equipment 21-2 n arranged outside the SoC. The CAN bus controller modules 1-n are correspondingly connected with external CAN devices 21-2 n one by one through CAN buses, and the external CAN devices 21-2 n are positioned outside the SoC and serve as equipment nodes of the CAN buses. In practical application, the number m of external CAN devices actually accessed to the system CAN be smaller than n, and at the moment, some CAN bus controller modules are not connected with the external CAN devices and are in an idle state.

Referring to fig. 2, each of the CAN bus controller modules 1 to n includes a CAN bus function control module 100, a CAN bus external interface (not shown), a CAN bus internal interface (not shown), and a general register set. The CAN bus function control module 100 is configured to implement a CAN bus standard protocol based on the logic resources of the FPGA core 10. And the CAN bus external interface is connected with the CAN bus function control module and one external CAN device in the external CAN devices 21-2 n so as to realize the communication interaction between the CAN bus function control module and the CAN bus of the external CAN device. The internal interface of the CAN bus is connected with the CAN bus function control module 100, the MCU bus mapping module 11 and the CAN bus interrupt signal mapping module 12, and is used for realizing interaction between the CAN bus function control module 100 and the MCU bus mapping module 11 and the CAN bus interrupt signal mapping module 12.

The general register set comprises a control register 101, a status register 102, a read data register 103 and a write data register 104, wherein the control register 101 is used for controlling and determining an operation mode and the characteristics of a currently executed task, and the status register 102 is used for storing two types of information: one type is various state information reflecting the execution result of the current instruction, and the other type is storage control information; the read data register 103 is used for temporarily storing read data; the write data register 104 is used to temporarily store data to be written.

The CAN bus function control module 100 comprises a clock pin, a reset pin, a control pin, a state pin, a data reading pin, a data writing pin and two pins CAN _ H, CAN _ L connected with an external interface of the CAN bus; the clock pin is externally connected with a clock signal of the MCU core 13, the reset pin is externally connected with a reset signal of the MCU core 13, the control pin is connected with the control register 101, the status pin is connected with the status register 102, the read data pin is connected with the read data register 103, and the write data pin is connected with the write data register 104.

Referring to fig. 1 and 2, the CAN bus interrupt signal mapping module 12 is mainly implemented by some combinational logic circuits in the FPGA core 10, and the combinational logic circuits are characterized in that the output at any time is only dependent on the input at that time, and is independent of the original state of the circuit. The input side of the CAN bus interrupt signal mapping module 12 is further connected with the control register 101 and the status register 102 of each CAN bus controller module 1-n through the CAN bus internal interface of each CAN bus controller module 1-n, and the output side of the CAN bus interrupt signal mapping module 12 is connected with the interrupt vector table of the MCU kernel 13. The CAN bus interrupt signal mapping module 12 is configured to map the interrupt signals of each CAN bus controller module 1 to n into an interrupt vector table of the MCU core 13 according to a specified priority, so as to control the priority of each CAN bus controller module 1 to n by the MCU core 13.

Referring to fig. 1 to fig. 3, the MCU bus mapping module 11 is connected to one CAN system bus of the MCU core 13, that is, the MCU bus mapping module 11 is connected to two lines, namely a low-level CAN system bus CAN _ L and a high-level CAN system bus CAN _ H of the MCU core 13. The MCU bus mapping module 11 CAN map one path of CAN system bus of the MCU kernel 13 into a plurality of paths of CAN subsystem buses which are the same as the number of the accessed external CAN devices according to the number of the external CAN devices connected with the CAN bus controller modules 1-n, namely, the MCU bus mapping module 11 CAN dynamically configure the number of the CAN subsystem buses according to the number of the external CAN devices which need to be accessed, each path of the CAN subsystem buses correspond to the external CAN devices which need to be accessed one by one, and each path of the CAN subsystem buses are used for being connected with corresponding one of the CAN bus controller modules 1-n.

Briefly, the MCU bus mapping module 11 CAN map a low-level CAN system bus CAN _ L of the MCU core 13 into a plurality of low-level CAN subsystem buses CAN _ L _ s, map a high-level CAN system bus CAN _ H of the MCU core 13 into a plurality of high-level CAN subsystem buses CAN _ H _ s, and form a low-level CAN subsystem bus and a low-level CAN subsystem bus CAN _ L _ s to form a CAN subsystem bus, where the CAN subsystem bus is connected to a corresponding CAN bus controller module, at this time, the external CAN devices 21 to 2n are equivalent to being connected in parallel to the MCU core 13, and the classification control of the priorities of the CAN bus controller modules 1 to n by the MCU core 13 CAN realize the priority control of the external CAN devices 21 to 2n by the MCU core 13, thereby avoiding that it is difficult to support two CAN devices and the MCU cannot control the CAN buses well when only two CAN systems buses exist in the prior art The priority of each device node.

Optionally, the MCU bus mapping module 11 extends into the FPGA core 10 through an internal boundary of the FPGA core 10 to connect with the corresponding CAN bus controller module, so as to realize interaction between the MCU core 13 and the external CAN devices 21-2 n.

Referring to fig. 3, the MCU bus mapping module 11 decodes the MCU core 13 peripheral address space corresponding to each CAN subsystem bus to map the corresponding register of the CAN bus controller module in the MCU core peripheral address space according to the decoding result, thereby implementing the read, write and control of the MCU core 13 and the external CAN devices 21-2 n.

As an example, the MCU bus mapping module 11 performs address segmentation on the peripheral address space of the MCU core 12 according to the address depth of the general register set in each of the CAN bus controller modules 1 to n and the number of the accessed external CAN devices 21 to 2n, forms a mapping relationship between the address segmentation and the register set address of the general register set, and further sends the mapping relationship to the MCU core 13 through the CAN subsystem bus and the CAN system bus, so that the MCU core 13 CAN generate a dedicated peripheral address signal of each accessed external CAN device in the MCU core 13 according to the mapping relationship. Further, the MCU bus mapping module 11 also maps the dedicated external device address signal of each external CAN device in the MCU core 13 to a register group address signal of the external CAN device, and further sends the register group address signal to the corresponding CAN bus controller module, which operates its general register group according to the register group address signal to further operate the connected external CAN devices by its general register group, so as to realize the read, write and control of the MCU core 13 and the external CAN devices 21-2 n.

Further, the MCU bus mapping module 11 is configured to receive an operation instruction sent by the MCU core 13 from a CAN system bus of the MCU core 13, and determine a type of the operation instruction; and the corresponding CAN bus controller module is used for carrying out corresponding operation on a corresponding register in the general register group according to the type of the operation instruction.

The following describes a specific flow when the MCU core 13 needs to operate a certain external CAN device 2i (1 ≦ i ≦ n) with reference to FIGS. 1 to 3, and at this time, the system-on-chip SoC where the MCU core 13 is located has access to a plurality of external CAN devices 21-2 n including the external CAN device 2i, and the MCU bus mapping module 11 has already according to the address depth of the general purpose register set in each of the CAN bus controller modules 1-n, and the number of the accessed external CAN devices 21-2 n, mapping one CAN system bus of the MCU kernel 13 into n CAN subsystem buses with dynamically configurable number, wherein each CAN subsystem bus is used for connecting one external CAN device, the ith CAN subsystem bus is connected with a CAN bus controller module i, and the CAN bus controller module i is connected with an external CAN device 2i, so that interaction between the system-on-chip SoC and the external CAN device 2i is realized. The specific process of the MCU core 13 that needs to operate the external CAN device 2i includes:

firstly, an MCU kernel 13 sends an operation instruction, an MCU bus mapping module 11 decodes the operation instruction to judge whether an ith CAN subsystem bus corresponding to an external CAN device 2i is selected or not, if not, a CAN bus controller module i connected with the external CAN device 2i is continuously in a standby state, if so, the CAN bus controller module i is enabled, the operation type is analyzed from the operation instruction, and whether the operation is a read operation or a write operation is judged;

if the external CAN device 2i is in a read operation, the CAN bus controller module i selects a register to be operated from a general register group according to a register group address signal of the external CAN device 2i provided by the MCU bus mapping module 11, wherein the register to be operated comprises a state register, a control register and a read data register, the selected register controls and reads data of the external CAN device 2i, the read data CAN be temporarily stored in the read data register, information such as control and determination operation modes, characteristics of a currently executed task and the like is temporarily stored in the control register, and various state information representing a current instruction execution result and control information which is generated by the CAN bus controller module i and is used for controlling the external CAN device 2i are temporarily stored in the state register; the CAN bus controller module i further sends the data in the read data register to the MCU core 13 through the MCU bus mapping module 11 and the CAN bus interrupt signal mapping module 12 to complete the read data operation.

If the external CAN device 2i is in write operation, the CAN bus controller module i selects a register to be operated from a general register group of the external CAN device 2i according to a register group address signal of the external CAN device 2i provided by the MCU bus mapping module 11, wherein the register to be operated comprises a control register and a write data register, the external CAN device 2i is controlled and written with data through the selected register, the data to be written into the external CAN device 2i CAN be temporarily stored in the write data register, and information such as the control and determination operation mode, the current task execution characteristic and the like is temporarily stored in the control register; the CAN bus controller module i further completes the write data operation by writing the data in its write data register into the external CAN device 2 i.

Based on the same inventive concept, please refer to fig. 1 to 3, this embodiment further provides a communication system, including the CAN bus communication control system of this embodiment, and at least one external CAN device 21 to 2n connected to the CAN bus communication control system (i.e., system on chip SoC), where each external CAN device is connected to a corresponding CAN bus controller module in the CAN bus communication control system.

Optionally, the external CAN device comprises an external CAN transceiver. In this embodiment, the external CAN transceiver is disposed outside a system on chip SoC where the CAN bus communication control system is located.

In other embodiments of the present invention, the external CAN transceiver may also be integrated with the CAN bus communication control system in the same system on chip SoC.

In summary, the CAN bus communication control system and the communication system of the present invention are based on the SoC architecture formed by the MCU core and the FPGA core integrated in the same system on chip, and realize the CAN bus between the MCU and the external CAN device outside the chip based on the logic resource in the FPGA core, so that the CAN bus realized in the FPGA CAN be used as the external device of the MCU, thereby improving the expansibility of the MCU. And based on the programmable characteristic of the FPGA, the number of the CAN bus controller modules realized by utilizing the logic resource in the FPGA kernel and the number of the CAN subsystem buses mapped by the MCU bus mapping module CAN be dynamically adjusted, so that the design has good expansibility, a user CAN dynamically configure the number of the CAN bus controller modules outside the MCU, and further dynamically configure the accessed external CAN equipment through the CAN bus controller modules, so that the purpose of dynamically configurable functions and data of the external CAN equipment is achieved, the expansibility and the usability of the MCU are improved, the design and application complexity of the MCU for hanging and loading the external CAN equipment is reduced, and the rapid application of the CAN bus by the user is facilitated. In addition, the CAN bus interrupt signal mapping module maps the interrupt signals of each CAN bus controller module into the interrupt vector table of the MCU kernel according to the specified priority, so that the classification control of the MCU kernel on the priority of each CAN bus controller module CAN be realized, the dependency of the CAN bus priority on CAN equipment nodes is reduced, the control performance of the MCU on the CAN equipment node priority is enhanced, and the expansibility and the usability of the CAN equipment outside the MCU are improved.

Based on the same inventive concept, referring to fig. 4, an embodiment of the present invention further provides a method for dynamically configuring priorities of each device node of a CAN bus, including the following steps:

s1, mapping one path of CAN system bus of an MCU into a plurality of paths of CAN subsystem buses with dynamically configurable quantity by using the logic resource of an FPGA;

s2, mounting the CAN bus controller of each external CAN device on the corresponding CAN subsystem bus;

and S3, setting an interrupt signal of each CAN bus controller, and mapping the interrupt signal of each CAN bus controller into an interrupt vector table of the MCU according to a specified priority, so as to realize the priority classification control of the MCU on the node where each external CAN device is located.

Preferably, referring to fig. 1 to 4, the method for dynamically configuring the priority of each device node of the CAN bus according to the embodiment is implemented by the CAN bus communication control system and the communication system of the present invention, that is, the MCU in step S1 is implemented by the MCU core 13 of the CAN bus communication control system of the present invention, the FPGA in step S1 is implemented by the FPGA core 10 of the CAN bus communication control system of the present invention, the overall process in step S1 is implemented by the function of the MCU bus mapping module 11 in the FPGA core 10, each CAN bus controller in step S2 is implemented by the corresponding CAN bus controller module in the FPGA core 10, the overall process in step S2 is implemented by the combined function of the connected CAN bus controller module, the MCU bus mapping module 11, and the MCU core 13, and the step S3 is implemented by the combined function of the connected CAN bus controller module, the connected CAN bus interrupt signal mapping module 12, and the connected MCU core 13.

In summary, the method for dynamically configuring the priority of each device node of the CAN bus according to the present invention CAN utilize the logic resource of the FPGA to implement the CAN bus between the MCU and the external CAN device, thereby implementing the dynamic adjustment of the number of the CAN system buses based on the programmable characteristic of the FPGA, so that the design has good extensibility, and the user CAN dynamically configure the CAN system buses outside the MCU and the number of the external CAN devices connected thereto, so as to achieve the purpose of dynamic configuration of the functions and data of the external CAN device, improve the extensibility and usability of the MCU, reduce the complexity of designing and applying the MCU to mount the external CAN device, and facilitate the user to quickly apply the CAN bus. Meanwhile, the interrupt signals of each CAN bus controller CAN be mapped into the interrupt vector table of the MCU according to the specified priority, so that the classification control of the MCU on the priority of each external CAN device CAN be realized, the dependency of the CAN bus priority on CAN device nodes is reduced, the controllability of the MCU on the priority of the CAN device nodes is enhanced, and the expansibility and the usability of the MCU external CAN device are improved.

It is to be understood that while the present invention has been described in conjunction with the preferred embodiments thereof, it is not intended to limit the invention to those embodiments. It will be apparent to those skilled in the art from this disclosure that many changes and modifications can be made, or equivalents modified, in the embodiments of the invention without departing from the scope of the invention. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention are still within the scope of the protection of the technical solution of the present invention, unless the contents of the technical solution of the present invention are departed.

It is to be further understood that the present invention is not limited to the particular methodology, materials, manufacturing techniques, uses, and applications described herein, as such may, of course, vary. It is also to be understood that the terminology used herein is for the purpose of describing particular embodiments only, and is not intended to limit the scope of the present invention. It must be noted that, as used herein and in the appended claims, the singular forms "a," "an," and "the" include plural referents unless the context clearly dictates otherwise. Thus, for example, reference to "a step" or "an apparatus" means a reference to one or more steps or apparatuses and may include sub-steps as well as sub-apparatuses. All conjunctions used should be understood in the broadest sense. Thus, the word "or" should be understood to have the definition of a logical "or" rather than the definition of a logical "exclusive or" unless the context clearly dictates otherwise. Structures described herein are to be understood as also referring to functional equivalents of such structures. Language that can be construed as approximate should be understood as such unless the context clearly dictates otherwise.

Claims

1. A CAN bus communication control system based on SoC architecture with FGPA and MCU is characterized by comprising an MCU core and an FPGA core which are integrated in the same system on chip, wherein logic resources of the FPGA core are provided with a CAN bus interrupt signal mapping module, an MCU bus mapping module and a plurality of CAN bus controller modules; each CAN bus controller module is used for realizing a CAN bus standard protocol based on the logic resource of the FPGA kernel and connecting external CAN equipment positioned outside the system on chip, and the MCU bus mapping module is used for mapping one path of CAN system bus of the MCU kernel into a plurality of paths of CAN subsystem buses with dynamically configurable quantity so as to realize the dynamic configuration of the functions and the quantity of the external CAN equipment connected with the system on chip; the CAN bus interrupt signal mapping module is connected with each CAN bus controller module, and is used for mapping the interrupt signals of each CAN bus controller module into an interrupt vector table of the MCU kernel according to the specified priority, so that the classification control of the MCU kernel on the priority of each CAN bus controller module is realized.

2. The CAN bus communication control system of claim 1, wherein the MCU system bus mapping module extends to the FPGA core through an internal boundary of the FPGA core and connects with the corresponding CAN bus controller module to enable interaction of the MCU core with the external CAN device.

3. The CAN bus communication control system of claim 1 wherein each of the CAN subsystem buses is adapted to connect to a respective one of the CAN bus controller modules; each of the CAN bus controller modules includes:

and the CAN bus internal interface is connected with the CAN bus function control module, the MCU bus mapping module and the CAN bus interrupt signal mapping module and is used for realizing interaction between the CAN bus function control module and the MCU bus mapping module as well as between the CAN bus interrupt signal mapping modules.

4. The CAN bus communication control system of claim 1, wherein each of the CAN bus controller modules comprises a general purpose register set comprising a control register, a status register, a read data register, and a write data register; and each register in the general register group is connected with a corresponding pin of the CAN bus function control module.

5. The CAN bus communication control system of claim 4, wherein the MCU bus mapping module is further configured to decode a peripheral address space of the MCU core, and map a register of the CAN bus controller module in the peripheral address space of the MCU core, so as to implement read, write, and control of the MCU core and the external CAN device.

6. The CAN-bus communication control system of claim 4, wherein the CAN-bus function control module comprises: the device comprises a clock pin, a reset pin, a control pin, a state pin, a data reading pin and a data writing pin; the clock pin is externally connected with a clock signal of the MCU kernel, the reset pin is externally connected with a reset signal of the MCU kernel, the control pin is connected with the control register, the state pin is connected with the state register, the data reading pin is connected with the data reading register, and the data writing pin is connected with the data writing register.

7. A communication system, comprising the CAN bus communication control system based on the SoC architecture with FGPA and MCU of any claim 1-6, and at least one external CAN device connected with the CAN bus communication control system, wherein each external CAN device is connected with a corresponding CAN bus controller module in the CAN bus communication control system.

8. The communication system of claim 7, wherein the external CAN device comprises an external CAN transceiver integrated in the same system-on-chip as the CAN bus communication control system, or wherein at least a portion of the external CAN transceiver is disposed off-chip from the system-on-chip on which the CAN bus communication control system is disposed.

9. A method for implementing dynamic configuration of priorities of device nodes of a CAN bus using the communication system of claim 7, comprising the steps of:

firstly, mapping one path of CAN system bus of MCU into a plurality of paths of CAN subsystem buses with dynamically configurable quantity by using logic resources of FPGA;