CN111755059B - Data reading circuit and memory cell - Google Patents
Data reading circuit and memory cell Download PDFInfo
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- CN111755059B CN111755059B CN201910240416.3A CN201910240416A CN111755059B CN 111755059 B CN111755059 B CN 111755059B CN 201910240416 A CN201910240416 A CN 201910240416A CN 111755059 B CN111755059 B CN 111755059B
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/26—Sensing or reading circuits; Data output circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/08—Address circuits; Decoders; Word-line control circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/30—Power supply circuits
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Abstract
A data reading circuit and a storage unit are provided, the data reading circuit comprises a reference voltage generating unit, a pull-down signal generating unit, a sensitive amplifying unit, a column decoding unit and a reference voltage adjusting unit corresponding to the column decoding unit one by one, wherein the reference voltage generating unit is used for receiving an inverted chip enable signal, generating a chip enable signal and generating a reference voltage, outputting the reference voltage to the sensitive amplifying unit and the reference voltage adjusting unit, and outputting the chip enable signal to the pull-down signal generating unit; the pull-down signal generating unit is used for generating a pull-down signal according to the chip enabling signal and outputting the pull-down signal to the sensitive amplifying unit and the reference voltage adjusting unit; the reference voltage adjusting unit is used for adjusting the reference voltage to a stable state after the reference voltage is reduced along with the pull-down signal. The scheme can ensure the stability of the reference voltage.
Description
Technical Field
The invention belongs to the technical field of integrated circuits, and particularly relates to a data reading circuit and a storage unit.
Background
Memory cells are an important component of integrated circuits. A minimum ROM device for storing information, such as a Read Only Memory (ROM), has a ROM cell that stores one bit of information, representing one of two states, namely "0" and "1". When the ROM cell is not being read, its bit line is at a low level "0". After reading is started, the bit line is charged to an intermediate level, then the bit line is subjected to pull-down discharge through the ROM unit, and the information stored in the ROM unit is judged based on the voltage value of the bit line after pull-down.
In reading information in a memory cell, a stable reference voltage is required to ensure proper margin for reading "0" and margin for reading "1". However, the amount of stored information is increasing, and the corresponding reference voltage loads are also different. Therefore, when the amount of stored information is different, it is necessary to ensure stability of the reference voltage and improve the read margin.
Disclosure of Invention
The embodiment of the invention solves the problem of how to ensure the stability of the reference voltage.
To solve the above technical problem, an embodiment of the present invention provides a data reading circuit, including: the device comprises a reference voltage generating unit, a pull-down signal generating unit, a sensitive amplifying unit, a row decoding unit and reference voltage adjusting units corresponding to the row decoding units one to one, wherein: the reference voltage generating unit is connected with the pull-down signal generating unit, the reference voltage adjusting unit and the sensitive amplifying unit, and is used for receiving an inverted chip enable signal, generating a chip enable signal and generating a reference voltage, outputting the reference voltage to the sensitive amplifying unit and the reference voltage adjusting unit, and outputting the chip enable signal to the pull-down signal generating unit; the pull-down signal generating unit is connected with the reference voltage generating unit, the reference voltage adjusting unit and the sensitive amplifying unit, and is used for generating a pull-down signal according to the chip enable signal and outputting the pull-down signal to the sensitive amplifying unit and the reference voltage adjusting unit; the column decoding unit is connected with the sensitive amplifying unit and used for decoding the received bit line signals and outputting the decoded bit line signals to the sensitive amplifying unit; the sensitive amplifying unit is connected with the reference voltage generating unit, the pull-down signal generating unit, the column decoding unit and the reference voltage adjusting unit, and is used for amplifying and outputting the decoded bit line signal according to the reference voltage; the reference voltage adjusting unit is connected with the reference voltage generating unit, the pull-down signal generating unit and the sensitive amplifying unit, and is used for adjusting the reference voltage to a stable state after the reference voltage is reduced along with the pull-down signal.
Optionally, the reference voltage adjusting unit includes at least one NMOS transistor.
Optionally, the reference voltage adjusting unit includes a first NMOS transistor; the grid electrode of the first NMOS tube is connected with the pull-down signal, the source electrode of the first NMOS tube is connected with the reference voltage and the sensitive amplifying unit, and the drain electrode of the first NMOS tube is grounded.
Optionally, the first NMOS transistor substrate is grounded.
Optionally, the reference voltage generating unit includes: first phase inverter, second NMOS pipe, first PMOS pipe, second PMOS pipe, third PMOS pipe, fourth PMOS pipe, fifth PMOS pipe, on-off switch and disconnection switch, wherein: the input end of the first phase inverter is connected with the inverted chip enable signal, and the output end of the first phase inverter outputs the chip enable signal; the grid electrode of the second NMOS tube is connected with the output end of the first phase inverter, the source electrode of the second NMOS tube is connected with the grid electrode and the drain electrode of the fourth PMOS tube, the grid electrode and the drain electrode of the first PMOS tube, the grid electrode and the drain electrode of the fifth PMOS tube and the output end of the reference voltage generating unit, and the drain electrode of the second NMOS tube is connected with a reference bit line signal input outside the reference voltage generating unit; the source electrode of the first PMOS tube is connected with the drain electrode of the second PMOS tube; the grid electrode of the second PMOS tube is connected with the disconnecting switch, and the source electrode of the second PMOS tube is connected with the source electrode of the fourth PMOS tube, the substrate of the second PMOS tube, the substrate of the first PMOS tube, the source electrode of the third PMOS tube, the substrate of the fifth PMOS tube and the power supply; and the grid electrode of the third PMOS tube is connected with the closed switch, and the drain electrode of the third PMOS tube is connected with the source electrode of the fifth PMOS tube.
Optionally, the substrate of the fourth PMOS transistor is connected to the power supply, and the substrate of the second NMOS transistor is grounded.
Optionally, the pull-down signal generating unit includes: delay timer, NAND gate and second inverter, wherein: the input end of the delayer is connected with the chip enable signal, and the output end of the delayer is connected with the first input pin of the NAND gate; the second input pin of the NAND gate is connected with the chip enable signal, and the output end of the NAND gate is connected with the second inverter; the second inverter outputs the output end of the pull-down signal generating unit.
In order to solve the above technical problem, an embodiment of the present invention further discloses a memory cell, including any one of the above data reading circuits.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following beneficial effects:
the data reading circuit comprises a column decoding unit and reference voltage adjusting units which correspond to the column decoding unit one by one, wherein the reference voltage adjusting units are used for adjusting the reference voltage to a stable state after the reference voltage drops along with a pull-down signal, namely, the reference voltage is quickly adjusted along with the pull-down signal, and the stability of the reference voltage is ensured. Meanwhile, the reference voltage adjusting units correspond to the column decoding units one to one, and the whole data reading circuit is partially adjusted according to the number of the column decoders, so that the aim of stabilizing the reference voltage can be fulfilled under the conditions of different bit numbers and different reference voltage loads.
Drawings
Fig. 1 is a partial circuit configuration diagram of a data reading circuit in an embodiment of the present invention;
FIG. 2 is another partial circuit structure diagram of a data reading circuit according to an embodiment of the present invention;
FIG. 3 is a comparison between a reference voltage of a data reading circuit in the prior art and a reference voltage of a data reading circuit in an embodiment of the present invention.
Detailed Description
In the prior art, when reading information in a memory cell, a stable reference voltage is required to ensure proper margin for reading "0" and margin for reading "1". However, the amount of stored information is increasing, and the corresponding reference voltage loads are also different. Therefore, when the amount of stored information is different, it is necessary to ensure stability of the reference voltage and improve the read margin.
In the embodiment of the invention, the data reading circuit comprises a column decoding unit and reference voltage adjusting units which are in one-to-one correspondence with the column decoding unit, wherein the reference voltage adjusting units are used for adjusting the reference voltage to a stable state after the reference voltage is reduced along with a pull-down signal, namely, the reference voltage is quickly adjusted along with the pull-down signal, so that the stability of the reference voltage is ensured. Meanwhile, the reference voltage adjusting units correspond to the column decoding units one to one, and the whole data reading circuit is partially adjusted according to the number of the column decoders, so that the aim of stabilizing the reference voltage can be fulfilled under the conditions of different bit numbers and different reference voltage loads.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
The embodiment of the invention provides a data reading circuit. Referring to fig. 1 and 2, fig. 1 is a partial circuit configuration diagram of a data reading circuit in an embodiment of the present invention. Fig. 2 is another partial circuit configuration diagram of a data reading circuit in the embodiment of the present invention.
The data reading circuit provided by the embodiment of the invention can be applied to the memory cell of an integrated circuit.
The data reading circuit in the embodiment of the present invention includes a reference voltage generating unit 101, a pull-down signal generating unit 102, a sensitive amplifying unit 103, a column decoding unit 104, and reference voltage adjusting units 105 corresponding to the column decoding units 104 one to one.
The reference voltage generating unit 101 is connected to the pull-down signal generating unit 102, the reference voltage adjusting unit 105, and the sensitive amplifying unit 103, and may be configured to receive an inverted chip enable signal CEN, generate a chip enable signal CE, and generate a reference voltage Vref, output the reference voltage Vref to the sensitive amplifying unit 103 and the reference voltage adjusting unit 105, and output the chip enable signal CE to the pull-down signal generating unit 102.
In a specific implementation, the reference voltage generating unit 101 may include: the inverter comprises a first phase inverter inv1, a second NMOS transistor N2, a first PMOS transistor P1, a second PMOS transistor P2, a third PMOS transistor P3, a fourth PMOS transistor P4, a fifth PMOS transistor P5, a closing switch S <1> and an opening switch S <0 >;
the input end of the first phase inverter inv1 is connected with the inverted chip enable signal CEN, the output end of the first phase inverter inv1 outputs the chip enable signal CE, and the other two pins are respectively connected with a power supply VDD and a ground VSS. The first inverter inv1 may be configured to convert the input inverted chip enable signal CEN into a chip enable signal CE and output the chip enable signal CE.
The second NMOS transistor N2 has a gate connected to the output terminal (chip enable signal CE) of the first inverter inv1, a source connected to the gate and drain of the fourth PMOS transistor P4, the gate and drain of the first PMOS transistor P1, the gate and drain of the fifth PMOS transistor P5, and the output terminal of the reference voltage generating unit 101, and a drain connected to a reference bit line signal BLref input from the outside of the reference voltage generating unit 101;
the grid electrode of the first PMOS pipe P1 is connected with the drain electrode of the second PMOS pipe P2;
the grid electrode of the second PMOS tube P2 is connected with the disconnecting switch S <0>, the source electrode is connected with the source electrode of the fourth PMOS tube P4, the substrate of the second PMOS tube P2, the substrate of the first PMOS tube P1, the source electrode of the third PMOS tube P3, the substrate of the third PMOS tube P3, the substrate of the fifth PMOS tube P5 and the power supply VDD;
the grid electrode of the third PMOS pipe P3 is connected with the closing switch S <1>, and the drain electrode is connected with the source electrode of the fifth PMOS pipe P5.
In a specific implementation, the substrate of the fourth PMOS transistor P4 is connected to the power supply VDD, and the substrate of the second NMOS transistor N2 is connected to the ground VSS.
The pull-down signal generating unit 102 is connected to the reference voltage generating unit 101, the reference voltage adjusting unit 105, and the sensitive amplifying unit 103, and configured to generate a pull-down signal PD according to the chip enable signal CE, and output the pull-down signal PD to the sensitive amplifying unit 103 and the reference voltage adjusting unit 105.
In a specific implementation, the pull-down signal generating unit 102 may include: a delay, a nand gate nand, and a second inverter inv 2.
The input end of the delayer delay is connected with the chip enable signal CE, the output end of the delayer delay is connected with the first input pin of the NAND gate nand, and the input chip enable signal CE can be delayed and then output to the NAND gate nand. It is understood that the time length of the delay may be adjusted by setting different delay devices according to different requirements of different users.
A second input pin of the nand gate nand is connected with the chip enable signal CE, an output pin of the nand gate nand is connected with the second inverter inv2, and the other two pins of the nand gate nand are respectively connected with a power supply VDD and a ground VSS;
the output end of the second inverter inv2 is connected to the output end of the pull-down signal generating unit 102, and the other two pins are respectively connected to the power supply VDD and the ground VSS, so as to process the signal output by the nand gate nand and output the pull-down signal PD.
The column decoding unit 104 is connected to the sensitive amplifying unit 103, and is configured to decode the received bit line signal BL in the binary code state into a bit line signal DB in a corresponding original state, and output the decoded bit line signal DB to the sensitive amplifying unit 103.
The sensitive amplifying unit 103 is connected to the reference voltage generating unit 101, the pull-down signal generating unit 102, the column decoding unit 104, and the reference voltage adjusting unit 105, and is configured to amplify and output the decoded bit line signal DB according to a reference voltage Vref.
In practical applications, the bit line signal DB is difficult to be read accurately because its variation is very small. Therefore, the sense amplifier 103 is required to amplify and sample the bit line signal DB in the data read circuit, and then output the variation of the bit line signal DB to the output terminal DOUT.
The reference voltage adjusting unit 105 is connected to the reference voltage generating unit 101, the pull-down signal generating unit 102, and the sensitive amplifying unit 103, and is configured to adjust the reference voltage Vref to a stable state after the reference voltage Vref decreases with the pull-down signal PD.
In a specific implementation, the reference voltage adjusting unit 105 may include at least one NMOS transistor.
In practical application, in the data reading circuit, the pull-down signal PD can be generated by the falling edge of the inverted chip enable signal CEN, and then the reference voltage Vref is pulled down by the pull-down signal PD in an accelerated manner. Specifically, a pull-down NMOS transistor may be adopted, so that the start time of the falling edge of the inverting chip enable signal CEN is effectively reduced, and therefore the time for pulling down the reference voltage Vref is also reduced, so that the reference voltage Vref quickly reaches the state of being stable again after being pulled down.
Further, since the reference voltage adjusting units 105 correspond to the column decoding units 104 one to one, the pull-down NMOS transistor in each reference voltage adjusting unit 105 can be respectively adjusted in size. The pull-down task of the reference voltage Vref in the whole data reading circuit is dispersed to the circuit corresponding to each ROM, so that the reference voltage Vref cannot be pulled down excessively, the condition of reading the '0' allowance is influenced, and the reading allowance in the data reading process is ensured.
In an embodiment of the present invention, the reference voltage adjusting unit 105 includes a first NMOS transistor N1; the gate of the first NMOS transistor N1 is connected to the pull-down signal PD, the source is connected to the reference voltage Vref and the sensitive amplification unit 103, and the drain is connected to the ground VSS.
In a specific implementation, the substrate of the first NMOS transistor N1 is grounded to VSS.
The data reading circuit comprises a column decoding unit and reference voltage adjusting units which correspond to the column decoding unit one by one, wherein the reference voltage adjusting units are used for adjusting the reference voltage to a stable state after the reference voltage drops along with a pull-down signal, namely, the reference voltage is quickly adjusted along with the pull-down signal, and the stability of the reference voltage is ensured. Meanwhile, the reference voltage adjusting units correspond to the column decoding units one to one, and the whole data reading circuit is partially adjusted according to the number of the column decoders, so that the aim of stabilizing the reference voltage can be fulfilled under the conditions of different bit numbers and different reference voltage loads.
Referring to fig. 3, a schematic diagram of a comparison between reference voltages of a data reading circuit in the prior art and a data reading circuit in an embodiment of the present invention is shown, where the abscissa unit is nanoseconds (ns) and the ordinate unit is volts (V).
Referring to fig. 3, as the falling edge of the inverted chip enable signal, a short pulse pull-down signal is generated, so that the reference voltage is pulled down rapidly. Compared with the reference voltage in the data reading circuit in the prior art, the reference voltage of the data reading circuit provided by the scheme is remarkably and rapidly adjusted to a stable state after being pulled down no matter under the condition of the maximum bit number (max bits) or the minimum bit number (min bits), so that the reference voltage is not excessively pulled down to further influence the reading margin, and the aim of stabilizing the reference voltage is effectively achieved under the conditions of different bit numbers and different reference voltage loads.
An embodiment of the present invention further provides a memory cell including the data reading circuit provided in any one of the above embodiments of the present invention.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (7)
1. A data reading circuit, comprising: the device comprises a reference voltage generating unit, a pull-down signal generating unit, a sensitive amplifying unit, a row decoding unit and reference voltage adjusting units corresponding to the row decoding units one to one, wherein:
the reference voltage generating unit is connected with the pull-down signal generating unit, the reference voltage adjusting unit and the sensitive amplifying unit, and is used for receiving an inverted chip enable signal, generating a chip enable signal and generating a reference voltage, outputting the reference voltage to the sensitive amplifying unit and the reference voltage adjusting unit, and outputting the chip enable signal to the pull-down signal generating unit;
the pull-down signal generating unit is connected with the reference voltage generating unit, the reference voltage adjusting unit and the sensitive amplifying unit, and is used for generating a pull-down signal according to the chip enable signal and outputting the pull-down signal to the sensitive amplifying unit and the reference voltage adjusting unit;
the column decoding unit is connected with the sensitive amplifying unit and used for decoding the received bit line signals and outputting the decoded bit line signals to the sensitive amplifying unit;
the sensitive amplifying unit is connected with the reference voltage generating unit, the pull-down signal generating unit, the column decoding unit and the reference voltage adjusting unit, and is used for amplifying and outputting the decoded bit line signal according to the reference voltage;
the reference voltage adjusting unit is connected with the reference voltage generating unit, the pull-down signal generating unit and the sensitive amplifying unit and is used for adjusting the reference voltage to a stable state after the reference voltage is reduced along with the pull-down signal;
the pull-down signal generating unit includes: delay timer, NAND gate and second inverter, wherein:
the input end of the delayer is connected with the chip enable signal, and the output end of the delayer is connected with the first input pin of the NAND gate;
the second input pin of the NAND gate is connected with the chip enable signal, and the output end of the NAND gate is connected with the second inverter;
the second inverter outputs the output end of the pull-down signal generating unit.
2. The data reading circuit of claim 1, wherein the reference voltage adjustment unit comprises at least one NMOS transistor.
3. The data reading circuit of claim 1, wherein the reference voltage adjustment unit comprises a first NMOS transistor; the grid electrode of the first NMOS tube is connected with the pull-down signal, the source electrode of the first NMOS tube is connected with the reference voltage and the sensitive amplifying unit, and the drain electrode of the first NMOS tube is grounded.
4. The data reading circuit of claim 3, wherein the first NMOS transistor substrate is grounded.
5. The data reading circuit according to claim 1, wherein the reference voltage generating unit includes: first phase inverter, second NMOS pipe, first PMOS pipe, second PMOS pipe, third PMOS pipe, fourth PMOS pipe, fifth PMOS pipe, on-off switch and disconnection switch, wherein: the input end of the first phase inverter is connected with the inverted chip enable signal, and the output end of the first phase inverter outputs the chip enable signal;
the grid electrode of the second NMOS tube is connected with the output end of the first phase inverter, the source electrode of the second NMOS tube is connected with the grid electrode and the drain electrode of the fourth PMOS tube, the grid electrode and the drain electrode of the first PMOS tube, the grid electrode and the drain electrode of the fifth PMOS tube and the output end of the reference voltage generating unit, and the drain electrode of the second NMOS tube is connected with a reference bit line signal input outside the reference voltage generating unit;
the source electrode of the first PMOS tube is connected with the drain electrode of the second PMOS tube;
the grid electrode of the second PMOS tube is connected with the disconnecting switch, and the source electrode of the second PMOS tube is connected with the source electrode of the fourth PMOS tube, the substrate of the second PMOS tube, the substrate of the first PMOS tube, the source electrode of the third PMOS tube, the substrate of the fifth PMOS tube and the power supply;
and the grid electrode of the third PMOS tube is connected with the closed switch, and the drain electrode of the third PMOS tube is connected with the source electrode of the fifth PMOS tube.
6. The data reading circuit of claim 5, wherein the substrate of the fourth PMOS transistor is connected to a power supply, and the substrate of the second NMOS transistor is connected to ground.
7. A memory cell comprising the data reading circuit of any one of claims 1 to 6.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201910240416.3A CN111755059B (en) | 2019-03-28 | 2019-03-28 | Data reading circuit and memory cell |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201910240416.3A CN111755059B (en) | 2019-03-28 | 2019-03-28 | Data reading circuit and memory cell |
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| CN111755059A CN111755059A (en) | 2020-10-09 |
| CN111755059B true CN111755059B (en) | 2022-04-15 |
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| US5187429A (en) * | 1992-02-20 | 1993-02-16 | Northern Telecom Limited | Reference voltage generator for dynamic random access memory |
| US6005379A (en) * | 1997-10-16 | 1999-12-21 | Altera Corporation | Power compensating voltage reference |
| US6160392A (en) * | 1998-06-05 | 2000-12-12 | Lg Semicon Co., Ltd. | Start-up circuit for voltage reference generator |
| KR20070075578A (en) * | 2006-01-13 | 2007-07-24 | 주식회사 하이닉스반도체 | Reference voltage selection circuit and reference voltage generation circuit using the same |
| CN102194520A (en) * | 2010-03-11 | 2011-09-21 | 索尼公司 | Control voltage generation circuit and nonvolatile storage device having the same |
| CN103295626A (en) * | 2012-02-28 | 2013-09-11 | 北京时代全芯科技有限公司 | High-precision data reading circuit for phase change memory |
-
2019
- 2019-03-28 CN CN201910240416.3A patent/CN111755059B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5187429A (en) * | 1992-02-20 | 1993-02-16 | Northern Telecom Limited | Reference voltage generator for dynamic random access memory |
| US6005379A (en) * | 1997-10-16 | 1999-12-21 | Altera Corporation | Power compensating voltage reference |
| US6160392A (en) * | 1998-06-05 | 2000-12-12 | Lg Semicon Co., Ltd. | Start-up circuit for voltage reference generator |
| KR20070075578A (en) * | 2006-01-13 | 2007-07-24 | 주식회사 하이닉스반도체 | Reference voltage selection circuit and reference voltage generation circuit using the same |
| CN102194520A (en) * | 2010-03-11 | 2011-09-21 | 索尼公司 | Control voltage generation circuit and nonvolatile storage device having the same |
| CN103295626A (en) * | 2012-02-28 | 2013-09-11 | 北京时代全芯科技有限公司 | High-precision data reading circuit for phase change memory |
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