CN111614651A

CN111614651A - Low-delay TDS protocol analysis method based on FPGA

Info

Publication number: CN111614651A
Application number: CN202010407637.8A
Authority: CN
Inventors: 秦轶轩; 陈进; 华征良
Original assignee: Nanjing Accelecom Information Technology Co ltd
Current assignee: Nanjing Accelecom Information Technology Co ltd
Priority date: 2020-05-14
Filing date: 2020-05-14
Publication date: 2020-09-01

Abstract

A method for analyzing a low-delay TDS protocol based on an FPGA comprises the following steps: the method comprises the following steps: the client module directly writes the transaction data that the customer sent into storage module, and after the inside TDS service end module of FPGA received the TDS request of transaction end module through integrated high-speed tcp card, according to the source TDS agreement generation TDS message flow type only label of waiting to resolve, step two: generating a statement type label corresponding to the generated TDS message stream type unique label, and checking statement validity; step three: generating grammar and lexical rules matched with the character data stream of the statement type label; step four: and converting the grammar and lexical rules into an output data stream of the corresponding table configuration type, and outputting the output data stream to the access management module for data interaction of the transaction end module to the storage module. The invention does not need a CPU to participate in scheduling and high concurrent execution, not only has high integration level, low cost and clear structure, but also saves the process of operating a database by intermediate software, thereby greatly reducing the delay of data interaction.

Description

Low-delay TDS protocol analysis method based on FPGA

Technical Field

The invention relates to the technical field of TDS (time domain synchronous analysis) analysis applied to financial transaction systems of securities, stocks and the like, in particular to a low-delay TDS protocol analysis method based on an FPGA (field programmable gate array).

Background

With the development of the global market, more and more users participate in financial transactions such as stock and stock, the data volume is larger and larger, and the requirement on the access time of the transaction data is higher and higher. Data in current financial transactions of securities, stocks and the like are interacted in a database mode, transaction data of a client side are transmitted to a database through a network, a trading exchange side scans the database to obtain and update the database, the database is basically accessed in a software-based mode, software is required to be executed through a CPU of a host no matter through a shared memory or an optical network, no matter how much flow is, and great delay exists in view of the limitations of a software system and a CPU architecture; and when the amount of data to be processed increases sharply, the delay of data access also increases sharply at this time because the number of messages processed by the CPU is limited. The access of the database firstly needs to rapidly analyze the TDS protocol, while the analysis operation of the software is a time-consuming process, and the time of each execution is consumed not only in the analysis logic but also in the CPU scheduling and the protocol data access; the various time consumptions above all directly or indirectly affect the interaction of transaction data.

Disclosure of Invention

1. The technical problem to be solved is as follows:

the existing financial transaction data interaction of securities, stocks and the like has large delay.

2. The technical scheme is as follows:

in order to solve the above problems, a method for analyzing a low-delay TDS protocol based on an FPGA includes the following steps: the method comprises the following steps: the client module directly writes the transaction data that the customer sent into storage module, and after the inside TDS service end module of FPGA received the TDS request of transaction end module through integrated high-speed tcp card, according to the source TDS agreement generation TDS message flow type only label of waiting to resolve, step two: generating a statement type label corresponding to the TDS message stream type unique label generated in the step one according to the TDS message stream type unique label generated in the step one, and checking statement validity; step three: generating grammar and lexical rules matched with the character data stream according to the statement type labels in the step two; step four: and converting the grammar and lexical rules into an output data stream of the corresponding table configuration type according to the third step, and outputting the output data stream to the access management module for data interaction of the transaction terminal module to the storage module.

In step one, the unique label of the message flow is SQL message flow or RPC message flow.

In the first step, in the TDS server module, the TDS to be analyzed is processed inside the FPGA according to a data stream single clock cycle.

If the message type does not exist, the current message stream is discarded.

In step two, the statement type tag is a TOKEN statement or a PARAMETER statement.

In the second step, the statement type label analysis is processed in parallel according to a single clock cycle.

In step two, if the result of checking the validity is illegal, the current message flow is discarded.

The grammar and lexical rules include length.

The grammar and lexical rules are generated in the FPGA.

The data streams are transferred in parallel to a plurality of memory modules in a single clock cycle.

3. Has the advantages that:

the invention provides a low-delay TDS protocol analysis method based on FPGA aiming at the defect of large delay in the prior art, compared with the prior serial execution based on a software analysis mode, more required components, high cost, large power consumption and high delay, and compared with the prior software database which basically has microsecond-level delay, the invention combines the technical characteristics of high concurrency and low delay of FPGA chip processing, fully exerts the advantages of parallel processing, analyzes all steps and is executed in parallel, not only has low delay and can reach nanosecond-level delay of an FPGA system clock, but also has fewer required components, low cost and small power consumption.

Drawings

Fig. 1 is a TDS access overall framework schematic.

Fig. 2 is a TDS protocol parsing flow.

Detailed Description

The present invention will be described in detail below with reference to the accompanying drawings.

As shown in fig. 1 and fig. 2, the present invention provides a method for analyzing a low delay TDS protocol based on an FPGA, which includes the following steps: the method comprises the following steps: the client module directly writes transaction Data sent by a client into the storage module, and after receiving a TDS (distributed Data Stream) request of the transaction end module through an integrated high-speed tcp card, the FPGA (field programmable Gate Array) server module generates a TDS message Stream type unique label according to a source TDS protocol to be analyzed.

The client module directly writes the transaction data sent by the client into the storage module without intermediate conversion steps.

The message stream unique label is SQL (Structured Query Language) message stream or RPC (Remote Procedure Call) message stream.

the tcp received data is directly sent to the TDS server module, single clock cycle processing is carried out in the FPGA according to data flow, SQL and RPC messages can be analyzed in parallel, the whole packet of data is not required to be stored in an array or a queue in software operation, then the data is fetched according to a time slice fetching instruction and decoded, then analysis is carried out, and the current message flow is discarded under the condition that the message type is not stored. The delay is reduced to some extent.

Step two: generating a TDS message stream type unique label according to the source TDS protocol to be analyzed according to the first step to generate a corresponding statement type label, and checking statement validity.

The statement type tag is a TOKEN statement or a PARAMETER statement. Statement analyses such as TOKEN statements or PARAMETER statements are processed in parallel according to a single clock cycle, and the whole packet of data is not required to be stored into an array or a queue firstly in software operation and then processed in series according to time slices. The delay is reduced, and the TOKEN statement or PARAMETER statement is checked for validity, and if the TOKEN statement or PARAMETER statement is not legal, the current message flow is discarded, so that the delay is further reduced.

Step three: and generating grammar and lexical rules matched with the character data stream according to the statement type label in the step two.

The grammar and lexical rules include length. The grammar and the lexical rules are generated in parallel in the FPGA, do not need to be executed through a host CPU, are not limited by the limitations of a software system and a CPU architecture, and reduce the delay.

Step four: and converting the grammar and lexical rules into an output data stream of the corresponding table configuration type according to the third step, and outputting the output data stream to the access management module for data interaction of the transaction terminal module to the storage module.

Be equipped with the access management module between TDS server module and storage module, access management module be used for managing the memory block to interact with TSD server module.

The detailed description of the invention shows that compared with the existing serial execution based on a software analysis mode, the invention has the advantages of more required components, high cost, large power consumption and high delay, and compared with the existing software database which basically has microsecond-level delay, the invention combines the technical characteristics of high concurrency and low delay of FPGA chip processing, fully exerts the advantages of parallel processing, analyzes each step and executes in parallel, has low delay, can achieve nanosecond-level delay of an FPGA system clock, and has less required components, low cost and low power consumption.

Although the present invention has been described with reference to the preferred embodiments, it should be understood that various changes and modifications can be made therein by those skilled in the art without departing from the spirit and scope of the invention as defined by the appended claims.

Claims

1. A method for analyzing a low-delay TDS protocol based on an FPGA comprises the following steps: the method comprises the following steps: the client module directly writes the transaction data that the customer sent into storage module, and after the inside TDS service end module of FPGA received the TDS request of transaction end module through integrated high-speed tcp card, according to the source TDS agreement generation TDS message flow type only label of waiting to resolve, step two: generating a corresponding statement type label according to the TDS message stream type unique label generated in the step one, and checking the legality of the statement type label; step three: generating grammar and lexical rules matched with the character data stream according to the statement type labels in the step two; step four: and converting the grammar and lexical rules into an output data stream of the corresponding table configuration type according to the third step, and outputting the output data stream to the access management module for data interaction of the transaction terminal module to the storage module.

2. The method of claim 1, wherein: in step one, the unique label of the message flow is SQL message flow or RPC message flow.

3. The method of claim 1, wherein: in the first step, in the TDS server module, the TDS to be analyzed is processed inside the FPGA according to a data stream single clock cycle.

4. A method as claimed in claim 1, 2 or 3, characterized by: if the message type does not exist, the current message stream is discarded.

5. The method of claim 1, wherein: in step two, the statement type tag is a TOKEN statement or a PARAMETER statement.

6. The method of claim 1, wherein; in the second step, the statement type label analysis is processed in parallel according to a single clock cycle.

7. The method of claim 1, 5 or 6, wherein; in step two, if the result of checking the validity is illegal, the current message flow is discarded.

8. The method of claim 1, wherein: the grammar and lexical rules include length.

9. The method of claim 1 or 8, wherein: the grammar and lexical rules are generated in the FPGA.

10. The method of claim 1, wherein: the data streams are transferred in parallel to a plurality of memory modules in a single clock cycle.