CN111489777B

CN111489777B - Magnetic memory structure, array, read-write control method and preparation method

Info

Publication number: CN111489777B
Application number: CN202010295621.2A
Authority: CN
Inventors: 余君; 庄晓辉; 余自强
Original assignee: Shanghai Industrial Utechnology Research Institute
Current assignee: Shanghai Industrial Utechnology Research Institute
Priority date: 2020-04-15
Filing date: 2020-04-15
Publication date: 2023-11-10
Anticipated expiration: 2040-04-15
Also published as: CN111489777A

Abstract

The invention provides a magnetic memory structure, an array, a read-write control method and a preparation method, wherein each magnetic memory unit of the array comprises a first transistor, a second transistor, a first bit unit and a second bit unit, wherein: the bit units of two adjacent magnetic memory units share a spin orbit torque layer and a shared bit line, the first bit unit and the second bit unit are respectively connected with the bit line and the shared bit line through the spin orbit torque layer, and the shared bit line is connected with the spin orbit torque layer between the two adjacent magnetic memories; the first and second bit units are connected with 2 adjacent word lines through the first and second transistors; and the read-write control unit is used for reading or setting the states of the first bit unit and the second bit unit. According to the invention, two adjacent magnetic memory units share one spin orbit torque layer and one shared bit line, independent operation of each magnetic bit unit is realized by regulating and controlling the substrate voltage of the transistor, and meanwhile, the occupied area of each bit unit and the whole memory array is effectively reduced.

Description

Magnetic memory structure, array, read-write control method and preparation method

Technical Field

The present invention relates to the field of semiconductor memory design and fabrication, and more particularly, to a magnetic memory structure, an array, a read-write control method, and a manufacturing method thereof.

Background

As feature sizes of semiconductor processes continue to decrease, the static power consumption caused by transistor leakage current is increasingly accounting for the total power consumption of integrated circuits, resulting in serious power consumption waste. The emerging nonvolatile memory is capable of storing data in a power-off state, and is one of effective schemes for solving the static power consumption problem of an integrated circuit. Among them, the magnetic random access memory (Magnetoresistive Random Access Memory, MRAM) is expected to be a next-generation general-purpose nonvolatile memory because of its advantages of high speed, low power consumption, unlimited erasing and writing. MRAM memory devices are spin-electron devices based on a magnetic tunnel junction (Magnetic Tunnel Junction, MTJ for short), the basic structure of which is two ferromagnetic thin films with an oxide layer sandwiched between them, i.e., a tunneling layer (tunneling barrier), such as magnesium oxide (MgO). The spin magnetic moment of a magnetic film is fixed, called a fixed layer (pinned layer); the other layer can be turned over to store information, called free layer or storage layer. Changing the magnetic moment direction of the ferromagnetic material of the free layer at one end of the magnetic tunneling junction can change the tunneling probability of electrons in different spin directions, so that the overall resistance of the magnetic tunneling junction is changed, and the storage of data is realized. The first generation of MRAM needs to implement data writing through a magnetic field, and the required writing current is high, which is a serious problem that as the size of a device is reduced, the current value required by the magnetic field writing technology cannot be reduced, and the development of a high-capacity low-power consumption MRAM is restricted.

To overcome the above-described drawbacks of the MARM, spin transfer torque (Spin Transfer Torque, STT) technology is proposed and applied to the data write operation of MRAM. The STT-MRAM utilizes the self spin torque of electrons to change the magnetic moment direction of a free layer in a magnetic tunneling junction, and has the advantages of simple structure, high integration density, low power consumption and the like. However, this approach presents a bottleneck that is difficult to overcome: in the initial stage of writing, the weak spin transfer torque is insufficient to change the spin direction of the free layer due to the damping characteristic of the magnetic thin film material, so that initial delay is caused, the writing speed is limited, and the cache requirement is difficult to meet. In addition, a large amount of current needs to directly pass through the magnetic tunneling junction during writing operation, so that the tunneling layer is aged, and the service life of the device is influenced.

As the next generation product of STT-RARM, the reading and writing paths of SOT-MRAM (Spin-Orbit Torque Magnetoresistive Random Access Memory) are separated, and current does not flow through a magnetic tunneling junction but passes through one SOT layer during writing operation, so that Spin Hall Effect (SHE) is utilized to realize the turnover of the free layer. SOT-MRAM optimizes the performance of STT-MRAM, has quicker writing speed, longer breakdown resistance, better device reliability and non-volatility, and is one of the most potential technologies for replacing the traditional L1/L2 cache. However, since the SOT-MRAM introduces one SOT layer, each memory cell can only store one bit, and 3 ports are needed for performing read-write operation, so that the cell area is larger and the storage density is lower.

Disclosure of Invention

In view of the above-mentioned drawbacks of the prior art, an object of the present invention is to provide a magnetic memory structure, an array, a read-write control method and a manufacturing method for solving the problem of low storage density of the SOT-MRAM in the prior art.

To achieve the above and other related objects, the present invention provides a magnetic memory array comprising: a plurality of magnetic memory cells, each of the plurality of magnetic memory cells: comprises a first transistor, a second transistor, a first bit unit and a second bit unit, wherein: the bit units of two adjacent magnetic memory units share a spin orbit torque layer and a shared bit line, the first bit unit and the second bit unit are respectively connected with the bit line and the shared bit line through the spin orbit torque layer, and the shared bit line is connected with the spin orbit torque layer between the two adjacent magnetic memories; the first bit unit and the second bit unit are connected with adjacent first word lines and second word lines through the first transistor and the second transistor; and a read-write control unit connected with the at least one magnetic memory unit through a source line, a bit line and a shared bit line, and controlling the working states of the first transistor and the second transistor in the at least one magnetic memory unit so as to read or set the states of the first bit unit or the second bit unit.

Optionally, the material of the spin-orbit torque layer includes one of a heavy metal including one of Pt, ta, and W and a topological insulator including one of a BiSe alloy and a BiSb alloy.

Optionally, the first bit cell includes a first magnetic tunnel junction and a first upper electrode, the second bit cell includes a second magnetic tunnel junction and a second upper electrode, the upper electrode of the first bit cell and the upper electrode of the second bit cell are connected to a drain of the second transistor, the drain of the first transistor is electrically connected to a spin orbit torque layer located between the first bit cell and the second bit cell, a gate of the first transistor is connected to the first word line, a gate of the second transistor is connected to the second word line, and sources of the first transistor and the second transistor are connected to the source line.

Optionally, the read-write control unit controls the operating states of the first transistor and the second transistor in at least one magnetic memory cell, and controls the current flowing through the spin orbit torque layer to set the state of the first bit cell or the second bit cell.

Further, the read-write control unit controls the voltages of the adjacent 2 word lines connected with at least one magnetic memory unit, and controls the voltages applied to the memory unit and/or the first transistor substrate of the adjacent memory unit so as to control the working states of the first transistor and the second transistor of the magnetic memory unit; the state of the first bit cell or the second bit cell is set by controlling a current flowing through the spin-orbit torque layer by gating one of the bit line and the common bit line and controlling a voltage thereof, a voltage of a source line.

Optionally, the read-write control unit controls the working states of the first transistor and the second transistor in at least one memory cell to read the states of the first bit cell and the second bit cell.

Optionally, the read-write control unit controls the working states of the first transistor and the second transistor of the memory unit by controlling the voltages of the adjacent 2 word lines connected with at least one memory unit and controlling the voltages applied to the memory unit and/or the first transistor substrate of the adjacent memory unit; the state of the first bit cell or the second bit cell is read by gating one of the bit line and the common bit line and controlling its voltage, and the voltage of the source line.

Optionally, the first transistor and the second transistor are common source.

Optionally, the magnetic tunnel junction includes a free magnetic layer, a fixed magnetic layer, and an insulating tunnel layer disposed between the free magnetic layer and the fixed magnetic layer, wherein the fixed magnetic layer has a fixed first magnetic pole, the free magnetic layer has a variable second magnetic pole, the magnetic tunnel junction is in a low resistance state if the first magnetic pole is in the same direction as the second magnetic pole, and the magnetic tunnel junction is in a high resistance state if the first magnetic pole is opposite to the second magnetic pole.

Optionally, the free magnetic layer is located on the spin-orbit torque layer, the direction of the first magnetic pole is vertical, the material of the free magnetic layer comprises one of CoFeB alloy, feB alloy and CoFe alloy, and the thickness of the free magnetic layer is between 0.8nm and 1.3 nm.

Optionally, the free magnetic layer includes a synthetic antiferromagnetic structure including first and second layers of ferromagnetic material that are in antiparallel, and a nonmagnetic material coupling spacer layer between the first and second layers of ferromagnetic material.

Optionally, the second magnetic pole direction of the fixed magnetic layer is a vertical direction, and the material of the fixed magnetic layer includes one of CoFeB alloy, feB alloy and CoFe alloy, and the thickness of the material is between 0.8nm and 1.3 nm.

Optionally, the material of the insulating tunnel layer includes MgO, and the thickness thereof is between 0.8nm and 1.3 nm.

Optionally, the magnetic tunnel junction further comprises a spacer layer on the fixed magnetic layer and a synthetic antiferromagnetic structure on the spacer layer.

Optionally, the material of the spacer layer includes one of Ta, an alloy containing Co, and an alloy containing Fe; the thickness of the spacer layer is between 0.2nm and 1.2 nm.

Optionally, the synthetic antiferromagnetic structure includes first and second layers of ferromagnetic material that are aligned in opposite directions, and a non-magnetic material coupling spacer layer between the first and second layers of ferromagnetic material.

Optionally, the ferromagnetic material layer includes a plurality of ferromagnetic composite layers, the thickness of the ferromagnetic composite layers is between 0.2nm and 0.6nm, the material of the ferromagnetic composite layers includes one of a Co/Pt composite layer, a Co/Pd composite layer and a Co/Ni composite layer, and the material of the nonmagnetic material coupling interlayer includes Ru, and the thickness of the nonmagnetic material coupling interlayer is between 0.4nm and 0.9 nm.

Optionally, the diameter of the magnetic tunnel junction is between 10nm and 90 nm.

Optionally, the first magnetic tunnel junction, the second magnetic tunnel junction are stacked over the first transistor and the second transistor.

Optionally, integrated into at least one of: music players, video players, entertainment units, navigation devices, communications devices, personal digital assistants, fixed location data units, mobile phones, and portable computers.

The invention also provides a read-write control method of the magnetic memory array, which comprises the following steps: controlling the operating states of the first transistor, the second transistor of at least one magnetic memory cell, controlling the current flowing through the spin-orbit torque layer to set the state of the first bit cell or the second bit cell; or controlling the working states of a first transistor and a second transistor of at least one magnetic memory cell, and reading the states of the first bit cell and the second bit cell.

Optionally, controlling the voltage of the adjacent 2 word lines to which at least one magnetic memory cell is connected, controlling the voltage applied to the memory cell and/or the first transistor substrate of its adjacent memory cell to control the operating states of the first transistor, the second transistor of the magnetic memory cell; the state of the first bit cell or the second bit cell is set by controlling a current flowing through the spin-orbit torque layer by gating one of the bit line and the common bit line and controlling a voltage thereof, a voltage of a source line.

Optionally, controlling the operating states of the first transistor and the second transistor of the memory cell by controlling the voltages of the adjacent 2 word lines to which at least one of the memory cells is connected and controlling the voltages applied to the memory cell and/or the first transistor substrate of its adjacent memory cell; the state of the first bit cell or the second bit cell is read by gating one of the bit line and the common bit line and controlling its voltage, and the voltage of the source line.

Alternatively, the states of the first magnetic tunnel junction, the second magnetic tunnel junction are set to a high resistance state or a low resistance state by controlling the current flowing through the spin orbit torque layer.

Optionally, the method comprises: the output current flowing through the first bit unit and the second bit unit is read to judge whether the resistance state is a high resistance state or a low resistance state.

The present invention also provides a magnetic memory structure comprising: a substrate; a plurality of magnetic memory cells formed on a substrate, the magnetic memory cells comprising: a first transistor, a second transistor, each comprising a gate line structure and source and drain regions in the substrate between the gate line structures; a first bit cell comprising a spin-orbit torque layer, a first magnetic tunnel junction on the spin-orbit torque layer, and a first upper electrode; the second bit cell includes the spin-orbit torque layer, a second magnetic tunnel junction located on the spin-orbit torque layer, and a second upper electrode; a plurality of metal wiring layers, wherein each metal wiring layer comprises a metal wire, a via and an interlayer dielectric; the drain region of the first transistor is electrically connected with the spin orbit torque layer shared by the first bit unit and the second bit unit through the contact hole, the metal wire and the via hole, and the drain region of the second transistor is connected with the first upper electrode and the second upper electrode through the contact hole, the metal layer wire and the via hole; wherein the first bit cell, the second bit cell of the magnetic memory cell and the first bit cell and the second bit cell of the adjacent magnetic memory cell share a spin-orbit torque layer and a metal wiring layer; the first transistor of the magnetic memory unit is connected with the grid electrode of the first transistor of the adjacent magnetic memory unit by the same word line; the first transistor of the magnetic memory unit and the first transistor of the adjacent magnetic memory are respectively provided with independent substrate well regions and are respectively led out by different metal wires.

Optionally, the first transistor and the second transistor share a source region, the common source region is located between gates of the first transistor and the second transistor, and the common source region is led out through a source line.

Alternatively, the gate of the first transistor is constructed as a word line for writing through a metal wire in the metal wiring layer connected to the contact hole, and the gate of the second transistor is constructed as a word line for reading through a metal wire in the metal wiring layer connected to the contact hole, respectively.

Optionally, a metal wiring layer below the spin orbit torque layer is used as a bit line layer, two ends of the spin orbit torque layer are respectively connected with two bit lines through vias in the metal wiring layer, one bit line is used as a bit line of a first bit unit of the magnetic memory, and the other bit line is used as a bit line of a second bit unit of the magnetic memory adjacent to the magnetic memory; the middle part of the common spin orbit torque layer of two adjacent magnetic memories is connected with the common bit line through a common via hole in the metal wiring layer.

The invention also provides a preparation method of the magnetic memory structure, which comprises the following steps: providing a substrate, and forming an isolation region on the substrate; forming a first transistor and a second transistor in an active region at one side of the isolation region, wherein the first transistor and the second transistor respectively comprise a grid line structure and a source region and a drain region which are positioned in the substrate and between the grid line structures; forming a plurality of metal wiring layers, wherein each metal wiring layer comprises a metal wire, a via hole and an interlayer medium; forming a first bit unit between two adjacent upper and lower metal wiring layers, wherein the first bit unit and a second bit unit comprise the spin orbit torque layer, a first magnetic tunnel junction and a first upper electrode, which are positioned on the spin orbit torque layer, and the second bit unit comprises the spin orbit torque layer, a second magnetic tunnel junction and a second upper electrode, which are positioned on the spin orbit torque layer; the drain region of the first transistor is electrically connected with the spin orbit torque layer shared by the first bit unit and the second bit unit through the contact hole, the metal wire and the via hole, and the drain region of the second transistor is connected with the first upper electrode and the second upper electrode through the contact hole, the metal layer wire and the via hole; wherein the first bit cell, the second bit cell of the magnetic memory cell and the first bit cell and the second bit cell of the adjacent magnetic memory cell share a spin-orbit torque layer and a metal wiring layer; the first transistor of the magnetic memory unit is connected with the grid electrode of the first transistor of the adjacent magnetic memory unit by the same word line; the first transistor of the magnetic memory unit and the first transistor of the adjacent magnetic memory are respectively provided with independent substrate well regions and are respectively led out by different metal wires.

As described above, the magnetic memory structure, array, read-write control method and preparation method of the invention have the following beneficial effects:

The invention provides a novel magnetic memory array (SOT-MRAM), wherein a magnetic memory structure in the array comprises two adjacent magnetic memory units, 4 switching transistors (transistors) are used for driving 4 magnetic bit units (MTJs) to form a 4T-4R structure, 4 memory bits (bits) can be stored in the magnetic memory structure, each magnetic bit unit can be independently operated, more memory units can be effectively arranged on a unit area, and the integration density can be greatly increased.

The two adjacent magnetic memory units share one spin orbit torque layer and one shared bit line, and independent operation of each magnetic bit unit is realized by regulating and controlling the substrate voltage of the corresponding transistor, and meanwhile, the occupied area of each bit unit is effectively reduced.

The invention can also reduce the effective area of the CMOS transistor required by driving the magnetic memory structure by arranging 2 switching transistors to share the source region, and can reduce the number of source lines (source lines), further reduce the area of the whole magnetic memory array (SOT-MRAM) and greatly increase the memory density.

Compared with the traditional SOT-MRAM device structure, the invention can reduce the memory cell area by about 33 percent, almost can reach the integration density (1T-1R) of a 2-end device STT-MRAM, and solves the problem of large SOT-MRAM cell area.

Drawings

FIG. 1 is a schematic diagram of a magnetic memory array according to an embodiment of the invention.

FIG. 2 is a schematic diagram of a device structure of a magnetic memory cell in a magnetic memory array according to an embodiment of the invention.

Fig. 3 to 4 are schematic circuit diagrams showing a writing method and a reading method of a magnetic memory array according to an embodiment of the invention.

FIG. 5 is a schematic diagram of a magnetic tunnel junction of a magnetic memory array according to an embodiment of the invention.

FIG. 6 is a schematic diagram of another magnetic tunnel junction of a magnetic memory array according to an embodiment of the invention.

FIG. 7 shows a schematic diagram of a magnetic tunnel junction of a magnetic memory array in accordance with an embodiment of the invention during writing.

FIG. 8 is a schematic diagram of a magnetic tunnel junction of a magnetic memory array according to an embodiment of the invention during read-out.

Description of element reference numerals

10. Bulk silicon substrate

20. 20' first transistor

30. 30' second transistor

101. Drain electrode of second transistor

102. Drain electrode of first transistor

103. Source electrode

104. The grid electrode of the first transistor

105. Grid electrode of second transistor

106. Shallow trench isolation structure

107. First well region

107' second well region

401. First layer metal wire

402. Second layer metal wire

403. Third layer metal wire

404. Fourth layer metal wire

405. Via hole

406. Interlayer medium

407. Insulating dielectric layer

408. Contact hole

50. 50' magnetic memory cell

50a, 50a' first bit cell

50b, 50b' second bit cell

501. Spin orbit torque layer

502. First magnetic tunnel junction

503. Second magnetic tunnel junction

504. Upper electrode of first bit cell

505. Upper electrode of second bit cell

WL1 first word line

RL1 second word line

BL1-1 first bit line

BL1-2 (BL 2-1) shares bit lines

BL2-2 second bit line

SL1 first source line

SL2 second source line

Detailed Description

Other advantages and effects of the present invention will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present invention with reference to specific examples. The invention may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present invention.

As described in detail in the embodiments of the present application, the cross-sectional view of the device structure is not partially enlarged to a general scale for convenience of explanation, and the schematic drawings are only examples, which should not limit the scope of the present application. In addition, the three-dimensional dimensions of length, width and depth should be included in actual fabrication.

For ease of description, spatially relative terms such as "under", "below", "beneath", "above", "upper" and the like may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that these spatially relative terms are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the figures. Furthermore, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers or one or more intervening layers may also be present.

In the context of the present application, a structure described as a first feature being "on" a second feature may include embodiments where the first and second features are formed in direct contact, as well as embodiments where additional features are formed between the first and second features, such that the first and second features may not be in direct contact.

It should be noted that, the illustrations provided in the present embodiment merely illustrate the basic concept of the present invention by way of illustration, and only the components related to the present invention are shown in the drawings rather than the number, shape and size of the components in actual implementation, and the form, number and proportion of each component in actual implementation may be arbitrarily changed, and the layout of the components may be more complex.

SOT-MRAM (Spin-Orbit Torque Magnetoresistive Random Access Memory) optimizes the performance of STT-MRAM, has a faster writing speed, a longer breakdown resistance, better device reliability, and a plurality of advantages such as non-volatility, however, SOT-MRAM also has some technical problems to be solved, because the read-write paths of SOT-MRAM are separated, one magnetic memory cell needs 2 switching transistors to control the read operation and the write operation respectively, namely, SOT-MARM usually adopts a 2T-1R cell structure, and STT-MRAM is a 1T-1R cell structure, which causes SOT-MRAM to be larger than the device cell area of STT-MRAM. How to reduce the area of the memory cell and increase the memory density without affecting the performance of the device is a difficult problem in the current SOT-MRAM research and development.

In order to solve the above-mentioned problems, as shown in fig. 1 and 2, fig. 1 is a schematic circuit diagram of a magnetic memory array according to the present embodiment, and fig. 2 is a schematic device diagram of a magnetic memory cell according to the present embodiment, where the present embodiment provides a magnetic memory array, including: a plurality of magnetic memory cells 50, 50', each magnetic memory cell 50, 50' of the plurality of magnetic memory cells 50, 50': the memory cell comprises a first transistor 20, a second transistor 30, a first bit cell 50a and a second bit cell 50b, wherein the bit cells of two adjacent magnetic memory cells 50, 50 'share a spin-orbit torque layer 501 and a shared bit line BL1-2 (BL 2-1), the first bit cell MTJ-1 and the second bit cell MTJ-2 are respectively connected with bit lines BL1-1, BL2-2 and the shared bit line BL1-2 (BL 2-1) through the spin-orbit torque layer 501, the shared bit line BL1-2 (BL 2-1) is connected with the spin-orbit torque layer between the two adjacent magnetic memory cells 50, 50', and the first bit cell 50a and the second bit cell 50b are connected with the adjacent first word line WL1 and the second word line RL1 through the first transistor 20 and the second transistor 30; and a read-write control unit connected to the at least one magnetic memory cell 50, 50 'through a source line SL1 (source line), bit lines BL1-1, BL2-2 and a common bit line BL1-2 (BL 2-1), and controlling the operation states of the first transistor 20 and the second transistor 30 in the at least one magnetic memory cell 50, 50' to read or set the state of the first bit cell 50a or the second bit cell 50 b.

In one embodiment, the read/write control unit controls the operation state of the first transistor 20, the second transistor 30 in at least one of the magnetic memory cells 50, 50', and controls the current flowing through the spin-orbit torque layer 501 to set the state of the first bit cell 50a or the second bit cell 50 b. Specifically, the read-write control unit controls the voltages of the adjacent 2 word lines to which at least one magnetic memory cell 50, 50 'is connected, controls the voltages applied to the memory cell 50 and/or the first transistor 20 substrate of its adjacent memory cell 50' to control the operation states of the first transistor 20, the second transistor 30 of the magnetic memory cell; the current flowing through the spin-orbit torque layer 501 is controlled to set the state of the first bit cell 50a or the second bit cell 50b by gating one of the bit lines BL1-1, BL2-2 and the common bit line BL1-2 (BL 2-1) and controlling the voltage thereof, the voltage of the source lines SL1, SL 2. For example, in a state where the first bit cell 50a or the second bit cell 50b is set, a current is applied to flow from the first bit line BL1-1, the common bit line BL1-2 (BL 2-1), between the first bit cell 50a or the second bit cell 50b of the spin-orbit torque layer 501, the electron spin-orbit of the spin-orbit torque layer 501 interacts with the current, electrons having opposite spin directions flow to both sides of the spin-orbit torque layer 501, respectively, spin current is formed, electrons at the interface of the free magnetic layer and the spin-orbit torque layer 501 are subjected to the coupling of the spin current, the spin direction of the electrons is turned from the vertical direction to the horizontal direction, and then 180 ° flip of the spin direction of the electrons in the free magnetic layer is achieved by a spin-transfer torque method or external magnetic field assistance, as shown in fig. 7.

In one embodiment, as shown in fig. 2, the first bit cell 50a includes a first magnetic tunnel junction 502 and a first upper electrode 504, the second bit cell 50b includes a second magnetic tunnel junction 503 and a second upper electrode 505, the first transistor 20 and the second transistor 30 may be NMOS transistors or PMOS transistors prepared based on a bulk silicon substrate 10, or include NMOS transistors or PMOS transistors prepared based on FD-SOI (fully depleted silicon on insulator), etc., as shown in fig. 2, the first transistor 20 includes a drain 102, a gate 104, and a source 103, the second transistor 30 includes a source 103, a gate 105, and a drain 101, the source 102 and the drain 103 are all formed in a well region opposite to the source 102 and the drain 103, for example, the source 102 and the drain 103 are formed in a p-type well region for NMOS transistors, and the source 102 and the drain 103 are formed in an n-type well region for PMOS transistors. The first transistor 20 and the second transistor 30 are designed in a common source, and share one source 103, so as to reduce the effective area of the switching transistor required for driving the magnetic memory structure, and reduce the wiring of the array source line (source line), thereby further reducing the area of the whole magnetic memory array (SOT-MRAM), and greatly increasing the storage density. The upper electrode of the first bit cell 50a and the upper electrode of the second bit cell 50b are connected to the drain of the second transistor 30, the drain of the first transistor 20 is electrically connected to the spin-orbit torque layer 501 between the first bit cell 50a and the second bit cell 50b, for example, the drain of the first transistor 20 may be connected to the spin-orbit torque layer 501 to save wiring and facilitate the subsequent read/write operation of the first bit cell 50a and the second bit cell 50b by current, the gate of the first transistor 20 is connected to one of the first word lines WL1 of the two adjacent word lines, the gate of the second transistor 30 is connected to the other of the two adjacent word lines RL1, and the sources of the first transistor 20 and the second transistor 30 are connected to the source line SL1. In other embodiments, the first transistor 20 and the second transistor may not be of a common source design.

In this embodiment, the first transistor 20 and the second transistor 30 corresponding to the magnetic memory cell 50, and the first transistor 20' and the second transistor 30' corresponding to the adjacent magnetic memory cell 50' are isolated in the substrate by the shallow trench isolation structure 106.

Specifically, taking the first transistor and the second transistor as NMOS as an example, as shown in fig. 3, when writing "1" into the first bit cell 50a, the first transistor 20 is turned on by applying a high voltage Vdd to the first word line WL1, the second transistor 30 is turned off by applying a ground voltage to the second word line RL1, the common bit line BL1-2 (BL 2-1) floats, the first bit line BL1-1 applies the high voltage Vdd, the source line SL1 applies the ground voltage, and in order to operate independently of the adjacent magnetic memory cell 50', the second source line SL2 and the second bit line BL2-2 of the adjacent magnetic memory cell 50' float, the substrate second well region 107 'of the first transistor 20' of the adjacent magnetic memory cell 50 'applies a positive voltage to turn off the first transistor 20', so that the state of the first bit cell 50a is set to "1". When writing a "0" to the first bit cell 50a, the first transistor is gated by applying a high voltage Vdd on the first word line WL1, the second transistor is turned off by applying a ground voltage on the second word line RL1, the common bit line BL1-2 (BL 2-1) floats, the first bit line BL1-1 applies a ground voltage, the source line SL1 applies a high voltage Vdd, and in order to operate independently of the adjacent magnetic memory cell 50', the second source line SL2 and the second bit line BL2 of the adjacent magnetic memory cell 50' float, the substrate first well region 107 of the first transistor 20 of the adjacent magnetic memory cell 50' applies a positive voltage to turn off the first transistor 20 to set the state of the first bit cell 50a to "0".

When writing a "1" to the second bit cell 50b, the first transistor is turned on by applying a high voltage Vdd to the first word line WL1, the second transistor 30 is turned off by applying a ground voltage to the second word line RL1, the first bit line BL1-1 floats, the common bit line BL1-2 (BL 2-1) applies the high voltage Vdd, the first source line SL1 applies the ground voltage, and in order to operate independently of the adjacent magnetic memory cell 50', the second source line SL2 and the second bit line BL2 of the adjacent magnetic memory cell 50' float, the substrate second well region 107 'of the first transistor 20' of the adjacent magnetic memory cell 50 'applies a positive voltage to turn off the first transistor 20', so that the state of the first bit cell 50a is set to "1". When writing a "0" to the first bit cell 50a, the first transistor is turned on by applying a high voltage Vdd to the first word line WL1, the second transistor is turned off by applying a ground voltage to the second word line RL1, the first bit line BL1-1 floats, the common bit line BL1-2 (BL 2-1) applies a ground voltage, the first source line SL1 applies a high voltage Vdd, and in order to operate independently of the adjacent magnetic memory cell 50', the second source line SL2 and the second bit line BL2 of the adjacent magnetic memory cell 50' float, the substrate second well region 107 'of the first transistor 20' of the adjacent magnetic memory cell 50 'applies a positive voltage to turn off the first transistor 20' to set the state of the first bit cell 50a to "0".

As shown in fig. 4, for the magnetic memory cell 50' within the dashed box, when writing a "1" to the first bit cell 50a ', a high voltage Vdd is applied to the first word line WL1 to gate the first transistor 20', a ground voltage is applied to the second word line RL1 to turn off the second transistor 30', a high voltage Vdd is applied to the common bit line BL1-2 (BL 2-1), the second bit line BL2-2 is floated, and a ground voltage is applied to the second source line SL2, so that the first source line SL1 and the first bit line BL1-1 of the adjacent magnetic memory cell 50 can be independently operated with each other, a positive voltage is applied to the substrate first well region 107 of the first transistor 20 of the adjacent magnetic memory cell 50 to turn off the first transistor 20 to set the state of the first bit cell 50a ' to "1". When writing a "0" to the first bit cell 50a ', the first transistor 20' is gated by applying a high voltage Vdd on the first word line WL1, the second transistor 30 'is turned off by applying a ground voltage on the second word line RL1, the common bit line BL1-2 (BL 2-1) is applied, the second bit line BL2-2 is floated, the second source line SL2 is applied with a high voltage Vdd, and in order to operate independently of the adjacent magnetic memory cell 50, the first source line SL1 and the first bit line BL1-1 of the adjacent magnetic memory cell 50 are floated, the first well region 107 of the substrate of the first transistor 20 of the adjacent magnetic memory cell 50 is applied with a positive voltage to turn off the first transistor 20 to set the state of the first bit cell 50a' to "0".

As shown in fig. 4, for the magnetic memory cell 50' in the dashed box, when writing "1" to the second bit cell 50b ', the first transistor 20' is turned on by applying the high voltage Vdd to the first word line WL1, the second transistor 30' is turned off by applying the ground voltage to the second word line RL1, the common bit line BL1-2 (BL 2-1) floats, the second bit line BL2-2 applies the high voltage Vdd, the second source line SL2 applies the ground voltage, and in order to operate independently of the adjacent magnetic memory cell 50, the first source line SL1 and the first bit line BL1-1 of the adjacent magnetic memory cell 50 float, the substrate first well 107 of the first transistor 20 of the adjacent magnetic memory cell 50 applies the positive voltage to turn off the first transistor 20, so that the state of the second bit cell 50b ' is set to "1". When writing a "0" to the second bit cell 50b ', the first transistor 20' is turned on by applying a high voltage Vdd to the first word line WL1, the second transistor 30 'is turned off by applying a ground voltage to the second word line RL1, the common bit line BL1-2 (BL 2-1) floats, the second bit line BL2-2 applies a ground voltage, the second source line SL2 applies a high voltage Vdd, and in order to operate independently of the adjacent magnetic memory cell 50, the first source line SL1 and the first bit line BL1-1 of the adjacent magnetic memory cell 50 float, the substrate first well region 107 of the first transistor 20 of the adjacent magnetic memory cell 50 applies a positive voltage to turn off the first transistor 20 to set the state of the second bit cell 50b' to "0".

Of course, for the case that the first transistor and the second transistor are PMOS, a person skilled in the art may make corresponding modifications according to the operation of the NMOS, for example, a negative voltage may be applied to the substrate well region of the PMOS to turn off the corresponding switching transistor. The read/write control unit may also control the operation states of the first transistor 20 and the second transistor 30 in at least one of the memory cells to read the state of the first bit cell 50a or the second bit cell 50 b. Specifically, the read-write control unit controls the working states of the first transistor and the second transistor by controlling the voltages of the adjacent 2 word lines of at least one memory cell and controlling the voltages applied to the first transistor substrate of the memory cell and/or the adjacent memory cell thereof; the state of the first bit cell 50a or the second bit cell 50b is read by gating one of the adjacent two bit lines and controlling its voltage, the voltage of the source line. Specifically, by injecting an input current into the magnetic tunnel junction (as shown by the arrow in fig. 8), the magnitude of the output current flowing through the magnetic tunnel junction is read to determine whether the resistance state of the magnetic tunnel junction is a high resistance state or a low resistance state, as shown in fig. 8. Of course, in other embodiments, the read current direction of the first cell 50a and the second cell 50b may be reversed, and is not limited to the above-listed examples.

Specifically, taking the first transistor and the second transistor as NMOS as an example, as shown in fig. 3, when the first bit cell 50a is read out, a ground voltage is applied to the first word line WL1 to turn off the first transistor 20, a high voltage Vdd is applied to the second word line RL1 to gate the second transistor 30, the common bit line BL1-2 (BL 2-1) floats, the high voltage Vdd is applied to the first bit line BL1-1, the ground voltage is applied to the first source line SL1, and in order to operate independently of the adjacent magnetic memory cell 50', the second source line SL2 and the second bit line BL2-2 of the adjacent magnetic memory cell 50', the substrate second well region 107 'of the first transistor 20' of the adjacent magnetic memory cell 50 'is applied with a positive voltage to turn off the first transistor 20' to read out a current flowing through the first bit cell 50 a.

In reading the second bit cell 50b, the first transistor 20 is turned off by applying a ground voltage to the first word line WL1, the second transistor 30 is turned on by applying a high voltage Vdd to the second word line RL1, the first bit line BL1-1 floats, the common bit line BL1-2 (BL 2-1) applies a high voltage Vdd, the first source line SL1 applies a ground voltage, and the second source line SL2 and the second bit line BL2 of the adjacent magnetic memory cell 50 'float in order to operate independently of the adjacent magnetic memory cell 50', and the substrate second well region 107 'of the first transistor 20' of the adjacent magnetic memory cell 50 'applies a positive voltage to turn off the first transistor 20' to read a current flowing through the second bit cell 50 b.

Specifically, taking the first transistor and the second transistor as NMOS as an example, as shown in fig. 4, when the first bit cell 50a ' is read out, a ground voltage is applied to the first word line WL1 to turn off the first transistor 20', a high voltage Vdd is applied to the second word line RL1 to gate the second transistor 30', a high voltage Vdd is applied to the common bit line BL1-2 (BL 2-1), the second bit line BL2-2 is floating, and a ground voltage is applied to the second source line SL2 to enable the adjacent magnetic memory cell 50 to operate independently of the adjacent magnetic memory cell 50, the first source line SL1 and the first bit line BL1-1 of the adjacent magnetic memory cell 50 are floating, and the substrate first well region 107 of the first transistor 20 of the adjacent magnetic memory cell 50 is applied with a positive voltage to turn off the first transistor 20 to read out a current flowing through the first bit cell 50 a.

In reading the second bit cell 50b ', the first transistor 20' is turned off by applying a ground voltage to the first word line WL1, the second transistor 30' is turned on by applying a high voltage Vdd to the second word line RL1, the common bit line BL1-2 (BL 2-1) floats, the high voltage Vdd is applied to the second bit line BL2-2, the ground voltage is applied to the second source line SL2, and in order to operate independently of the adjacent magnetic memory cell 50, the first source line SL1 and the first bit line BL1-1 of the adjacent magnetic memory cell 50 float, the first well region 107 of the substrate of the first transistor 20 of the adjacent magnetic memory cell 50 is applied with a positive voltage to turn off the first transistor 20, so that a current flowing through the first bit cell 50a is read.

Of course, for the case that the first transistor and the second transistor are PMOS, a person skilled in the art may make corresponding modifications according to the operation of the NMOS, for example, a negative voltage may be applied to the substrate well region of the PMOS to turn off the corresponding switching transistor. The present embodiment also provides a magnetic memory structure and a method for manufacturing the same, as shown in fig. 2, the magnetic memory structure includes a substrate 10, a plurality of magnetic memory cells formed on the substrate 10, each of the magnetic memory cells including: a first transistor 20 and a second transistor 30, the first transistor 20 and the second transistor 30 each comprising a gate line structure and source and drain regions 103, 101, 102 in the substrate 10 between the gate line structures;

a first bit cell 50a and a second bit cell 50b, the first bit cell 50a comprising a spin-orbit torque layer 501, a first magnetic tunnel junction 502 and a first upper electrode 504 on the spin-orbit torque layer 501; the second bit cell 50b includes a spin-orbit torque layer 501, a second magnetic tunnel junction 503 and a second upper electrode 505 on the spin-orbit torque layer 501;

an insulating dielectric layer 407 formed on the substrate 10, wherein the insulating dielectric layer 407 includes a plurality of contact holes 408;

A plurality of metal wiring layers, wherein each metal wiring layer comprises a metal wire 401, 402, 403 or 404, a via 405 and an interlayer dielectric 406; for example, a first metal wiring layer is formed by a first metal wire 401, a via 405, and an interlayer dielectric 406, a second metal wiring layer is formed by a second metal wire 402, a via 405, and an interlayer dielectric 406, a third metal wiring layer is formed by a third metal wire 403, a via 405, and an interlayer dielectric 406, a fourth metal wire 404, a via 405, and an interlayer dielectric 406, a fourth metal wiring layer, and so on;

the drain region 102 of the first transistor 20 is electrically connected to the spin orbit torque layer 501 common to the first bit cell 50a and the second bit cell 50b through the contact hole 408, the metal wire and the via 405, and the drain region 101 of the second transistor 30 is connected to the first upper electrode 504 and the second upper electrode 505 through the contact hole 408, the metal wire and the via 405.

Wherein the first bit cell 50a, the second bit cell 50b of the magnetic memory cell 50 and the first bit cell 50a ' and the second bit cell 50b ' of the adjacent magnetic memory cell 50' share a spin-orbit torque layer 501 and a metal wiring layer; the first transistor 20 of the magnetic memory cell 50 is connected to the gate of the first transistor 20 'of the adjacent magnetic memory cell 50' by the same word line WL 1;

The first transistor 20 of the magnetic memory cell 50 and the first transistor 20 'of its neighboring magnetic memory cell 50' each have separate substrate well regions and are each routed from a different metal line. This arrangement allows different voltages to be applied to the two transistor substrates (wells) to achieve different operation of switching on and off the two transistors simultaneously, avoiding interaction between the first transistor 20 of the magnetic memory cell 50 belonging to one word line and the first transistor 20 'of its neighboring magnetic memory cell 50'. For example, the substrate (well) voltage of the first transistor or the second transistor in the memory cell can be controlled to realize reading and writing of the memory cell; for another example, the substrate (well) voltage of the first transistor or the second transistor in the adjacent memory cell of the memory cell can be controlled to realize the reading and writing of the memory cell.

The gate 104 of the first transistor 20 may be configured as a word line WL for writing by a metal wire in a metal wiring layer connected to the contact hole 408, and the gate 105 of the second transistor 30 may be configured as a word line RL for reading by a metal wire in a metal wiring layer connected to the contact hole 408.

A metal wiring layer below the spin-orbit torque layer 501 is used as a bit line layer, two ends of the spin-orbit torque layer 501 are respectively connected with two bit lines BL1-1 and BL2-2 through vias in the metal wiring layer, wherein one bit line is used as a bit line BL1-1 of a first bit cell of the magnetic memory cell 50, and the other bit line is used as a bit line BL2-2 of a second bit cell of a magnetic memory cell 50' adjacent to the magnetic memory cell 50; the middle of the two adjacent magnetic memories common spin-orbit torque layer 501 is connected to the common bit line BL1-2 (BL 2-1) through a common via in the metal wiring layer. The second bit unit of the magnetic memory and the first bit unit of the adjacent magnetic memory adopt a shared bit line design, so that the area of the memory can be effectively saved.

The first transistor 20 and the second transistor 30 are both NMOS or PMOS, and the two transistors are located in the same well region, which is formed by the process of ion implantation onto the substrate 10, and which may be an N-well (PMOS) or a P-well (NMOS), or an NMOS transistor or a PMOS transistor prepared based on FD-SOI (fully depleted silicon on insulator), or the like.

The first transistor 20 and the second transistor 30 together have a structural design. The first transistor 20 and the second transistor 30 are identical in structure and each comprise a gate line structure and source and drain regions in the substrate between the gate line structures. Both transistors are made by conventional logic device design rules and processes including polysilicon deposition processes, photolithography and etching. The gate line of the first transistor 20 serves as a write control line for the two bit cells, namely word line WL; the gate line of the second transistor 30 serves as the read control line for the two bit cells, namely word line RL.

The first transistor 20 and the second transistor 30 are commonly configured. The source and drain regions of the first transistor 20 and the second transistor 30 are formed by ion implantation processes, have the same depth, and are conventional logic process and design. In order to save the area of the transistors, the two transistors are designed in a common source structure, i.e. the first transistor 20 and the second transistor 30 share the same source region 103, the common source region 103 of the transistors is located between the two transistor gates 104 and 105 of the first and the second transistor, and the source region 103 is led out through a source line SL 1. Compared with the traditional two-separated transistor design structure, the design of the common source structure transistor can eliminate the STI isolation layer design between the two transistors, and the area of the common source structure transistor can be saved by 40% from the area of the two transistors alone, so that the area of the first magnetic memory cell and the area of the second magnetic memory cell are saved. Meanwhile, from the perspective of the whole magnetic memory array, since the source lines of every two memory cells can be merged from two to one, as shown in SL1 in fig. 2, the whole memory array area is greatly saved. By applying a high voltage or a low voltage to the source line SL1, the corresponding first bit line BL1-1 or the common bit line BL1-2 (BL 2-1) is connected to the low voltage or the high voltage or floating (floating), and the first or second transistor 30 is turned on or off, thereby controlling a direction in which a current flows, to perform a read/write operation on the first or second magnetic memory cell.

The drain region connection of the first transistor 20 and the second transistor 30 is designed. The drain region 102 of the first transistor 20 is in the left well of its gate 104, and the drain region 102 is connected to the upper first layer metal wiring 401, the second layer metal wiring 402 and the third layer metal wiring 403, and the Via (Via) 405 in each wiring layer, all the way to the spin-orbit torque 501 common to the first and second magnetic bit cells, as a channel through which current flows through the first bit line BL1-1 and the common bit line BL1-2 (BL 2-1) and the spin-orbit torque layer (SOT layer) and the current of the first transistor 20 at the time of the two bit cell writing operation, through a Contact hole (Contact) 408. The drain region 101 of the second transistor 30 is within the right side well of the second transistor 30, and the drain region 101 of the second transistor 30 is directly connected to the first upper electrode of the first magnetic tunnel junction and the second upper electrode of the second magnetic tunnel junction of the two bit cells through a Contact hole (Contact) 408, metal wires and vias (Via) 405 in the upper metal wiring layer, as channels for the current to flow through the first bit line BL1-1 or the common bit line BL1-2 (BL 2-1) and the first/second magnetic tunnel junction and the second transistor 30 during a memory cell read operation. The two memory cells share the same metal line connection, so that the cell area occupied by metal wiring is reduced, and the area of the whole memory array is further reduced, but in specific operation, the first or second magnetic bit cell can be selected by controlling whether the first bit line BL1-1 and the shared bit line BL1-2 (BL 2-1) are subjected to voltage or floating. The Contact 408, the metal wires in each metal wiring layer, the Via 405 and the interlayer dielectric are all made according to the conventional logic rule design and the conventional logic process, the metal layer number and the corresponding Via 405 layer are determined according to the position of the metal layer where the magnetic memory cell is placed, and the three-layer metal design is just one example.

The design of the memory cell bit line. A first bit line BL1-1 of a first magnetic tunnel junction for connecting the first tunnel junction spin-orbit torque layer in all memory cells of each column in the magnetic memory array; a common bit line BL1-2 (BL 2-1) of the second magnetic tunnel junction is used to connect the second tunnel junction spin-orbit torque layer in all memory cells of each column in the magnetic memory array. The first bit line BL1-1 and the shared bit line BL1-2 (BL 2-1) are both a spin-orbit torque layer next-level metal structure, and are designed and processed according to the design rules and processes of the Logic interconnect metal layer and are connected to the tunnel junction spin-orbit torque layer through a Via (Via) 405.

Formation of a magnetic memory array. All transistor gates 104 on the row of the first transistor 20 are all connected together by one word line to form WL, all transistor gates 105 on the row of the second transistor 30 are all connected together by another word line to form RL, adjacent to WL and RL, oriented perpendicular to the gate line direction of the first and second transistors 30, and connected to peripheral control circuitry of the magnetic memory array, respectively. Word lines WL and RL form two adjacent rows of control lines of the memory array. As described above, the source lines of the first transistor 20 and the second transistor 30 are all connected as one common source line, which is perpendicular to the word lines WL and RL connecting the two gates 104 and 105 together. All first bit lines BL1-1 of the column in which the first magnetic tunnel junction is located are all connected together by a metal layer for controlling all magnetic tunnel junctions on the column, and all common bit lines BL1-2 (BL 2-1) of the column in which the second magnetic tunnel junction is located are all connected together by a metal layer for controlling all magnetic tunnel junctions on the column. The first bit line BL1-1 and the shared bit line BL1-2 (BL 2-1) form two bit lines of a pair of adjacent magnetic tunnel junctions, the bit line direction being parallel to the common source line direction. Thus, a magnetic memory array is formed with the first bit line BL1-1 and the shared bit line BL1-2 (BL 2-1) perpendicular to the word lines WL/RL.

Control of read and write operations by the first transistor 20 and the second transistor 30 in the memory cell. Looking at the write "1" operation of the first bit cell, the word line WL connected to the first transistor 20 is applied with a high voltage, so that the first transistor 20 is turned on, the corresponding source line SL1 is connected to a low voltage, and the word line RL connected to the second transistor 30 is connected to a low voltage, so that it is turned off. The bit line BL1-1 of the first tunnel junction is charged with a high voltage and the common bit line BL1-2 (BL 2-1) floats to avoid the influence of current on the second bit cell through the common bit line BL1-2 (BL 2-1). Under the voltage loading condition of each end, the current flow is realized to flow through the source line SL1, the first transistor 20, the spin orbit torque layer and the first bit line BL1-1, so that the writing '1' operation of the first bit unit is realized.

The write "0" operation of the first bit cell causes the first transistor 20 to be turned on by applying a high voltage to the word line WL connected to the first transistor 20, the corresponding source line SL1 is connected to the high voltage, and the word line RL connected to the second transistor 30 is connected to the low voltage, so that it is turned off. The first bit line BL1-1 of the first tunnel junction is applied with a low voltage and the common bit line BL1-2 (BL 2-1) floats to avoid the influence of current on the second bit cell through the common bit line BL1-2 (BL 2-1). Under the voltage loading condition of each end, the current flow is realized to flow through the first bit line BL1-1, the spin orbit torque layer, the first transistor 20 and the source line SL1, so that the operation of writing '0' into the first bit memory cell is realized.

The write operation to the second bit cell is the same as the write operation to the first bit cell described above, except that the corresponding first bit line BL1-1 is replaced with the common bit line BL1-2 (BL 2-1), and the first bit line BL1-1 floats (floating) to avoid current flowing through the first bit line BL1-1, thereby affecting the state of the first memory cell.

And a read operation of the memory cell. First, looking at the read operation of the first bit cell, the word line RL connected to the second transistor 30 is turned on by applying a high voltage to the word line RL, the corresponding source line SL1 is connected to a low voltage, and the word line WL connected to the first transistor 20 is connected to a low voltage to be turned off. The first bit line BL1-1 of the first tunnel junction is applied with a high voltage, and the common bit line BL1-2 (BL 2-1) floats (floating) to avoid the influence of the state of the second bit cell on the first bit cell. Under the voltage loading condition of each end, the current flowing through the source line SL1, the second transistor 30, the first magnetic memory cell tunnel junction, the first magnetic bit cell spin orbit torque layer and the first bit line BL1-1 is read, and the memory cell is determined to be in a '1' or '0' state at the moment according to the judgment of the value of the BL-1 read current.

The read operation for the second bit cell is the same as the read operation for the first bit cell described above, except that the corresponding first bit line BL1-1 is replaced with the common bit line BL1-2 (BL 2-1), and the first bit line BL1-1 floats (floating) to avoid the effect of the state of the first bit cell on the state read of the second bit cell.

In order that two adjacent magnetic memory cells do not affect each other during the above operation, different voltages may be applied to the two transistor substrates (well regions) when operating the magnetic memory cell 50, so as to realize different on and off operations of the two transistors at the same time, and avoid the interaction between the first transistor 20 of the magnetic memory cell 50 belonging to one word line and the first transistor 20 'of the adjacent magnetic memory cell 50'. For example, the substrate (well) voltage of the first transistor or the second transistor in the memory cell can be controlled to realize reading and writing of the memory cell; for another example, the substrate (well) voltage of the first transistor or the second transistor in the adjacent memory cell of the memory cell can be controlled to realize the reading and writing of the memory cell.

Specifically, as shown in fig. 2, the first magnetic tunnel junction 502 and the second magnetic tunnel junction 503 are stacked above the first transistor 20 and the second transistor 30. The first transistor 20, the second transistor 30, the first magnetic tunnel junction 502 and the second magnetic tunnel junction 503 are electrically connected by wiring layers, for example, in this embodiment, including 4 metal wiring layers 401, 402, 403, 404, each of which includes a metal wire, a (metal Via) and an interlayer dielectric 406 electrically connected to the metal wires, in this embodiment, the metal wires in the first layer metal wire 401 for connecting the first transistor gate 104 and the second transistor gate 105 are set as word lines, the metal wires in the second metal layer 402 for connecting the first transistor and the second transistor common source region 103 are set as source lines SL1, the metal wires in the third metal wiring layer 403 for connecting the first bit cell and the second bit cell common spin torque layer 501 are set as bit lines, and the metal wires in the fourth layer metal wire 404 are set as conductive channels connecting the upper electrodes of the first magnetic tunnel junction 502 and the second magnetic tunnel junction 503 and the second transistor common drain electrode 30 to the drain electrode.

The material of the spin-orbit torque layer 501 comprises one of heavy metal and topological insulator, the heavy metal comprises one of Pt, ta and W, the topological insulator comprises one of BiSe alloy and BiSb alloy, the thickness of the spin-orbit torque layer 501 is between 2nm and 30nm, the length is between 100nm and 800nm, and the width is between 10nm and 100 nm.

As shown in fig. 5, the magnetic tunnel junction includes a free magnetic layer, a fixed magnetic layer, and an insulating tunnel layer disposed between the free magnetic layer and the fixed magnetic layer, wherein the fixed magnetic layer has a fixed first magnetic pole, the free magnetic layer has a variable second magnetic pole, the magnetic tunnel junction is in a low resistance state if the first magnetic pole is in the same direction as the second magnetic pole, and the magnetic tunnel junction is in a high resistance state if the first magnetic pole is opposite to the second magnetic pole. For example, the diameter of the magnetic tunnel junction may be between 10nm and 90nm, for example, the diameter of the magnetic tunnel junction may be 60nm. It should be noted that a thin film layer structure having other functions may be further included between the spin-orbit torque layer 501 and the free magnetic layer.

In one embodiment, as shown in fig. 6, the free magnetic layer is located on the spin-orbit torque layer 501, the direction of the first magnetic pole is vertical, the material of the free magnetic layer includes one of CoFeB alloy, feB alloy and CoFe alloy, and the thickness of the free magnetic layer is between 0.8nm and 1.3 nm.

In yet another embodiment, as shown in FIG. 6, the free magnetic layer includes a synthetic antiferromagnetic structure including first and second layers of ferromagnetic material that are aligned in opposite directions, and a nonmagnetic material coupling spacer layer between the first and second layers of ferromagnetic material.

The second magnetic pole direction of the fixed magnetic layer is a vertical direction, and the material of the fixed magnetic layer comprises one of CoFeB alloy, feB alloy and CoFe alloy, and the thickness of the fixed magnetic layer is between 0.8nm and 1.3 nm. The material of the insulating tunnel layer comprises MgO, and the thickness of the MgO is between 0.8nm and 1.3 nm.

As shown in FIG. 5, the magnetic tunnel junction further includes a spacer layer on the fixed magnetic layer and a synthetic antiferromagnetic structure on the spacer layer. For example, the material of the spacer layer may include one of Ta, co-containing alloys, and Fe-containing alloys, and may also include W or Mo to increase the thermal stability of the device. The thickness of the spacer layer is between 0.2nm and 1.2 nm. The synthetic antiferromagnetic structure includes first and second layers of ferromagnetic material that are aligned in opposite directions, and a nonmagnetic material coupling spacer layer between the first and second layers of ferromagnetic material. The ferromagnetic material layer may include a plurality of ferromagnetic composite layers, for example, 4-20, the thickness of the ferromagnetic composite layers is between 0.2nm and 0.6nm, the material of the ferromagnetic composite layers includes one of a Co/Pt composite layer, a Co/Pd composite layer and a Co/Ni composite layer, and the material of the non-magnetic material coupling interlayer includes Ru, and the thickness of the non-magnetic material coupling interlayer is between 0.4nm and 0.9 nm.

As an application example of the magnetic memory array of the present embodiment, the magnetic memory array may be integrated into at least one of: music players, video players, entertainment units, navigation devices, communications devices, personal digital assistants, fixed location data units, mobile phones, and portable computers.

It should be noted that, the first transistor 20', the second transistor 30', the first bit cell 50a ', and the second bit cell 50b ' of the adjacent magnetic memory cell 50' are the same as the first transistor 20, the second transistor 30, the first bit cell 50a, and the second bit cell 50b of the magnetic memory cell 50, and the common bit line BL1-2 (BL 2-1) is used as the magnetic memory cell 50, and their corresponding read/write operation is explained in detail above and will not be described here. The first transistor 20 and the second transistor 30 corresponding to the magnetic memory cell 50, and the first transistor 20' and the second transistor 30' corresponding to the adjacent magnetic memory cell 50' are isolated in the substrate by the shallow trench isolation structure 106.

The embodiment also provides a read-write control method of the magnetic memory array, which comprises the following steps: controlling the operating states of the first and second transistors of the at least one magnetic memory cell 50, controlling the current flowing through the spin-orbit torque layer 501 to set the state of the first or second bit cell 50a, 50 b; or controlling the operating states of the first transistor, the second transistor of at least one magnetic memory cell 50, reading the state of said first bit cell 50a or second bit cell 50 b.

For example, the operating states of the first transistor, the second transistor of the magnetic memory cell may be controlled by controlling the voltages of the adjacent 2 word lines to which at least one magnetic memory cell is connected, controlling the voltages applied to the memory cell and/or the first transistor substrate of its adjacent memory cell; the state of the first bit cell or the second bit cell is set by controlling a current flowing through the spin-orbit torque layer by gating one of the bit line and the common bit line and controlling a voltage thereof, a voltage of a source line. Controlling the operating states of the first transistor and the second transistor of the memory cell by controlling the voltages of the adjacent 2 word lines connected with at least one memory cell and controlling the voltages applied to the memory cell and/or the first transistor substrate of the adjacent memory cell; the state of the first bit cell or the second bit cell is read by gating one of the bit line and the common bit line and controlling its voltage, and the voltage of the source line. Further, the state of the first magnetic tunnel junction 502 or the second magnetic tunnel junction can be set to a high resistance state or a low resistance state by controlling the current flowing through the spin orbit torque layer 501.

Of course, for the case that the first transistor and the second transistor are PMOS, a person skilled in the art may make corresponding modifications according to the operation of the NMOS, for example, a negative voltage may be applied to the substrate well region of the PMOS to turn off the corresponding switching transistor. As described above, the magnetic memory structure, array, read-write control method and preparation method of the invention have the following beneficial effects:

the invention provides a novel magnetic memory array (SOT-MRAM), wherein a magnetic memory structure in the array comprises two adjacent magnetic memory units, 4 switching transistors (transistors) are used for driving 4 magnetic bit units (MTJs) to form a 4T-4R structure, 4 memory bits (bits) can be stored in the magnetic memory structure, each magnetic bit unit can be independently operated, more memory units are effectively arranged on a unit area, and the integration density can be greatly increased.

Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.

The above embodiments are merely illustrative of the principles of the present invention and its effectiveness, and are not intended to limit the invention. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the invention. Accordingly, it is intended that all equivalent modifications and variations of the invention be covered by the claims, which are within the ordinary skill of the art, be within the spirit and scope of the present disclosure.

Claims

1. A magnetic memory array, comprising:

A plurality of magnetic memory cells, each of the plurality of magnetic memory cells: the magnetic memory comprises a first transistor, a second transistor, a first bit unit and a second bit unit, wherein the bit units of two adjacent magnetic memory units share a spin orbit torque layer and a shared bit line, the first bit unit and the second bit unit are respectively connected with the bit line and the shared bit line through the spin orbit torque layer, and the shared bit line is connected with the spin orbit torque layer between the two adjacent magnetic memories; the first bit unit and the second bit unit are connected with adjacent first word lines and second word lines through the first transistor and the second transistor, the first bit unit comprises a first magnetic tunnel junction and a first upper electrode, the second bit unit comprises a second magnetic tunnel junction and a second upper electrode, the upper electrode of the first bit unit and the upper electrode of the second bit unit are connected with the drain electrode of the second transistor, the drain electrode of the first transistor is electrically connected with a spin orbit torque layer between the first bit unit and the second bit unit, the grid electrode of the first transistor is connected with the first word lines, the grid electrode of the second transistor is connected with the second word lines, and the sources of the first transistor and the second transistor are connected with the source lines;

And the read-write control unit is connected with at least one magnetic memory unit through a source line, a bit line and a shared bit line and controls the working states of the first transistor and the second transistor in the at least one magnetic memory unit so as to read or set the states of the first bit unit or the second bit unit.

2. The magnetic memory array of claim 1, wherein the material of the spin-orbit torque layer comprises one of a heavy metal comprising one of Pt, ta, and W and a topological insulator comprising one of a BiSe alloy and a BiSb alloy.

3. The magnetic memory array of claim 1, wherein the read-write control unit controls the operating states of the first and second transistors in at least one of the magnetic memory cells, and controls the current flowing through the spin-orbit torque layer to set the state of the first or second bit cell.

4. A magnetic memory array according to claim 3 wherein the read-write control unit controls the voltages of the adjacent 2 word lines to which at least one magnetic memory cell is connected, controls the voltages applied to the memory cell and/or the first transistor substrate of its adjacent memory cell to control the operating states of the first and second transistors of the magnetic memory cell; the state of the first bit cell or the second bit cell is set by controlling a current flowing through the spin-orbit torque layer by gating one of the bit line and the common bit line and controlling a voltage thereof, a voltage of a source line.

5. The magnetic memory array of claim 1 wherein the read-write control unit controls the operating states of the first and second transistors in at least one of the memory cells to read the states of the first and second bit cells.

6. The magnetic memory array of claim 5, wherein the read-write control unit controls the operating states of the first and second transistors of the memory cells by controlling voltages of adjacent 2 word lines to which at least one of the memory cells is connected, controlling voltages applied to the first transistor substrate of the memory cell and/or its adjacent memory cell; the state of the first bit cell or the second bit cell is read by gating one of the bit line and the common bit line and controlling its voltage, and the voltage of the source line.

7. The magnetic memory array of claim 1, wherein the first transistor and the second transistor are common source.

8. The magnetic memory array of claim 1, wherein: the magnetic tunnel junction comprises a free magnetic layer, a fixed magnetic layer and an insulating tunnel layer arranged between the free magnetic layer and the fixed magnetic layer, wherein the fixed magnetic layer is provided with a fixed first magnetic pole, the free magnetic layer is provided with a variable second magnetic pole, the magnetic tunnel junction is in a low-resistance state if the first magnetic pole and the second magnetic pole are in the same direction, and the magnetic tunnel junction is in a high-resistance state if the first magnetic pole and the second magnetic pole are opposite.

9. The magnetic memory array of claim 8, wherein: the free magnetic layer is positioned on the spin-orbit torque layer, the direction of the first magnetic pole is vertical, the material of the free magnetic layer comprises one of CoFeB alloy, feB alloy and CoFe alloy, and the thickness of the free magnetic layer is between 0.8nm and 1.3 nm.

10. The magnetic memory array of claim 8, wherein: the free magnetic layer includes a synthetic antiferromagnetic structure including first and second layers of ferromagnetic material that are aligned in opposite directions, and a nonmagnetic material coupling spacer layer between the first and second layers of ferromagnetic material.

11. The magnetic memory array of claim 8, wherein: the second magnetic pole direction of the fixed magnetic layer is a vertical direction, and the material of the fixed magnetic layer comprises one of CoFeB alloy, feB alloy and CoFe alloy, and the thickness of the fixed magnetic layer is between 0.8nm and 1.3 nm.

12. The magnetic memory array of claim 8, wherein: the material of the insulating tunnel layer comprises MgO, and the thickness of the MgO is between 0.8nm and 1.3 nm.

13. The magnetic memory array of claim 8, wherein: the magnetic tunnel junction further includes a spacer layer on the fixed magnetic layer and a synthetic antiferromagnetic structure on the spacer layer.

14. The magnetic memory array of claim 13, wherein: the material of the spacer layer comprises one of Ta, an alloy containing Co and an alloy containing Fe; the thickness of the spacer layer is between 0.2nm and 1.2 nm.

15. The magnetic memory array of claim 13, wherein: the synthetic antiferromagnetic structure includes first and second layers of ferromagnetic material that are aligned in opposite directions, and a nonmagnetic material coupling spacer layer between the first and second layers of ferromagnetic material.

16. The magnetic memory array of claim 15, wherein: the ferromagnetic material layer comprises a plurality of ferromagnetic composite layers, the thickness of the ferromagnetic composite layers is between 0.2nm and 0.6nm, the material of the ferromagnetic composite layers comprises one of a Co/Pt composite layer, a Co/Pd composite layer and a Co/Ni composite layer, and the material of the nonmagnetic material coupling interlayer comprises Ru, and the thickness of the nonmagnetic material coupling interlayer is between 0.4nm and 0.9 nm.

17. The magnetic memory array of claim 1, wherein: the diameter of the magnetic tunnel junction is between 10nm and 90 nm.

18. The magnetic memory array of claim 1, wherein: the first magnetic tunnel junction, the second magnetic tunnel junction are stacked over the first transistor and the second transistor.

19. The magnetic memory array of claim 1, wherein: is integrated into at least one of the following: entertainment units, navigation devices, communications devices, personal digital assistants, and fixed location data units.

20. A read-write control method of a magnetic memory array according to any one of claims 1 to 19, comprising:

controlling the operating states of the first transistor, the second transistor of at least one magnetic memory cell, controlling the current flowing through the spin-orbit torque layer to set the state of the first bit cell or the second bit cell; or alternatively

And controlling the working states of a first transistor and a second transistor of at least one magnetic memory unit, and reading the states of the first bit unit and the second bit unit.

21. The method of claim 20, wherein the voltages of adjacent 2 word lines to which at least one magnetic memory cell is connected are controlled, and the voltages applied to the memory cell and/or the first transistor substrate of its adjacent memory cell are controlled to control the operation states of the first and second transistors of the magnetic memory cell; the state of the first bit cell or the second bit cell is set by controlling a current flowing through the spin-orbit torque layer by gating one of the bit line and the common bit line and controlling a voltage thereof, a voltage of a source line.

22. The method according to claim 20, wherein the operating states of the first transistor and the second transistor of the memory cell are controlled by controlling voltages of adjacent 2 word lines to which at least one of the memory cells is connected, and controlling voltages applied to the memory cell and/or the first transistor substrate of the adjacent memory cell; the state of the first bit cell or the second bit cell is read by gating one of the bit line and the common bit line and controlling its voltage, and the voltage of the source line.

23. The method of claim 22, wherein the first magnetic tunnel junction and the second magnetic tunnel junction are set to a high-resistance state or a low-resistance state by controlling a current flowing through the spin-orbit torque layer.

24. The method of claim 20, wherein: comprising the following steps: the output current flowing through the first bit unit and the second bit unit is read to judge whether the resistance state is a high resistance state or a low resistance state.

25. A magnetic memory structure comprising:

A substrate;

a plurality of magnetic memory cells formed on a substrate, the magnetic memory cells comprising:

a first transistor, a second transistor, each comprising a gate line structure and source and drain regions in the substrate between the gate line structures;

a first bit cell comprising a spin-orbit torque layer, a first magnetic tunnel junction on the spin-orbit torque layer, and a first upper electrode; the second bit cell includes the spin-orbit torque layer, a second magnetic tunnel junction located on the spin-orbit torque layer, and a second upper electrode;

a plurality of metal wiring layers, wherein each metal wiring layer comprises a metal wire, a via and an interlayer dielectric;

the drain region of the first transistor is electrically connected with the spin orbit torque layer shared by the first bit unit and the second bit unit through the contact hole, the metal wire and the via hole, and the drain region of the second transistor is connected with the first upper electrode and the second upper electrode through the contact hole, the metal layer wire and the via hole;

wherein the first bit cell, the second bit cell of the magnetic memory cell and the first bit cell and the second bit cell of the adjacent magnetic memory cell share a spin-orbit torque layer and a metal wiring layer; the first transistor of the magnetic memory unit is connected with the grid electrode of the first transistor of the adjacent magnetic memory unit by the same word line;

The first transistor of the magnetic memory unit and the first transistor of the adjacent magnetic memory are respectively provided with independent substrate well regions and are respectively led out by different metal wires.

26. The magnetic memory structure of claim 25 wherein the first transistor and the second transistor share a source region, the common source region being located between the gates of the first transistor and the second transistor, the common source region being routed through a source line.

27. The magnetic memory structure of claim 26, wherein the gates of the first transistors are implemented as word lines for writing by metal wires in the metal wiring layer connected to the contact holes, and the gates of the second transistors are implemented as word lines for reading by metal wires in the metal wiring layer connected to the contact holes, respectively.

28. The magnetic memory of claim 25 wherein a metal wiring layer below the spin-orbit torque layer serves as a bit line layer, two ends of the spin-orbit torque layer being connected to two bit lines respectively through vias in the metal wiring layer, one of the bit lines serving as a bit line of a first bit cell of the magnetic memory and the other bit line serving as a bit line of a second bit cell of an adjacent magnetic memory of the magnetic memory; the middle parts of the two adjacent magnetic memories share the spin orbit torque layer and are connected with the shared bit line through the shared via hole in the metal wiring layer.

29. A method of fabricating a magnetic memory structure, comprising the steps of:

providing a substrate, and forming an isolation region on the substrate;

forming a first transistor and a second transistor in an active region at one side of the isolation region, wherein the first transistor and the second transistor both comprise a grid line structure and a source region and a drain region which are positioned in the substrate and between the grid line structures;

forming a plurality of metal wiring layers, wherein each metal wiring layer comprises a metal wire, a via hole and an interlayer medium;

forming a first bit unit and a second bit unit between two adjacent upper and lower metal wiring layers, wherein the first bit unit comprises a spin orbit torque layer, a first magnetic tunnel junction and a first upper electrode which are positioned on the spin orbit torque layer, and the second bit unit comprises the spin orbit torque layer, a second magnetic tunnel junction and a second upper electrode which are positioned on the spin orbit torque layer;

Wherein the first bit cell, the second bit cell of the magnetic memory cell and the first bit cell and the second bit cell of the adjacent magnetic memory cell share a spin-orbit torque layer and a metal wiring layer; the first transistor of the magnetic memory unit is connected with the grid electrode of the first transistor of the adjacent magnetic memory unit by the same word line; the first transistor of the magnetic memory unit and the first transistor of the adjacent magnetic memory are respectively provided with independent substrate well regions and are respectively led out by different metal wires.

30. The method of claim 29, wherein a metal wiring layer under the spin-orbit torque layer is used as a bit line layer, and two ends of the spin-orbit torque layer are respectively connected with two bit lines through vias in the metal wiring layer, wherein one bit line is used as a bit line of a first bit cell of the magnetic memory, and the other bit line is used as a bit line of a second bit cell of an adjacent magnetic memory; the middle parts of the two adjacent magnetic memories share the spin orbit torque layer and are connected with the shared bit line through the shared via hole in the metal wiring layer.

31. The method of claim 29, wherein the first transistor and the second transistor share a source region, the common source region being located between gates of the first transistor and the second transistor, the common source region being routed through a source line.

32. The method of manufacturing a magnetic memory structure according to claim 29, wherein the gate of the first transistor is configured as a word line for writing through a metal wire in a metal wiring layer connected to the contact hole, and the gate of the second transistor is configured as a word line for reading through a metal wire in a metal wiring layer connected to the contact hole, respectively.