CN111343148A - A method, system and device for processing FGPA communication data - Google Patents

Abstract

The invention discloses a method for processing FGPA communication data. After using a preset protocol to encapsulate data packets, the data packets can be received through a network interface. The preset protocol defines frame types and frame contents, and the data packets can be received after the data packets are received. Then, the data packet is parsed according to the preset protocol, the frame type and frame content are determined, and corresponding operations are performed on the data in the frame content according to the frame type. Therefore, this solution can transmit FPGA data through the network instead of PCIE transmission data, so that the FPGA heterogeneous acceleration card It can not be installed in the PCIE slot, so as to avoid dependence on the server, and can receive and process data independently, reduce the dependence of the FPGA communication data processing process on the server CPU, and improve the data processing efficiency. The present application also provides a system, device and computer-readable storage medium for processing FGPA communication data, which can also achieve the above effects.

Description

A method, system and device for processing FGPA communication data

technical field

The present invention relates to FPGA technology, and more particularly, to a method, system and device for processing FPGA communication data.

Background technique

The FPGA (Field-Programmable Gate Array, Field Programmable Gate Array) heterogeneous accelerator card can accelerate the calculation of the source operation data sent by the CPU (Central Processing Unit, central processing unit), and return the calculation result to the CPU, thereby realizing High-performance computing power to complete functions that require high computing power, such as video encoding and decoding, deep learning, scientific computing, and graphics processing.

With the development of FPGA heterogeneous accelerator cards in cloud data centers, FPGA accelerator cards have begun to be deployed on a large scale. The existing deployment method generally adopts the method of machine-card binding, that is, each FPGA accelerator card is inserted through PCI-E. The slot is directly connected to the standard bus interface of the server. When a user applies for an FPGA instance, a virtual machine environment is generally allocated to the user, and the user uses the virtual machine to access and use the FPGA board.

At present, the deployment modes of FPGA heterogeneous accelerator cards mainly include single-machine single-card and single-machine multi-card modes, that is, one card is inserted into one server or multiple cards are inserted into one server. In the machine-card binding mode, the FPGA heterogeneous accelerator card is tightly coupled with the server's CPU, that is, the use of the FPGA heterogeneous accelerator card depends on the CPU, and the user can only access the FPGA heterogeneous accelerator card through the server's CPU.

Therefore, how to reduce the dependence of the FPGA communication data processing process on the server CPU and improve the data processing efficiency is a problem to be solved by those skilled in the art.

SUMMARY OF THE INVENTION

The purpose of the present invention is to provide a method, system and device for processing FGPA communication data, so as to reduce the expansion cost of the FPGA heterogeneous acceleration card.

To achieve the above purpose, the embodiments of the present invention provide the following technical solutions:

A method for processing FGPA communication data, comprising:

Utilize the network interface to receive the data packet encapsulated by the data sender using the preset protocol; wherein, the data packet includes frame type and frame content, and the frame content includes FPGA communication data information;

Parse the data packet to obtain the frame type and the frame content;

A data processing operation corresponding to the frame type is determined, and the data processing operation is performed on the FPGA communication data in the frame content.

Optionally, when the frame type includes a data movement type, performing the data processing operation on the FPGA communication data in the frame content includes:

The FPGA communication data in the frame content is moved according to the frame type.

Optionally, the frame type includes an RDMA type, and the FPGA communication data information includes a source address for storing the FPGA communication data, a data length for the FPGA communication data, and a destination address for storing the FPGA communication data;

Correspondingly, performing the data processing operation on the FPGA communication data in the frame content includes:

Moving the FPGA communication data of the data length to the destination address to the source address.

Optionally, the frame type includes a file programming type, and the FPGA communication data information includes the content of the file to be programmed;

Correspondingly, performing the data processing operation on the FPGA communication data in the frame content includes:

Program the content of the to-be-programmed file to the FPGA.

Optionally, the frame type includes an instruction type, the FPGA communication data information includes a read/write identifier, the number of commands and the command information of the number of commands, and each of the command information includes an FPGA register address and a Data to be written or empty data corresponding to the FPGA register address;

Correspondingly, performing the data processing operation on the FPGA communication data in the frame content includes:

According to the read and write identifiers, a register write or register read operation is sequentially performed on the FPGA register address in each command message.

Optionally, the frame type includes a reply type, and the FPGA communication data information includes a reply identifier;

Correspondingly, performing the data processing operation on the FPGA communication data in the frame content includes:

The processing result of the FPGA communication data is determined by using the reply identifier.

Optionally, the data packet further includes a frame sequence number, and after the use of the network interface to receive the data packet encapsulated by the data sender using a preset protocol, further includes:

Parsing the data packet to obtain the frame sequence number;

The frame sequence numbers of all currently received data packets are determined by using the frame sequence numbers to determine whether the data packets are lost.

Optionally, the FPGA communication data information is the sub-packet data that divides the original data into a preset number of packets;

The data packet also includes a sub-packet sequence number;

After the using the network interface to receive the data packets encapsulated by the data sender using the preset protocol, the method further includes:

The packet sequence number is obtained by parsing the data packet, so as to use the packet sequence number to package the communication data.

To achieve the above purpose, the application also provides a processing system for FGPA communication data, including:

a data packet receiving module, configured to use a network interface to receive a data packet encapsulated by a data sender using a preset protocol, where the data packet includes a frame type and frame content, and the frame content includes FPGA communication data information;

a parsing module, configured to parse the data packet to obtain the frame type and the frame content;

A data processing module, configured to determine a data processing operation corresponding to the frame type, and perform the data processing operation on the FPGA communication data in the frame content.

To achieve the above purpose, the present application also provides a processing device for FGPA communication data, including:

memory for storing computer programs;

The processor is configured to implement the steps of the method for processing FGPA communication data according to any one of the above when executing the computer program.

It can be seen from the above solutions that a method for processing FGPA communication data provided by the present invention includes: using a network interface to receive a data packet encapsulated by a data sender using a preset protocol, where the data packet includes a frame type and frame content, and the frame The content includes FPGA communication data information; parse the data packet to obtain the frame type and the frame content; determine the data processing operation corresponding to the frame type, and perform the data processing on the FPGA communication data in the frame content operate.

It can be seen that, in a method for processing FGPA communication data provided by the present application, after the data packet is encapsulated by the preset protocol, the data packet can be received through the network interface, and the frame type and frame content are defined in the preset protocol. After receiving the data packet, parse the data packet according to the preset protocol, determine the frame type and frame content, and perform corresponding operations on the data in the frame content according to the frame type. Therefore, this solution can transmit FPGA data through the network instead of PCIE transmission data, so that FPGA Heterogeneous accelerator cards can not be installed in the PCIE slot, thus avoiding the dependence on the server CPU, and can receive and process data independently, reducing the dependence of the FPGA communication data processing process on the server CPU, and improving the data processing efficiency. The present application also provides a system, device and computer-readable storage medium for processing FGPA communication data, which can also achieve the above effects.

Description of drawings

In order to explain the embodiments of the present invention or the technical solutions in the prior art more clearly, the following briefly introduces the accompanying drawings that need to be used in the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description are only These are some embodiments of the present invention. For those of ordinary skill in the art, other drawings can also be obtained according to these drawings without creative efforts.

1 is a flowchart of a method for processing FGPA communication data disclosed in an embodiment of the present invention;

2 is a flowchart of a specific method for processing FGPA communication data disclosed in an embodiment of the present invention;

3 is a flowchart of a specific FGPA communication data processing method disclosed in an embodiment of the present invention;

FIG. 4 is a schematic structural diagram of a system for processing FGPA communication data disclosed in an embodiment of the present invention.

Detailed ways

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, but not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

The embodiments of the present invention disclose a method, system and device for processing FGPA communication data, so as to reduce the expansion cost of the FPGA heterogeneous acceleration card.

Referring to FIG. 1, a method for processing FGPA communication data provided by an embodiment of the present invention specifically includes:

S101 , using a network interface to receive a data packet encapsulated by a data sender using a preset protocol, where the data packet includes a frame type and frame content, and the frame content includes FPGA communication data information.

Different from the prior art, in this solution, the FPGA board no longer only receives data through the PCIE interface, but can receive data packets through the network interface.

Specifically, a network interface is used to receive a data packet, where the data packet is a data packet encapsulated by the data sender using a preset encapsulation protocol. It should be noted that since the data transmission mode is changed, the encapsulation mode of the data packet also needs to be adjusted in this solution, so that the data can be transmitted in the network and can be identified and processed by both communicating parties. This solution uses the preset protocol to encapsulate the FPGA communication data information, so as to realize the transmission of FPGA communication data through the network.

In this solution, the content of the preset protocol at least includes frame type and frame content. The frame type is used to set the processing operation type of the FPGA communication data, the frame content includes the FPGA communication data information, and the FPGA communication data information is the operation content corresponding to the processing operation type. For example, the frame type is data transfer, and the FPGA communication data information Communication data for the FPGA to be moved.

It should be noted that in this solution, the data sender can be either a CPU or an FPGA, and the data receiver can also be a CPU or an FPGA. When the data sender or data receiver is an FPGA, the opposite end can be either an FPGA or a CPU.

It should also be noted that data packets can be transmitted in the local area network or in the public network. When transmitting in the local area network, the data packets encapsulated by the preset protocol can be directly transmitted, and in the public network During transmission, data packets need to be encapsulated with a preset protocol based on the transport layer or MAC layer protocol. Taking the transport layer protocol UDP protocol as an example, the encapsulation results are shown in Table 1 below, where FCS is a frame check sequence.

Table 1

source address Destination address type IP header UDP header Packets encapsulated with preset protocols FCS

S102, parse the data packet to obtain the frame type and the frame content.

After receiving the data packet, the data packet needs to be parsed according to the preset protocol, so as to obtain the frame type and frame content therein.

S103: Determine a data processing operation corresponding to the frame type, and perform the data processing operation on the FPGA communication data in the frame content.

It should be noted that different frame types correspond to different data processing operations. After the frame type and frame content are parsed, the processing operation is determined according to the frame type, and the FPGA communication data in the real content is processed accordingly.

It can be seen that, in a method for processing FGPA communication data provided by the present application, after the data packet is encapsulated by the preset protocol, the data packet can be received through the network interface, and the frame type and frame content are defined in the preset protocol. After receiving the data packet, parse the data packet according to the preset protocol, determine the frame type and frame content, and perform corresponding operations on the data in the frame content according to the frame type. Therefore, this solution can transmit FPGA data through the network instead of PCIE transmission data, so that FPGA Heterogeneous accelerator cards can not be installed in the PCIE slot, thus avoiding dependence on the server, and can receive and process data independently, reduce the dependence of the FPGA communication data processing process on the server CPU, and improve the data processing efficiency.

The following describes different frame types and corresponding processing operations in a method for processing FGPA communication data provided by an embodiment of the present application.

The frame types may specifically include five types, namely, a data movement type, an RDMA (Remote Direct Memory Access, remote direct data access) type, a file programming type, an instruction type, and a reply type.

Referring to Table 2, each frame type is described with specific examples in Table 2, wherein the encoding can be adjusted according to the actual situation, which is not limited in this solution. In this example, X is a variable, which can be modified according to different types. For example, for the data movement type 0x0X01, when the data movement operation is specifically moved from the HOST to the FPGA, then X is 0, that is, it is encoded as 0x0101. HOST is the server host side, and FPGA is the FPGA heterogeneous acceleration card side.

In this table, there are three types of data transfer types and RDMA types, each of which represents a different data transfer direction; the file programming type includes two programming methods, namely, programming Bit files to FPGA and programming Bit files to FLASH file; the instruction type includes several kinds of instructions. The specific content of the instruction is not introduced one by one in this solution, and can be selected and set according to the actual situation, such as remote update program instruction, temperature reading instruction, etc.; The frame type in the above 4 corresponds to the operation type that replies to the processing result of the frame type in the above 4.

The codes reserved in this table are codes that are not used for the time being, and can be defined according to actual needs.

Table 2

In a specific embodiment, the frame type includes a data transfer type, and the FPGA communication data information is FPGA communication data;

Correspondingly, the processing of the FPGA communication data in the frame content according to the frame type includes:

The FPGA communication data in the frame content is moved according to the frame type.

In this solution, if the frame type is the data movement type, the corresponding frame content includes the FPGA communication data, that is, the data to be moved. That is to say, if the frame type is the data movement type, the actual data to be moved needs to be Save the data packet and send it to the data receiver. After the data receiver receives the data packet and parses that the frame type is the data movement type, it will obtain the FPGA communication data to be moved from the frame content and move it. to the local destination address. It should be noted that the target address can also be set by data transmission, and is defined in the data packet by using a preset protocol.

In a specific embodiment, the frame type includes an RDMA type, and the FPGA communication data information includes a source address storing the FPGA communication data, a data length of the FPGA communication data, and a destination address storing the FPGA communication data;

Correspondingly, the processing of the FPGA communication data in the frame content according to the frame type includes:

Moving the FPGA communication data of the data length to the destination address to the source address.

In this solution, the frame type is RDMA type. In this type, the data receiver needs to take the initiative to find the data to be moved and move it to the source address of the data to be moved. Therefore, in this solution, when the frame type is RDMA type, the FPGA communication data information is no longer the data to be moved, but the source address, destination address and data length of the data to be moved. When the analysis frame type is RDMA type, three parameters of source address, destination address and data length are determined in the FPGA communication data information, and the FPGA communication data to be moved is actively obtained from the source address.

In a specific embodiment, the frame type includes an instruction type, the FPGA communication data information includes a read/write identifier, the number of commands, and the command information of the number of commands, and each of the command information includes an FPGA register address and data to be written or empty data corresponding to the FPGA register address;

Correspondingly, the processing of the FPGA communication data in the frame content according to the frame type includes:

According to the read and write identifiers, a register write or register read operation is sequentially performed on the FPGA register address in each command message.

In this solution, the frame type is the instruction type. For the instruction type, the corresponding FPGA communication data information is at least one command information. It should be noted that in the FPGA, different registers correspond to different functions. For example, a register is Authorization management register, when the register is written to 1, the current user is granted a certain authority, and when the register is written to 0, the current user's authority is cancelled. In this solution, the command is specifically in the form of reading or writing a register, and the register command information includes the FPGA register address and data to be written or empty data. It should be noted that if the register is written, a data field in the FPGA communication data information includes the value to be written into the register. If the register is read, the data field in the FPGA communication data information is a reserved field. Field is not filled with any data.

See Table 3. Table 3 shows the specific content of the FPGA communication data information when the frame type is an instruction type. Among them, this solution can transmit multiple commands at a time, the number of commands field is filled with the specific number of commands, the message body is the command information of the number of commands, and each command information includes the FPGA register address, data field (Data) and a reserved text.

table 3

In a specific embodiment, the frame type includes a reply type, and the FPGA communication data information includes a reply identifier;

Correspondingly, the processing of the FPGA communication data in the frame content according to the frame type includes:

The processing result of the FPGA communication data is determined by using the reply identifier.

In this solution, the reply type corresponds to the above frame type, and is used to identify the operation processing result of the above frame type. There are 4 types of reply types, namely data transfer reply, RDMA reply, Bit file programming reply, command reply, and reply type.

See Table 4 to Table 7 for the specific content of the FPGA communication data information corresponding to the four reply types. In the data packet header, the type of reply may be specifically included, that is, to identify which operation is to be replied to, so that after receiving the FPGA communication data information, the type of reply can be directly determined from the data packet header.

Table 4

table 5

Table 6

Table 7

A specific method for processing FGPA communication data provided by an embodiment of the present application is introduced below, and a specific method for processing FGPA communication data described below can be referred to each other with any of the above-mentioned embodiments.

Referring to FIG. 2 , a specific method for processing FGPA communication data provided by an embodiment of the present application specifically includes:

S201, using a network interface to receive a data packet encapsulated by a data sender using a preset protocol, where the data packet includes a frame type and frame content, and the frame content includes FPGA communication data information.

S202, parsing the data packet to obtain a frame sequence number.

In this solution, the data packet also includes a frame sequence number, which is used to identify each data packet. For example, if data transmission needs to send 5 data packets, the 5 sequence numbers can be used to identify each data packet respectively.

S203: Determine whether there is a missing data packet by using the frame sequence number to determine and the frame sequence numbers of all currently received data packets.

After the data packet is received, the frame sequence number in it is obtained by parsing, so that the frame sequence number can be used to determine whether there is an unreceived data packet, that is, it can be determined whether there is a packet loss.

S204, parse the data packet to obtain the frame type and the frame content.

S205: Process the FPGA communication data in the frame content according to the frame type.

It can be seen that, by adding the frame sequence number to the data packet in the embodiment of the present application, after receiving the data packet, the frame sequence number in the data packet can be parsed, and the frame sequence number can be used to determine whether the problem of packet loss occurs. information to determine lost packets.

A specific method for processing FGPA communication data provided by an embodiment of the present application is introduced below, and a specific method for processing FGPA communication data described below can be referred to each other with any of the above-mentioned embodiments.

Referring to FIG. 3 , a specific method for processing FGPA communication data provided by an embodiment of the present application specifically includes:

A specific method for processing FGPA communication data provided by an embodiment of the present application is introduced below, and a specific method for processing FGPA communication data described below can be referred to each other with any of the above-mentioned embodiments.

Referring to FIG. 3 , a specific method for processing FGPA communication data provided by an embodiment of the present application specifically includes:

S301 , using a network interface to receive a data packet encapsulated by a data sender using a preset protocol, where the data packet includes a frame type and frame content, and the frame content includes FPGA communication data information.

S302, parse the data packet to obtain the sub-packet sequence number, so as to use the sub-packet sequence number to package the communication data.

It should be noted that when the amount of FPGA communication data to be transmitted is large, the time delay for transmitting the FPGA communication data at one time is relatively large, which affects the quality of data transmission. To this end, in this solution, the FPGA communication data is sub-packaged, that is, the big data is divided into multiple small data, each small data is a sub-package data, and a sub-package sequence number is determined for each sub-package data, which is used to identify the sub-package data. package data. After receiving the data packet, the data receiver parses the data packet to obtain the sub-packet sequence number. After receiving all the data packets corresponding to a data, the sub-package data can be packaged according to the sub-packet sequence number to obtain a complete package. FPGA communication data.

S303, parse the data packet to obtain the frame type and the frame content.

S304, process the FPGA communication data in the frame content according to the frame type.

It can be seen that the method for processing FGPA communication data provided by the embodiment of the present application can reduce the data amount of each data transmission by subcontracting, so as to avoid excessive data affecting the quality of data transmission. The way of encapsulating the sub-package sequence number in the middle can enable the data receiver to package the data through the sub-package sequence number to obtain the complete FPGA communication data.

The following describes a system for processing FGPA communication data provided by an embodiment of the present application, and a system for processing FGPA communication data described below may refer to any of the above-mentioned embodiments.

Referring to FIG. 4 , a system for processing FGPA communication data provided by an embodiment of the present application specifically includes:

A data packet receiving module 401, configured to receive a data packet encapsulated by a data sender using a preset protocol by using a network interface, the data packet includes a frame type and frame content, and the frame content includes FPGA communication data information;

A parsing module 402, configured to parse the data packet to obtain the frame type and the frame content;

The data processing module 403 is configured to determine the data processing operation corresponding to the frame type, and perform the data processing operation on the FPGA communication data in the frame content.

The system for processing FGPA communication data in this embodiment is used to implement the aforementioned method for processing FGPA communication data. Therefore, the specific implementation in the system for processing FGPA communication data can be found in the embodiment section of the foregoing method for processing FGPA communication data, for example, , the data packet receiving module 401, the parsing module 402, and the data processing module 403 are respectively used to realize the steps S101, S102, and S103 in the above-mentioned FGPA communication data processing method. Therefore, the specific implementation can refer to the corresponding parts of the embodiments. description, which will not be repeated here.

The application also provides a processing device for FGPA communication data, including:

memory for storing computer programs;

The processor, configured to execute the computer program, can implement the steps provided in any of the foregoing embodiments of the method for processing FGPA communication data.

The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments, and the same and similar parts between the various embodiments can be referred to each other.

The above description of the disclosed embodiments enables any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims (10)

1. A method for processing FGPA communication data, comprising:

receiving a data packet encapsulated by a data sender by using a preset protocol by using a network interface; the data packet comprises a frame type and frame contents, and the frame contents comprise FPGA communication data information;

analyzing the data packet to obtain the frame type and the frame content;

and determining data processing operation corresponding to the frame type, and executing the data processing operation on the FPGA communication data in the frame content.

2. The method of claim 1, wherein when the frame type comprises a data movement type, performing the data processing operation on the FPGA communication data in the frame content comprises:

and moving the FPGA communication data in the frame content according to the frame type.

3. The method of claim 1, wherein the frame type comprises an RDMA type, wherein the FPGA communication data information comprises a source address where FPGA communication data is stored, a data length of the FPGA communication data, and a destination address where the FPGA communication data is stored;

correspondingly, the data processing operation is performed on the FPGA communication data in the frame content, and includes:

and moving the FPGA communication data with the data length to the source address to the destination address.

4. The method according to claim 1, wherein the frame type comprises a file programming type, and the FPGA communication data information comprises file contents to be programmed;

correspondingly, the data processing operation is performed on the FPGA communication data in the frame content, and includes:

and programming the content of the file to be programmed to the FPGA.

5. The method according to claim 1, wherein the frame type includes an instruction type, the FPGA communication data information includes a read-write identifier, command number and command information of the command number, and each command information includes an FPGA register address and data to be written or null data corresponding to the FPGA register address;

correspondingly, the data processing operation is performed on the FPGA communication data in the frame content, and includes:

and sequentially executing register writing or register reading operation on the FPGA register address in each command message according to the read-write identification.

6. The method of claim 1, wherein the frame type comprises a reply type, and wherein the FPGA communication data information comprises a reply identification;

correspondingly, the data processing operation is performed on the FPGA communication data in the frame content, and includes:

and determining the processing result of the FPGA communication data by using the reply identifier.

7. The method according to claim 1, wherein the data packet further includes a frame sequence number, and after receiving, by the network interface, the data packet encapsulated by the data sender using the predetermined protocol, the method further includes:

analyzing the data packet to obtain the frame sequence number;

and determining whether the data packet is lost or not by using the frame sequence numbers and the frame sequence numbers of all the currently received data packets.

8. The method according to claim 1, wherein the FPGA communication data message is packetized data dividing original data into a preset number of packets;

the data packet also comprises a packet sequence number;

after receiving the data packet encapsulated by the data sender by using the preset protocol by using the network interface, the method further comprises the following steps:

and analyzing the data packet to obtain the packet sequence number so as to package the communication data by using the packet sequence number.

9. A system for processing FGPA communication data, comprising:

the data packet receiving module is used for receiving a data packet which is encapsulated by a data sender by using a preset protocol by using a network interface, wherein the data packet comprises a frame type and a frame content, and the frame content comprises FPGA communication data information;

the analysis module is used for analyzing the data packet to obtain the frame type and the frame content;

and the data processing module is used for determining the data processing operation corresponding to the frame type and executing the data processing operation on the FPGA communication data in the frame content.

10. An apparatus for processing FGPA communication data, comprising:

a memory for storing a computer program;

a processor for implementing the steps of the method of processing FGPA communication data according to any of claims 1 to 8 when executing the computer program.

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