CN111293138A - Three-dimensional MRAM storage structure and fabrication method thereof - Google Patents

Abstract

The invention provides a three-dimensional MRAM memory structure and a manufacturing method thereof, wherein the structure comprises: the first storage layer comprises a CMOS circuit substrate, a magnetic tunneling junction device, a source line metal layer, a word line metal layer and a bit line metal layer; the first connection circuit layer is used for providing read-write signals of the storage layers and providing a signal connection path between two adjacent storage layers; a plurality of second memory layers directly formed on the first connection circuit layers, and a plurality of second connection circuit layers between the adjacent second memory layers. Compared with the traditional process, the invention does not need the steps of single-layer chip flow, grinding and thinning, alignment welding and the like in a Through Silicon Via (TSV) process, directly prepares the multilayer memory circuit on the same substrate through orderly stacking of semiconductor materials and metal wiring layers, and has the manufacturing process compatible with a CMOS process.

Description

Three-dimensional MRAM storage structure and fabrication method thereof

technical field

The invention belongs to the field of semiconductor integrated circuit design and manufacture, and in particular relates to a three-dimensional MRAM storage structure and a manufacturing method thereof.

Background technique

As the use of portable computing devices and wireless communication devices increases, memory devices may require higher density, lower power consumption, and/or non-volatility. The magnetic memory device may be able to meet the above-mentioned technical requirements.

Many electronic devices contain electronic memory. Electronic storage can be volatile or non-volatile. Non-volatile memory can store data when power is lost, whereas volatile memory cannot store data when power is lost. Magnetoresistive random access memory (MRAM) is a promising candidate for the next generation of electronic memory due to its advantages over current electronic memory. MRAM is generally faster and has better endurance than current non-volatile memories such as flash random access memory. Compared to current volatile memories such as dynamic random access memory (DRAM) and static random access memory (SRAM), MRAM typically has similar performance and density, but MRAM has lower power consumption. Since MTJ devices have high operating speed and low power consumption and are used to replace capacitors of DRAMs, MTJ devices can be applied to image devices and mobile devices having low power consumption and high speed.

The magnetoresistive device has low resistance when the spin directions (ie, the directions of the magnetic fluxes) of the two magnetic layers are the same as each other, and has high resistance when the spin directions are opposite to each other. In this way, bit data can be written into a magnetoresistive memory device using a change in cell resistance that is dependent on the magnetization state of the magnetic layer. A magnetoresistive memory having an MTJ structure will be described by way of example. In an MTJ memory cell having a structure composed of a ferromagnetic layer/insulating layer/ferromagnetic layer, when electrons passing through the first ferromagnetic layer pass through the insulating layer serving as a tunneling barrier, tunneling The penetration probability varies depending on the magnetization direction of the second ferromagnetic layer. That is, when the magnetization directions of the two ferromagnetic layers are parallel, the tunneling current is maximized, and when they are antiparallel, the tunneling current is minimized. For example, it can be considered that when the resistance is high, data "1" is written, and when the resistance is low, data "0" is written. When current flows through the magnetic layer, the current will be polarized, forming a spin-polarized current. The spin electron transfers the spin momentum to the magnetic moment of the free magnetic layer, so that the magnetic moment of the spin magnetic layer changes direction after acquiring the spin momentum. This process is called spin transfer torque. The current realizes the writing of information.

The core of the STT-MRAM memory cell is still an MTJ, which consists of two ferromagnetic layers of different thicknesses and a non-magnetic isolation layer several nanometers thick. With external circuitry, current can flow through the MTJ in a direction perpendicular to the MJT surface. When an electric current passes through a thicker ferromagnetic layer (called a pinned magnetic layer), the electrons are spin-polarized in the direction of the magnetic moment of the pinned magnetic layer. If the thickness of the intermediate nonmagnetic spacer is small enough to ensure a high degree of polarization, the spin-polarized electrons are able to transfer their spin angular momentum to the thinner ferromagnetic layer (called the free magnetic layer), changing the free magnetic The magnetization equilibrium state of the layer. The fixed magnetic layer that plays the role of "polarization layer" is generally thick (tens of nanometers), its saturation magnetization is very large, and its equilibrium state will not change. On the contrary, the free magnetic layer to be affected by the spin moment effect is generally very thin, and its saturation magnetization is small, so its magnetic moment vector can freely change its orientation according to the polarization direction of the spin electrons in the spin current. The structure of the STT-MRAM memory cell is simple, it omits the additional write information line with a magnetic shell, minimizes the preparation process, and reduces the cross-sectional area of the memory cell, high storage density, and fast storage speed. Design requirements for high performance computer systems.

As Moore's Law comes to an end, it becomes increasingly difficult to increase the storage density of memory chips through device scaling. All MRAM memory chips currently put into production are single-layer memory chips. Through the effective stacking of multi-layer memory circuits, the memory density of the chip can be significantly improved and the application scope of the MRAM memory chip can be expanded.

Most of the proposed 3D stacking technologies are accomplished through TSV (Through Silicon Via) technology. In this technical solution, the stacked memory layer substrate needs to be thinned from the back to less than 100um, which is difficult to process; the TSV through hole occupies a large area, which limits the storage bit density; each layer of memory chips needs to be soldered when soldering. Pad and ensure precise soldering, which limits process yield; interconnect lines between memory layers are long, increasing parasitic capacitance/inductance.

SUMMARY OF THE INVENTION

In view of the above-mentioned shortcomings of the prior art, the purpose of the present invention is to provide a three-dimensional MRAM storage structure and a manufacturing method thereof, which are used to solve the problem that in the prior art, 3D stacking needs to be realized through silicon vias, which is difficult and restricts the process. The problem of storage bit density.

In order to achieve the above object and other related objects, the present invention provides a method for fabricating a three-dimensional MRAM storage structure. The fabrication method includes the steps of: 1) providing a CMOS circuit substrate, and forming a magnetic tunnel junction device on the CMOS circuit substrate , the first end of the magnetic tunnel junction device is connected to the drain of the MOS transistor of the CMOS circuit substrate; 2) prepare a source line metal layer, a word line metal layer and a bit line metal layer, the source line metal layer , The word line metal layer and the bit line metal layer are separated by an interlayer dielectric layer, and the source line metal layer, the word line metal layer and the bit line metal layer are connected to the source electrode of the MOS transistor, the connecting the gate of the MOS transistor and the second end of the magnetic tunnel junction device to form a first storage layer; 3) preparing a first connection circuit layer on the first storage layer, the first connection circuit 4) A semiconductor material layer is formed on the first connection circuit layer, and a CMOS circuit is fabricated based on the semiconductor material layer layer and fabricate a magnetic tunnel junction device on the CMOS circuit layer, then repeat step 2) to form a second storage layer, and then repeat step 3) to form a second connection circuit layer on the second storage layer 5) Repeat step 4) multiple times to form a three-dimensional MRAM storage structure.

Preferably, the CMOS circuit substrate includes one of a CMOS circuit substrate based on an SOI substrate and a CMOS circuit substrate based on a flexible substrate.

Preferably, the flexible substrate comprises one of polydimethylsiloxane, polyimide, polyethylene, polypropylene, polyethylene terephthalate and polyethylene terephthalate kind.

Preferably, step 2) includes: 2-1) forming a first dielectric layer covering the CMOS circuit substrate and the magnetic tunnel junction device, and forming a first through hole in the first dielectric layer, and the first through hole is formed in the first dielectric layer. A hole is connected to the source of the MOS transistor, a first electrode layer is formed on the first dielectric layer and in the first through hole, and the first electrode layer is patterned to form the source line metal layer; 2-2) Form a second dielectric layer covering the source line metal layer, and form a second through hole in the second dielectric layer and the first dielectric layer, and the second through hole communicates with the MOS transistor , forming a second electrode layer on the second dielectric layer and in the second through hole, and patterning the second electrode layer to form the word line metal layer; 2-3) forming a cover a third dielectric layer of the word line metal layer, a third through hole is formed in the third dielectric layer, the second dielectric layer and the first dielectric layer, and the third through hole communicates with the magnetic tunnel At the second end of the through-junction device, a third electrode layer is formed on the third dielectric layer and in the third through hole, and the third electrode layer is patterned to form the bit line metal layer.

Preferably, step 4) adopts chemical vapor deposition method or atomic layer deposition method to form a semiconductor material layer on the first connection circuit layer, and the material of the semiconductor material layer includes silicon, germanium, silicon germanium, silicon carbide and III- One of the Group V compounds.

Preferably, the magnetic tunnel junction device comprises a first metal connection layer, a first metal transition layer, a fixed magnetic layer, a tunneling layer, a free magnetic layer, a second metal transition layer and a second metal connection layer stacked in sequence, The first metal connection layer is connected to the drain of the MOS transistor of the CMOS circuit.

Preferably, the material of the fixed magnetic layer includes one of CoFeB, elemental ferromagnetic material and alloy ferromagnetic material, and the material of the free magnetic layer includes one of CoFeB, elemental ferromagnetic material and alloy ferromagnetic material .

Preferably, the tunneling layer is a two-dimensional insulating material layer with a single crystal structure, and the two-dimensional insulating material layer includes one of two-dimensional boron nitride, graphene fluoride and graphene oxide.

The present invention also provides a three-dimensional MRAM storage structure, comprising: a first storage layer including a CMOS circuit substrate, a magnetic tunnel junction device, a source line metal layer, a word line metal layer and a bit line metal layer, the magnetic tunnel junction The device is formed on the CMOS circuit substrate, the first end of the magnetic tunnel junction device is connected to the drain of the MOS transistor of the CMOS circuit substrate, the source line metal layer, the word line metal layer and the bit line metal layer The layers are separated by an interlayer dielectric layer, the source line metal layer, word line metal layer and bit line metal layer are respectively connected to the source of the MOS transistor, the gate of the MOS transistor and the The second end of the magnetic tunnel junction device is connected; the first connection circuit layer is formed on the first storage layer and used to provide read and write signals of the storage layer and to provide a signal connection path between two adjacent storage layers a plurality of second storage layers, the second storage layers include a CMOS circuit layer, a magnetic tunnel junction device, a source line metal layer, a word line metal layer and a bit line metal layer, the magnetic tunnel junction devices are located in the On the CMOS circuit layer, the first end of the magnetic tunnel junction device is connected to the drain of the MOS transistor of the CMOS circuit layer, and the source line metal layer, the word line metal layer and the bit line metal layer are connected by The interlayer dielectric layer is isolated, the source line metal layer, word line metal layer and bit line metal layer are respectively connected to the source of the MOS transistor, the gate of the MOS transistor and the magnetic tunnel junction device through through holes A plurality of second connection circuit layers are located between adjacent second storage layers to provide read and write signals of the storage layers and to provide signal connection paths between two adjacent storage layers.

Preferably, the CMOS circuit substrate includes one of a CMOS circuit substrate based on an SOI substrate and a CMOS circuit substrate based on a flexible substrate.

Preferably, the flexible substrate comprises one of polydimethylsiloxane, polyimide, polyethylene, polypropylene, polyethylene terephthalate and polyethylene terephthalate kind.

Preferably, the CMOS circuit layer is a CMOS circuit layer based on a semiconductor material layer, and the material of the semiconductor material layer includes one of silicon, germanium, silicon germanium, silicon carbide and III-V compounds.

Preferably, the magnetic tunnel junction device comprises a first metal connection layer, a first metal transition layer, a fixed magnetic layer, a tunneling layer, a free magnetic layer, a second metal transition layer and a second metal connection layer stacked in sequence, The first metal connection layer is connected to the drain of the MOS transistor of the CMOS circuit.

Preferably, the material of the fixed magnetic layer includes one of CoFeB, elemental ferromagnetic material and alloy ferromagnetic material, and the material of the free magnetic layer includes one of CoFeB, elemental ferromagnetic material and alloy ferromagnetic material .

Preferably, the tunneling layer is a two-dimensional insulating material layer with a single crystal structure, and the two-dimensional insulating material layer includes one of two-dimensional boron nitride, graphene fluoride and graphene oxide.

As mentioned above, the three-dimensional MRAM storage structure of the present invention and the manufacturing method thereof have the following beneficial effects:

Compared with the traditional process, the present invention does not require the steps of tape-out, grinding and thinning, and alignment welding of the single-layer chip in the TSV process, but directly passes the multi-layer storage circuit through the semiconductor material and the metal wiring layer. The ordered stack is fabricated on the same substrate, and its fabrication process is compatible with the CMOS process.

Description of drawings

1 to 14 are schematic structural diagrams showing the steps of the manufacturing method of the three-dimensional MRAM memory structure of the present invention.

Component label description

10 CMOS circuit substrate

101 CMOS circuit layer

102 Drain

103 Source

104 grid

201 The first metal connection layer

202 The first metal transition layer

203 Fixed magnetic layer

204 Tunneling layer

205 Free magnetic layer

206 The second metal transition layer

207 Second metal connection layer

208 dielectric layer

301 first dielectric layer

302 first through hole

303 Source line metal layer

304 Second dielectric layer

305 Second through hole

306 word line metal layer

307 Third dielectric layer

308 Third through hole

309-bit line metal layer

401 The first connection circuit layer

501 CMOS circuit layer

601 Second connection circuit layer

Detailed ways

The embodiments of the present invention are described below through specific specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

Please refer to Figure 1 to Figure 14. It should be noted that the diagrams provided in this embodiment are only to illustrate the basic concept of the present invention in a schematic way, so the diagrams only show the components related to the present invention rather than the number, shape and the number of components in the actual implementation. For dimension drawing, the type, quantity and proportion of each component can be changed at will in actual implementation, and the component layout may also be more complicated.

As shown in FIG. 1 to FIG. 14 , this embodiment provides a method for fabricating a three-dimensional MRAM storage structure, and the fabrication method includes the steps:

As shown in FIG. 1 to FIG. 2 , step 1) is first performed, a CMOS circuit substrate is provided, a magnetic tunnel junction device is formed on the CMOS circuit substrate, and the first end of the magnetic tunnel junction device is connected to the CMOS The drain 102 of the MOS transistor of the circuit substrate is connected.

The CMOS circuit substrate includes one of a CMOS circuit substrate based on an SOI substrate and a CMOS circuit substrate based on a flexible substrate.

In one embodiment, the CMOS circuit substrate 10 may include an SOI substrate-based CMOS circuit layer 102 and a planarized dielectric layer 208 covering the CMOS circuit layer 102 .

In another embodiment, the CMOS circuit substrate may also include a flexible substrate, a CMOS circuit layer on the flexible substrate, and a flexible dielectric layer covering the CMOS circuit layer, wherein the flexible dielectric layer The surface roughness is less than 0.2nm. For example, the flexible substrate includes one of polydimethylsiloxane, polyimide, polyethylene, polypropylene, polyethylene terephthalate, and polyethylene terephthalate . The present invention adopts a flexible substrate, the formed magnetic tunnel junction device is lighter and thinner than the magnetic tunnel junction device of the existing solid ferromagnetic material, the formed MRAM is suitable for the application of flexible circuit, and the macroscopic view of the flexible substrate is There is basically no requirement for the topography. For example, the flexible substrate can be a circle, an ellipse, a polygon or any other desired shape. The processing technology of the flexible substrate is relatively simple, compared with the existing solid ferromagnetic Magnetic tunnel junction devices of materials have greater advantages.

The magnetic tunnel junction device includes a first metal connection layer 201, a first metal transition layer 202, a fixed magnetic layer 203, a tunneling layer 204, a free magnetic layer 205, a second metal transition layer 206 and a second metal layer stacked in sequence A connection layer 207, the first metal connection layer 201 is connected to the drain 102 of the MOS transistor of the CMOS circuit.

The material of the first metal connection layer 201 may be one of W, Cu and Al.

The first metal connection layer 201 in this embodiment is formed on a flat flexible dielectric layer, and the first metal connection layer 201 can be planarized to obtain a first metal connection layer 201 with a flat surface, so as to improve the subsequent first metal connection layer 201 . The flatness of a metal transition layer 202 .

In one embodiment, the material of the fixed magnetic layer 203 includes one of CoFeB, elemental ferromagnetic material and alloy ferromagnetic material, and the material of the free magnetic layer 205 includes CoFeB, elemental ferromagnetic material and alloy ferromagnetic material. one of the materials.

In another embodiment, the fixed magnetic layer 203 may be a two-dimensional magnetic material, and the material of the fixed magnetic layer 203 includes one of CrGeTe ₃ and CrI ₃ . The fixed magnetic layer 203 of the present invention adopts a two-dimensional magnetic material. materials, and a relatively thin and light magnetic tunnel junction device can be obtained.

The free magnetic layer 205 may be a two-dimensional ferromagnetic material layer, and the material of the free magnetic layer 205 may be one of CrGeTe ₃ and CrI ₃ . The free magnetic layer 205 of the present invention is a two-dimensional ferromagnetic material layer with a relatively thin thickness, which can improve the magnetization orientation speed of the magnetic tunnel junction device on the one hand, and obtain a lighter and thinner magnetic tunnel junction device on the other hand.

The tunneling layer 204 is a two-dimensional insulating material layer with a single crystal structure. For example, the two-dimensional insulating material layer includes one of two-dimensional boron nitride, graphene fluoride and graphene oxide. The tunneling layer 204 in this embodiment is a two-dimensional insulating material layer with a very thin thickness, and the consistency of the tunneling layer 204 is very good, which can greatly improve the tunneling probability while ensuring the quality and function of the tunneling layer 204 .

As shown in FIGS. 3 to 11 , then step 2) is performed to prepare a source line metal layer 303 , a word line metal layer 306 and a bit line metal layer 309 . The source line metal layer 303 , the word line metal layer 306 and the bit line The metal layers 309 are separated by an interlayer dielectric layer. The source line metal layer 303 , the word line metal layer 306 and the bit line metal layer 309 are respectively connected to the source electrode 103 of the MOS transistor and the MOS transistor through through holes. The gate 104 and the second end of the magnetic tunnel junction device are connected to form a first storage layer. It should be noted that, in the memory chip, in addition to the memory cells, there are corresponding signal read-write circuits, such as comparators, amplifiers, etc., on the periphery of the memory cells, which are not shown in this embodiment.

Specifically, step 2) includes:

As shown in FIGS. 3 to 5 , step 2-1) is first performed to form a first dielectric layer 301 covering the CMOS circuit substrate and the magnetic tunnel junction device, and the first dielectric layer 301 may be silicon dioxide ( SiO ₂ ), silicon nitride (Si ₃ N ₄ ) or silicon oxynitride (SiO _x N _y ), etc., a first through hole 302 is formed in the first dielectric layer 301 by a photolithography process and an etching process. The first through hole 302 is connected to the source electrode 103 of the MOS transistor, and a first electrode layer is formed on the first dielectric layer 301 and in the first through hole 302, such as by using a metal deposition process, and patterning The first electrode layer is etched to form the source line metal layer 303 . Of course, the source line metal layer 303 can also be fabricated by a metal lift-off process. That is, a patterned photoresist is fabricated first, then a metal layer is deposited, and then the photoresist and the metal layer on the upper surface thereof are removed. Meanwhile, the following second dielectric layer 304 , word line metal layer 306 , third dielectric layer 307 , bit line metal layer 309 and the like can also be fabricated by the above-mentioned process.

As shown in FIG. 6 to FIG. 8 , then step 2-2) is performed to form a second dielectric layer 304 covering the source line metal layer 303 in the second dielectric layer 304 and the first dielectric layer 301 A second through hole 305 is formed, the second through hole 305 is connected to the gate 104 of the MOS transistor, a second electrode layer is formed on the second dielectric layer 304 and in the second through hole 305, and patterned The second electrode layer is annealed to form the word line metal layer 306 .

As shown in FIG. 9 to FIG. 11 , step 2-3) is performed next, and a third dielectric layer 307 covering the word line metal layer 306 is formed, and the third dielectric layer 307 , the second dielectric layer 304 and the A third through hole 308 is formed in the first dielectric layer 301, the third through hole 308 communicates with the second end of the magnetic tunnel junction device, on the third dielectric layer 307 and the third through hole A third electrode layer is formed in 308 , and the third electrode layer is patterned to form the bit line metal layer 309 .

As shown in FIG. 12 , step 3) is performed next, and a first connection circuit layer 401 is prepared on the first storage layer. The first connection circuit layer 401 is used to provide read and write signals of the storage layer and to provide adjacent Signal connection path between two storage layers.

As shown in FIG. 13 , step 4) is performed next, a semiconductor material layer is formed on the first connection circuit layer 401 , and then a CMOS circuit layer 501 is formed based on the semiconductor material layer and a magnetic field is formed on the CMOS circuit layer tunnel junction device, and then repeat step 2) to form a second storage layer, including:

First, a first dielectric layer 301 covering the CMOS circuit layer 501 and the magnetic tunnel junction device is formed. The first dielectric layer 301 may be silicon dioxide (SiO ₂ ), silicon nitride (Si ₃ N ₄ ) or Silicon oxynitride (SiO _x N _y ), etc., a first through hole 302 is formed in the first dielectric layer 301 by a photolithography process and an etching process, and the first through hole 302 is connected to the source of the MOS transistor 103. Form a first electrode layer on the first dielectric layer 301 and in the first through hole 302, such as by using a metal deposition process, and pattern-etch the first electrode layer to form the source line Metal layer 303 . Of course, the source line metal layer 303 can also be fabricated by a metal lift-off process. That is, a patterned photoresist is fabricated first, then a metal layer is deposited, and then the photoresist and the metal layer on the upper surface thereof are removed. Meanwhile, the following second dielectric layer 304 , word line metal layer 306 , third dielectric layer 307 , bit line metal layer 309 and the like can also be fabricated by the above-mentioned process.

Then, a second dielectric layer 304 covering the source line metal layer 303 is formed, and a second through hole 305 is formed in the second dielectric layer 304 and the first dielectric layer 301 , and the second through hole 305 communicates with each other. For the gate 104 of the MOS transistor, a second electrode layer is formed on the second dielectric layer 304 and in the second through hole 305, and the second electrode layer is patterned to form the word line metal layer 306.

Next, a third dielectric layer 307 covering the word line metal layer 306 is formed, and third through holes 308 are formed in the third dielectric layer 307 , the second dielectric layer 304 and the first dielectric layer 301 . The third through hole 308 is connected to the second end of the magnetic tunnel junction device, a third electrode layer is formed on the third dielectric layer 307 and in the third through hole 308, and the third electrode layer is patterned electrode layer to form the bit line metal layer 309 .

Next, step 3) is repeated to form a second connection circuit layer 601 on the second storage layer. The second connection circuit layer 601 is used to provide read and write signals of the storage layer, and to provide a signal connection path between two adjacent storage layers.

In one embodiment, a chemical vapor deposition method or an atomic layer deposition method can be used to form a semiconductor material layer on the first connection circuit layer 401, and the material of the semiconductor material layer includes silicon, germanium, silicon germanium, silicon carbide and One of the compounds of Group III-V.

In another embodiment, the semiconductor material layer is a two-dimensional semiconductor material layer, and the material of the two-dimensional semiconductor material layer may be, for example, MoS2, WS2, black phosphorus, etc., which may adopt chemical vapor deposition or atomic layer Preparation by deposition method, preferably atomic layer deposition method, in this example, a two-dimensional semiconductor material layer is used, so that the preparation process of the CMOS circuit layer 501 only needs to be performed at a temperature lower than 400-500° C. instead of 400-500° C. The high temperature treatment above 500° C. will not cause damage to the magnetic tunnel junction device structure that has been fabricated below, which greatly improves the performance stability of the magnetic tunnel junction device and improves the production yield.

As shown in FIG. 14 , step 5) is finally performed, and step 4) is repeated several times to form a three-dimensional MRAM storage structure, as shown in FIG. 14 .

As shown in FIG. 14 , this embodiment further provides a three-dimensional MRAM storage structure, including: a first storage layer, including a CMOS circuit substrate, a magnetic tunnel junction device, a source line metal layer 303 , a word line metal layer 306 and a bit line Metal layer 309, the magnetic tunnel junction device is formed on the CMOS circuit substrate, the first end of the magnetic tunnel junction device is connected to the drain 102 of the MOS transistor of the CMOS circuit substrate, and the source line The metal layer 303, the word line metal layer 306 and the bit line metal layer 309 are isolated by an interlayer dielectric layer. The source electrode 103 of the MOS transistor, the gate electrode 104 of the MOS transistor, and the second end of the magnetic tunnel junction device are connected; the first connection circuit layer 401 is formed on the first storage layer to provide read and write signals of the storage layer, and provide a signal connection path between two adjacent storage layers; a number of second storage layers, the second storage layers include a CMOS circuit layer 501, a magnetic tunnel junction device, and a source line metal layer 303 , the word line metal layer 306 and the bit line metal layer 309 , the magnetic tunnel junction device is located on the CMOS circuit layer 501 , the first end of the magnetic tunnel junction device is connected to the MOS of the CMOS circuit layer 501 The drain 102 of the tube is connected to each other. The source line metal layer 303, the word line metal layer 306 and the bit line metal layer 309 are isolated by an interlayer dielectric layer. The source line metal layer 303, the word line metal layer 306 and The bit line metal layer 309 is respectively connected with the source electrode 103 of the MOS transistor, the gate electrode 104 of the MOS transistor and the second end of the magnetic tunnel junction device through through holes; a plurality of second connection circuit layers 601, It is located between the adjacent second storage layers and is used to provide read and write signals of the storage layers, and to provide a signal connection path between two adjacent storage layers.

The CMOS circuit substrate includes one of a CMOS circuit substrate based on an SOI substrate and a CMOS circuit substrate based on a flexible substrate. For example, the flexible substrate includes one of polydimethylsiloxane, polyimide, polyethylene, polypropylene, polyethylene terephthalate, and polyethylene terephthalate .

In one embodiment, the CMOS circuit layer 501 is a CMOS circuit layer based on a semiconductor material layer, and the material of the semiconductor material layer includes one of silicon, germanium, silicon germanium, silicon carbide, and group III-V compounds.

In another embodiment, the semiconductor material layer is a two-dimensional semiconductor material layer, and the material of the two-dimensional semiconductor material layer may be, for example, MoS2, WS2, black phosphorus, etc., which may adopt chemical vapor deposition or atomic layer Preparation by deposition method, preferably atomic layer deposition method, in this example, a two-dimensional semiconductor material layer is used, so that the preparation process of the CMOS device layer only needs to be performed at a temperature lower than 400-500 ° C, instead of 400-500 ° C. The high temperature treatment above ℃ will not cause damage to the magnetic tunnel junction device structure that has been fabricated below, thus greatly improving the performance stability of the magnetic tunnel junction device and improving the production yield.

The magnetic tunnel junction device includes a first metal connection layer 201, a first metal transition layer 202, a fixed magnetic layer 203, a tunneling layer 204, a free magnetic layer 205, a second metal transition layer 206 and a second metal layer stacked in sequence A connection layer 207, the first metal connection layer 201 is connected to the drain 102 of the MOS transistor of the CMOS circuit.

The material of the fixed magnetic layer 203 includes one of CoFeB, elemental ferromagnetic material and alloy ferromagnetic material, and the material of the free magnetic layer 205 includes one of CoFeB, elemental ferromagnetic material and alloy ferromagnetic material.

The tunneling layer 204 is a two-dimensional insulating material layer with a single crystal structure, and the two-dimensional insulating material layer includes one of two-dimensional boron nitride, graphene fluoride and graphene oxide.

As mentioned above, the three-dimensional MRAM storage structure of the present invention and the manufacturing method thereof have the following beneficial effects:

Compared with the traditional process, the present invention does not require the steps of tape-out, grinding and thinning, and alignment welding of the single-layer chip in the TSV process, but directly passes the multi-layer storage circuit through the semiconductor material and the metal wiring layer. The ordered stack is fabricated on the same substrate, and its fabrication process is compatible with the CMOS process.

Therefore, the present invention effectively overcomes various shortcomings in the prior art and has high industrial utilization value.

The above-mentioned embodiments merely illustrate the principles and effects of the present invention, but are not intended to limit the present invention. Anyone skilled in the art can modify or change the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes made by those with ordinary knowledge in the technical field without departing from the spirit and technical idea disclosed in the present invention should still be covered by the claims of the present invention.

Claims (15)

1. a preparation method of three-dimensional MRAM storage structure, is characterized in that, described preparation method comprises the steps: 1) A CMOS circuit substrate is provided, a magnetic tunnel junction device is formed on the CMOS circuit substrate, and a first end of the magnetic tunnel junction device is connected to a drain of a MOS transistor of the CMOS circuit substrate; 2) Prepare a source line metal layer, a word line metal layer and a bit line metal layer. The source line metal layer, the word line metal layer and the bit line metal layer are isolated by an interlayer dielectric layer. The source line metal layer , The word line metal layer and the bit line metal layer are respectively connected with the source of the MOS transistor, the gate of the MOS transistor and the second end of the magnetic tunnel junction device through through holes to form a first storage layer ; 3) preparing a first connection circuit layer on the first storage layer, and the first connection circuit layer is used to provide the read and write signals of the storage layer, and to provide a signal connection path between two adjacent storage layers; 4) forming a semiconductor material layer on the first connecting circuit layer, fabricating a CMOS circuit layer based on the semiconductor material layer and fabricating a magnetic tunnel junction device on the CMOS circuit layer, and then repeating step 2) to form a first two storage layers, and then repeating step 3) to form a second connection circuit layer on the second storage layer; 5) Repeat step 4) multiple times to form a three-dimensional MRAM memory structure. 2 . The method for manufacturing a three-dimensional MRAM storage structure according to claim 1 , wherein the CMOS circuit substrate comprises one of a CMOS circuit substrate based on an SOI substrate and a CMOS circuit substrate based on a flexible substrate. 3 . 3 . The method for manufacturing a three-dimensional MRAM storage structure according to claim 2 , wherein the flexible substrate comprises polydimethylsiloxane, polyimide, polyethylene, polypropylene, and polyterephthalene. 4 . A kind of polyethylene terephthalate and polyethylene naphthalate. 4. the making method of three-dimensional MRAM storage structure according to claim 1, is characterized in that: step 2) comprises: 2-1) Form a first dielectric layer covering the CMOS circuit substrate and the magnetic tunnel junction device, and form a first through hole in the first dielectric layer, and the first through hole communicates with the source of the MOS transistor electrode, forming a first electrode layer on the first dielectric layer and in the first through hole, and patterning the first electrode layer to form the source line metal layer; 2-2) Form a second dielectric layer covering the source line metal layer, and form a second through hole in the second dielectric layer and the first dielectric layer, and the second through hole communicates with the MOS transistor forming a second electrode layer on the second dielectric layer and in the second through hole, and patterning the second electrode layer to form the word line metal layer; 2-3) forming a third dielectric layer covering the word line metal layer, forming third through holes in the third dielectric layer, the second dielectric layer and the first dielectric layer, the third through holes A hole is connected to the second end of the magnetic tunnel junction device, a third electrode layer is formed on the third dielectric layer and in the third through hole, and the third electrode layer is patterned to form the bit wire metal layer. 5. The method for making a three-dimensional MRAM storage structure according to claim 1, wherein in step 4) a semiconductor material layer is formed on the first connecting circuit layer by chemical vapor deposition or atomic layer deposition, and the The material of the semiconductor material layer includes one of silicon, germanium, silicon germanium, silicon carbide and III-V group compounds. 6 . The method for fabricating a three-dimensional MRAM storage structure according to claim 1 , wherein the magnetic tunnel junction device comprises a first metal connection layer, a first metal transition layer, a fixed magnetic layer, a tunneling layer, a free magnetic layer, a second metal transition layer and a second metal connection layer, the first metal connection layer is connected to the drain of the MOS transistor of the CMOS circuit. 7 . The method for manufacturing a three-dimensional MRAM storage structure according to claim 6 , wherein the material of the fixed magnetic layer comprises one of CoFeB, an elemental ferromagnetic material and an alloyed ferromagnetic material, and the free magnetic layer The material includes one of CoFeB, elemental ferromagnetic material and alloy ferromagnetic material. 8 . The method for fabricating a three-dimensional MRAM memory structure according to claim 6 , wherein the tunneling layer is a two-dimensional insulating material layer with a single crystal structure, and the two-dimensional insulating material layer comprises two-dimensional boron nitride. 9 . , one of fluorinated graphene and graphene oxide. 9. a three-dimensional MRAM storage structure, is characterized in that, comprises: The first storage layer includes a CMOS circuit substrate, a magnetic tunnel junction device, a source line metal layer, a word line metal layer and a bit line metal layer, the magnetic tunnel junction device is formed on the CMOS circuit substrate, and the magnetic tunnel junction device is formed on the CMOS circuit substrate. The first end of the tunnel junction device is connected to the drain of the MOS transistor of the CMOS circuit substrate. The source line metal layer, the word line metal layer and the bit line metal layer are isolated by an interlayer dielectric layer. The source line metal layer, the word line metal layer and the bit line metal layer are respectively connected with the source electrode of the MOS transistor, the gate electrode of the MOS transistor and the second end of the magnetic tunnel junction device through through holes; a first connection circuit layer, formed on the first storage layer, to provide read and write signals of the storage layer and to provide a signal connection path between two adjacent storage layers; a plurality of second storage layers, the second storage layers include a CMOS circuit layer, a magnetic tunnel junction device, a source line metal layer, a word line metal layer and a bit line metal layer, the magnetic tunnel junction device is located in the CMOS On the circuit layer, the first end of the magnetic tunnel junction device is connected to the drain of the MOS transistor of the CMOS circuit layer, and the source line metal layer, the word line metal layer and the bit line metal layer are connected by a layer The source line metal layer, the word line metal layer and the bit line metal layer are respectively connected to the source of the MOS transistor, the gate of the MOS transistor and the magnetic tunnel junction device through through holes. the second end is connected; A plurality of second connection circuit layers are located between adjacent second storage layers to provide read and write signals of the storage layers and to provide signal connection paths between two adjacent storage layers. 10 . The three-dimensional MRAM storage structure according to claim 9 , wherein the CMOS circuit substrate comprises one of a CMOS circuit substrate based on an SOI substrate and a CMOS circuit substrate based on a flexible substrate. 11 . 11. The three-dimensional MRAM memory structure of claim 10, wherein the flexible substrate comprises polydimethylsiloxane, polyimide, polyethylene, polypropylene, polyethylene terephthalate A kind of alcohol ester and polyethylene naphthalate. 12 . The three-dimensional MRAM storage structure according to claim 9 , wherein the CMOS circuit layer is a CMOS circuit layer based on a semiconductor material layer, and the material of the semiconductor material layer comprises silicon, germanium, silicon germanium, and silicon carbide. 13 . And one of the III-V compounds. 13 . The three-dimensional MRAM storage structure according to claim 9 , wherein the magnetic tunnel junction device comprises a first metal connection layer, a first metal transition layer, a fixed magnetic layer, a tunneling layer, a free a magnetic layer, a second metal transition layer and a second metal connection layer, the first metal connection layer is connected to the drain of the MOS transistor of the CMOS circuit. 14 . The three-dimensional MRAM storage structure according to claim 13 , wherein the material of the fixed magnetic layer comprises one of CoFeB, an elemental ferromagnetic material and an alloyed ferromagnetic material, and the material of the free magnetic layer comprises 14 . One of CoFeB, elemental ferromagnetic material and alloy ferromagnetic material. 15 . The three-dimensional MRAM storage structure according to claim 13 , wherein the tunneling layer is a two-dimensional insulating material layer with a single crystal structure, and the two-dimensional insulating material layer comprises two-dimensional boron nitride, fluorinated One of graphene and graphene oxide.

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