CN119341520A - A clock and data recovery circuit adaptive method and device - Google Patents
A clock and data recovery circuit adaptive method and device Download PDFInfo
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Classifications
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H21/00—Adaptive networks
- H03H21/0012—Digital adaptive filters
- H03H21/0043—Adaptive algorithms
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03G—CONTROL OF AMPLIFICATION
- H03G11/00—Limiting amplitude; Limiting rate of change of amplitude
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H21/00—Adaptive networks
- H03H21/0012—Digital adaptive filters
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H21/00—Adaptive networks
- H03H21/0012—Digital adaptive filters
- H03H21/0067—Means or methods for compensation of undesirable effects
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/093—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using special filtering or amplification characteristics in the loop
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/10—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range
- H03L7/107—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range using a variable transfer function for the loop, e.g. low pass filter having a variable bandwidth
- H03L7/1075—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range using a variable transfer function for the loop, e.g. low pass filter having a variable bandwidth by changing characteristics of the loop filter, e.g. changing the gain, changing the bandwidth
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Abstract
The invention discloses a self-adapting method and a device of a clock and data recovery circuit, which relate to the technical field of communication and comprise the following steps of judging phase deviation and frequency deviation between a sending clock and a receiving clock, transmitting a phase error signal to a loop filter, analyzing the frequency response of the loop filter, determining the range and the relative relation of parameter adjustment, calculating the statistical characteristic output by the loop filter in real time, judging the working state of the clock and data recovery circuit, realizing a state machine of the clock and data recovery circuit, and determining and adjusting the parameters and the output range of the loop filter according to the statistical characteristic output by the loop filter and based on the principle of threshold detection. According to the invention, the working states of the clock and data recovery circuit are monitored, the design parameters of the loop filter are adjusted in real time according to the state change, the frequency capturing range is ensured, the phase noise of the clock and data recovery circuit in a steady state is improved, and the stability of data acquisition is improved.
Description
Technical Field
The present invention relates to the field of communications technologies, and in particular, to a method and an apparatus for self-adapting a clock and data recovery circuit.
Background
Clock and data recovery circuit Clock and Data Recovery, abbreviated as CDR, is a core functional module of modern digital communication system and is widely used in various wireless and wired communication systems. The goal of the clock and data recovery circuit is to track the clock drift and a range of clock jitter at the transmitting end at the receiving end to ensure correct data sampling. The principle of CDR is that the data is sampled by using the multi-phase clock generated locally by the receiving end, the edge of the data bit is judged by the phase discriminator, the output of the phase discriminator is filtered and then controlled by the voltage-controlled oscillator or the phase interpolator to form a loop, and the edge alignment of the local sampling clock and the edge of the received data is adjusted, thereby realizing the recovery of the clock with the same frequency and the same phase as the data.
Among the many components used in clock and data recovery circuits, loop filters are the most important component because they determine the system transfer function and dynamic range, the bandwidth, type and order of the loop filter need to trade off the noise versus frequency capture range metrics, and system stability, and CDR loop filters need to provide sufficient bandwidth to achieve the same frequency, in-phase clock recovery when there is a large frequency offset between the transmit and receive clocks. On the other hand, after the clock and data recovery circuit enters a steady state, an excessively wide loop bandwidth can cause larger output phase noise, and the stability of data sampling is affected.
Disclosure of Invention
The present invention is directed to a method and apparatus for clock and data recovery circuit to solve the above-mentioned problems.
In order to achieve the above purpose, the invention provides a self-adaptive method of a clock and data recovery circuit, comprising the following steps:
Step S1, receiving data sent by a sending device through a sampler, and processing and transmitting data signals;
step S2, receiving the data signal transmitted by the sampler through the phase discriminator, judging the phase deviation and the frequency deviation between the transmitting clock and the receiving clock, and outputting the phase deviation and the frequency deviation as phase error signals ;
Step S3 by phase error signalTransmitting the signals to a loop filter to remove noise and interference signals, firstly analyzing the frequency response of the loop filter, and determining the range and the relative relation of parameter adjustment;
S4, calculating the statistical characteristics of Loop Filter output in real time, and judging the working state of the CDR;
Step S5, finally, a CDR state machine is realized, and how to adjust parameters and output ranges of the Loop Filter is determined according to statistical characteristics of the Loop Filter output and based on a principle of threshold detection;
And S6, the output signal of the loop filter enters a voltage-controlled oscillator to form a loop, and the edge alignment of the local sampling clock and the edge of the received data is adjusted, so that the recovery of the clock with the same frequency and the same phase as the data is realized.
Preferably, in the step S3, the loop filter ring-opening frequency response, taking a second-order loop filter as an example, is given by the formula:
;
Is known to be The system function of the CDR is:
;
the system function H (Z) has (N+1) poles, and a single zero In order to ensure the stability and causality of the system, the (n+1) poles of H (Z) are all required to be in a unit circle (|z|=1), the distribution of the poles and zero affects the frequency response of the system together, and given the system delay N, the system analysis determines K, K 1 and the adjustment range and relative relation of K 2, wherein K is the common gain of the CDR loop, K 1 and K 2 are the gains of the first-order and second-order integrators respectively, and the method of the system analysis is applicable to the second-order loop filter and the loop filter with any order.
Preferably, in step S4, the method is as followsThe operating state of the CDR can be divided into a capture phase and a tracking phase, where,To a large extent, at this timeAlong with itRapid changes, requiring H (Z) to provide sufficient bandwidth, increased K, and each order integrator gain (K 1,K2, …Kn) to ensure system stabilityFast followingIs a variation of (c).
Preferably, said step S4 is performed during a tracking phase,Jitter around 0 is generated, and CDR is avoidedAlong with itIs unnecessarily varied, it is necessary to reduce K, and the integrator gain of each stage (K 1,K2, …Kn).
Preferably, the CDR state machine in step S5 includes:
The common gain of the clock and the data recovery circuit and the gain of the loop filter integrator are both configurable in real time;
The output of the clock and data recovery circuit comprises a limiter, and the output amplitude of the limiter is configurable;
for the non-limited phase output and frequency output of the loop filter, their statistical properties, including but not limited to mean and variance, are calculated in real time.
Preferably, the CDR state machine in step S5 includes two important design parameters, acq_th and track_th, corresponding to the detection thresholds of CDR tending to capture state and CDR tending to track state, respectively, and the main task is to calculate the statistical characteristics of phase output and frequency output of the loop filter, and compare with the set thresholds acq_th and track_th.
Preferably, the CDR state machine further comprises:
The CDR state machine determines the moment and direction of adjusting K and the gains of the integrator of each step, when the CDR is in a capturing state, the K and the gains of the integrator of each step need to be kept high, and when the CDR state tends to be converged, the K and the gains of the integrator of each step can be gradually reduced;
the respective adjustment ranges and adjustment granularities of the given system delays N, K and the gains of the integrator of each order are determined by the stability analysis and the frequency response of the system function H (Z);
Whether increasing K and each order integrator gain or decreasing K and each order integrator gain, the value of each gain change cannot exceed a set threshold to smooth out the transient response caused by the gain change.
Preferably, the CDR state machine further comprises:
when the CDR tends to capture state, increasing K and the gains of the integrator of each step according to the granularity calculated in advance, and correspondingly adjusting output amplitude limiting, wherein the K and the gains of the integrator of each step are required to be in a preset range;
When the CDR tends to a tracking state, K and the gains of the integrator of each step are reduced according to the granularity calculated in advance, and output amplitude limiting is correspondingly adjusted, wherein the K and the gains of the integrator of each step are required to be in a preset range;
in the CDR state adjustment process, the detection thresholds acq _ th and track _ th are also adjusted based on the corresponding design granularity, respectively, such that when K, and the respective order integrator gains increase, AndThe detection thresholds acq _ th and track _ th based on both statistics increase as well, and as K, and the integrator gains of the respective stages decrease,AndThe detection thresholds acq_th and track_th based on the statistical characteristics of both are also reduced;
The state machine comprises a waiting state, wherein when the parameters of the CDR change, the state machine enters the waiting state, and unstable results caused by transient response are ignored.
An adaptive device of a clock and data recovery circuit, comprising:
the sampler is used for receiving the data sent by the sending device;
a phase detector connected to the sampler for determining a phase deviation and a frequency deviation between the transmit clock and the receive clock and outputting a phase error signal ;
The loop filter is connected with the phase discriminator and is used for adjusting the built-in gain and the output range of the loop filter in real time according to the working state of the CDR;
and the voltage-controlled oscillator is connected with the loop filter and the sampler.
Preferably, the loop filter includes:
A gain unit for adjusting the intensity of the phase detector output signal and adjusting the gain of the amplifier to match the state of the clock and data recovery circuit;
the delayer is used for adjusting the response time of the gain device;
the statistical characteristic analysis module is used for calculating the statistical characteristic output by the Loop Filter in real time and judging the working state of the CDR;
the CDR state machine is used for adjusting parameters and output ranges of the Loop Filter according to statistical characteristics of the Loop Filter output and based on a principle of threshold detection;
Limiter for dynamic range control, peak protection and noise cancellation.
The invention has the technical effects and advantages that:
The invention utilizes the matched setting mode of the statistical characteristic of the Loop Filter output and the CDR state machine, determines the range and the relative relation of parameter adjustment by analyzing the frequency response of the Loop Filter, calculates the statistical characteristic of the Loop Filter output in real time for judging the working state of the CDR, realizes the CDR state machine, determines and adjusts the parameter and the output range of the Loop Filter according to the statistical characteristic of the Loop Filter output and based on the principle of threshold detection, achieves the aim of monitoring the working state of the CDR circuit, adjusts the design parameter of the Loop Filter in real time according to the state change, improves the phase noise under the CDR steady state while ensuring enough frequency capturing range, and improves the stability of data acquisition.
Drawings
FIG. 1 is a schematic diagram of the CDR adaptive filtering principle of the present invention.
FIG. 2 is a schematic diagram of a CDR state machine according to the present invention.
FIG. 3 is a schematic diagram of a CDR adaptive device according to the present invention.
Fig. 4 is a schematic diagram of a two-loop filter structure according to the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
The invention provides an adaptive method of a clock and data recovery circuit as shown in fig. 1-2, which comprises the following steps:
Step S1, receiving data sent by a sending device through a sampler, and processing and transmitting data signals;
step S2, receiving the data signal transmitted by the sampler through the phase discriminator, judging the phase deviation and the frequency deviation between the transmitting clock and the receiving clock, and outputting the phase deviation and the frequency deviation as phase error signals ;
Step S3 by phase error signalTransmitting the signals to a loop filter to remove noise and interference signals, firstly analyzing the frequency response of the loop filter, and determining the range and the relative relation of parameter adjustment;
S4, calculating the statistical characteristics of Loop Filter output in real time, and judging the working state of the CDR;
Step S5, finally, a CDR state machine is realized, and how to adjust parameters and output ranges of the Loop Filter is determined according to statistical characteristics of the Loop Filter output and based on a principle of threshold detection;
And S6, the output signal of the loop filter enters a voltage-controlled oscillator to form a loop, and the edge alignment of the local sampling clock and the edge of the received data is adjusted, so that the recovery of the clock with the same frequency and the same phase as the data is realized.
In step S3, taking the second-order loop filter as an example, the formula is:
;
Is known to be The system function of the CDR is:
;
the system function H (Z) has (N+1) poles, and a single zero . To ensure stability and causality of the system, the (n+1) poles of H (Z) need to be all within the unit circle (|z|=1), and the distribution of zeros and poles together affect the frequency response of the system. Given the system delay N, the system analysis determines K, K 1, and the adjustment range and relative relationship of K 2, Z/(Z-1) is the integrating circuit Z transform, and K 1 and K 2 are the gains of the first and second order integrators, respectively. It should be noted that a delay is inevitably introduced in the system implementation, so the delay logic Z -N must be included in the transfer function for the phase output and the frequency output, and the second order loop filter is the loop filter most commonly used in CDRs, but can be extended to any order of loop filter.
According to the following steps S4The operating state of the CDR can be divided into a capture phase and a tracking phase, where,To a large extent, at this timeAlong with itRapid changes, requiring H (Z) to provide sufficient bandwidth, increased and various integrator gains (K 1,K2, …Kn) to ensure system stabilityFast followingIs provided, during the tracking phase,Jitter around 0 is generated, and CDR is avoidedAlong with itUnnecessary variations in jitter, need to be reduced and the integrator gains of each order (K 1,K2, …Kn), when CDR is enabled, due to unknown frequency and phase offsets between transmit and receive clocks,And particularly when the frequency deviation is large,Oscillations may occur, withGradually lockingIn the course of the variation of (a),Gradually decreasing the absolute value of (a) to finally realize dynamic balance, at this time ≈,|I≡0, during the capture phase and tracking phase,There will be a difference in the range of values of (2), the former, the system design hopes to accelerateCan quickly catch up with the change of (a)Variations of (2) are not intended to limitIn the latter state, however, the system design wishes to avoid occasional abnormal events leading toSo that it is required toLimited in a certain range, the Loop Filter parameter is adaptively adjusted and simultaneously adjusted in real timeIs provided.
The CDR state machine in step S5 includes:
The common gain of the clock and the data recovery circuit and the gain of the loop filter integrator are both configurable in real time;
The output of the clock and data recovery circuit comprises a limiter, and the output amplitude of the limiter is configurable;
for the non-limited phase output and frequency output of the loop filter, their statistical properties, including but not limited to mean and variance, are calculated in real time.
In step S5, the CDR state machine comprises two important design parameters, namely acq_th and track_th, which correspond to detection thresholds of CDR tending to capture state and CDR tending to track state respectively, and mainly work is to calculate the statistical characteristics of phase output and frequency output of a loop filter and compare the statistical characteristics with set thresholds acq_th and track_th.
The CDR state machine further comprises:
The CDR state machine determines the moment and direction of adjusting K and the gains of the integrator of each step, when the CDR is in a capturing state, the K and the gains of the integrator of each step need to be kept high, and when the CDR state tends to be converged, the K and the gains of the integrator of each step can be gradually reduced;
the respective adjustment ranges and adjustment granularities of the given system delays N, K and the gains of the integrator of each order are determined by the stability analysis and the frequency response of the system function H (Z);
Whether increasing K and each order integrator gain or decreasing K and each order integrator gain, the value of each gain change cannot exceed a set threshold to smooth out the transient response caused by the gain change.
The CDR state machine further comprises:
when the CDR tends to capture state, increasing K and the gains of the integrator of each step according to the granularity calculated in advance, and correspondingly adjusting output amplitude limiting, wherein the K and the gains of the integrator of each step are required to be in a preset range;
When the CDR tends to a tracking state, K and the gains of the integrator of each step are reduced according to the granularity calculated in advance, and output amplitude limiting is correspondingly adjusted, wherein the K and the gains of the integrator of each step are required to be in a preset range;
in the CDR state adjustment process, the detection thresholds acq _ th and track _ th are also adjusted based on the corresponding design granularity, respectively, such that when K, and the respective order integrator gains increase, AndThe detection thresholds acq _ th and track _ th based on both statistics increase as well, and as K, and the integrator gains of the respective stages decrease,AndThe detection thresholds acq_th and track_th based on the statistical characteristics of both are also reduced;
The state machine comprises a waiting state, wherein when the parameters of the CDR change, the state machine enters the waiting state, and unstable results caused by transient response are ignored.
The invention provides a self-adaptive device of a clock and data recovery circuit as shown in figures 3-4, which comprises a sampler, a phase detector, a loop filter and a voltage-controlled oscillator, wherein the sampler is used for receiving data sent by a sending device, the phase detector is connected with the sampler, and is used for judging phase deviation and frequency deviation between a sending clock and a receiving clock and outputting a phase error signalThe loop filter is connected with the phase discriminator, the loop filter is used for adjusting the built-in gain and the output range of the loop filter in real time according to the working state of the CDR, the loop filter is composed of a first-order or multi-order integrator, the voltage-controlled oscillator is connected with the loop filter and the sampler, the phase discriminator can judge the phase deviation and the frequency deviation between the sending clock and the receiving clock based on the turnover characteristic of the digital signal after sampling, the receiving sampling clock is assumed to be unchanged and the influence of noise and a channel is eliminated, when the sending clock and the receiving clock are in the same frequency and different phase, the error signal is a constant which is not changed with time, when the frequency of the sending clock and the receiving clock are deviated,The change slope is normalized frequency deviation with time linear change, so theoretically, the receiving device can analyzeRecovering the ideal transmission clock but the transmission channel and analog front end result inIncluding significant linear and nonlinear disturbances, as well as noise, masks true phase and frequency deviations, soNoise and interference signals must be removed by the loop filter before it can be used for local clock reconstruction.
The Loop Filter comprises a gain device, a delay device, a statistical characteristic analysis module, a CDR state machine and a limiter, wherein the gain device is used for adjusting the intensity of an output signal of the phase discriminator and adjusting the gain of the amplifier to match the state of a clock and data recovery circuit, the delay device is used for adjusting the response time of the gain device, the statistical characteristic analysis module is used for calculating the statistical characteristic of the Loop Filter output in real time and judging the working state of the CDR, the CDR state machine is used for adjusting the parameter and the output range of the Loop Filter according to the statistical characteristic of the Loop Filter output and based on the principle of threshold detection, and the limiter is used for dynamic range control, peak protection and noise elimination.
The principle of the invention is as follows:
The frequency response of the Loop Filter is analyzed, the range and the relative relation of parameter adjustment are determined, the statistical characteristics of Loop Filter output are calculated in real time and are used for judging the working state of the CDR, a CDR state machine is realized, the parameter and the output range of the Loop Filter are determined to be adjusted according to the statistical characteristics of Loop Filter output and based on the principle of threshold detection, the purpose of monitoring the working state of the CDR circuit is achieved, the design parameters of the Loop Filter are adjusted in real time according to state change, the sufficient frequency capturing range is ensured, meanwhile, the phase noise in the stable state of the CDR is improved, and the stability of data acquisition is improved.
It should be noted that the foregoing description is only a preferred embodiment of the present invention, and although the present invention has been described in detail with reference to the foregoing embodiments, it should be understood that modifications, equivalents, improvements and modifications to the technical solution described in the foregoing embodiments may occur to those skilled in the art, and all modifications, equivalents, and improvements are intended to be included within the spirit and principle of the present invention.
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