CN118972039A - A hardware implementation circuit for SM3 algorithm - Google Patents
A hardware implementation circuit for SM3 algorithm Download PDFInfo
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- CN118972039A CN118972039A CN202411069896.9A CN202411069896A CN118972039A CN 118972039 A CN118972039 A CN 118972039A CN 202411069896 A CN202411069896 A CN 202411069896A CN 118972039 A CN118972039 A CN 118972039A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
- H04L9/06—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols the encryption apparatus using shift registers or memories for block-wise or stream coding, e.g. DES systems or RC4; Hash functions; Pseudorandom sequence generators
- H04L9/0618—Block ciphers, i.e. encrypting groups of characters of a plain text message using fixed encryption transformation
- H04L9/0631—Substitution permutation network [SPN], i.e. cipher composed of a number of stages or rounds each involving linear and nonlinear transformations, e.g. AES algorithms
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L2209/00—Additional information or applications relating to cryptographic mechanisms or cryptographic arrangements for secret or secure communication H04L9/00
- H04L2209/12—Details relating to cryptographic hardware or logic circuitry
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- Signal Processing (AREA)
- Compression, Expansion, Code Conversion, And Decoders (AREA)
Abstract
The application belongs to the field of SM3 algorithm hardware circuits, and relates to an SM3 algorithm hardware implementation circuit, which comprises: the message expansion circuit is used for receiving the input of the preset bit and carrying out iterative expansion on the input of the preset bit so as to obtain iterative expansion output; the compression circuit is used for receiving the iteration expansion output of the message expansion circuit and compressing the iteration expansion output; the compression circuit is connected with the message expansion circuit. The SM3 algorithm hardware implementation circuit provided by the application saves the use of an adder and an exclusive-OR gate, reduces the use of a compressor, saves related wiring resources and occupied areas, and simplifies the circuit design.
Description
Technical Field
The invention relates to the technical field of SM3 algorithm hardware circuits, in particular to an SM3 algorithm hardware implementation circuit.
Background
The rapid development of technologies such as cloud computing, artificial intelligence, internet of things and the like has put higher demands on data processing speed and data security in high-throughput data transmission.
At present, a domestic general method for realizing high-security data transmission is to adopt a security chip with a built-in cryptographic algorithm. The SM3 cryptographic hash algorithm is a cryptographic hash algorithm which is independently developed in China, and the core content of the cryptographic hash algorithm is that a message with the length of bits is subjected to filling expansion and iterative compression to generate a hash value with the length of 256 bits, and the cryptographic hash algorithm can be widely applied to the aspects of data integrity detection, digital signature verification, random number generation and the like.
The current research result has a complete SM3 algorithm hardware implementation circuit, which mainly comprises a message expansion circuit and a compression circuit. According to analysis, the circuit has remarkable effect on realizing high throughput of the SM3 algorithm circuit, but the circuit is complex in structure, more in used devices, higher in cost, slower in operation speed and lower in operation efficiency, so that improvement is needed.
Disclosure of Invention
In view of this, the present invention provides an SM3 algorithm hardware implementation circuit.
Specifically, the invention is realized by the following technical scheme:
According to a first aspect of the present invention, there is provided an SM3 algorithm hardware implementation circuit, comprising:
the message expansion circuit is used for receiving the input of the preset bit and carrying out iterative expansion on the input of the preset bit so as to obtain iterative expansion output;
The compression circuit is used for receiving the iteration expansion output of the message expansion circuit and compressing the iteration expansion output; the compression circuit is connected with the message expansion circuit.
Optionally, the message expansion circuit includes: the data processing device comprises a first input port, a second input port, a first data selector, a register, an exclusive-or and an output port, wherein the first data selector is respectively connected with the first input port, the second input port, the register and the exclusive-or, and the exclusive-or is connected with the output port.
Optionally, the message expansion circuit further comprises: the data processing device comprises a third input port, a fourth input port, a second data selector and a first expansion chip, wherein the fourth input port is connected with the first expansion chip, and the second data selector is respectively connected with the third input port, the first expansion chip, the register and the exclusive OR.
Optionally, the message expansion circuit further comprises: the data processing device comprises a fifth input port, a sixth input port, a third data selector and a second expansion chip, wherein the fifth input port is connected with the second expansion chip, and the third data selector is respectively connected with the fifth input port, the second expansion chip, the register and the exclusive OR.
Optionally, the compression circuit includes: the device comprises a first compression circuit and a second compression circuit, wherein the first compression circuit is connected with the second compression circuit.
Optionally, the first compression circuit includes: the device comprises a first compression input port, a second compression input port, a first compression data selector, a first adder compressor, a first compression register, a second compression register and a first compression output port, wherein the first compression input port is respectively connected with the first compression register and the first compression data selector, the first compression data selector is respectively connected with the second compression input port and the first adder compressor, and the second compression register is respectively connected with the first adder compressor, the first compression register and the first compression output port.
Optionally, the first compression circuit further includes: a third compressed input port, a fourth compressed input port, and a second compressed data selector, wherein the second compressed data selector is connected to the third compressed input port, the fourth compressed input port, and the first adder-compressor, respectively.
Optionally, the first compression circuit further includes: a fifth compressed input port, a sixth compressed input port, and a third compressed data selector, wherein the third compressed data selector is connected to the fifth compressed input port, the sixth compressed input port, and the first adder-compressor, respectively.
Optionally, the second compression circuit includes: the device comprises a first partial compression input port, a second partial compression input port, a first partial compression data selector, a second addition compressor, a first partial compression register and a first partial compression output port, wherein the first partial compression data selector is respectively connected with the first partial compression input port, the second partial compression input port and the second addition compressor, and the first partial compression register is respectively connected with the second addition compressor and the first partial compression output port.
Optionally, the second compression circuit further includes: the system comprises a third partial compression input port, a fourth partial compression input port and a second partial compression data selector, wherein the second partial compression data selector is respectively connected with the second addition compressor, the third partial compression input port and the fourth partial compression input port.
The technical scheme provided by the invention has at least the following beneficial effects:
The SM3 algorithm hardware implementation circuit provided by the application saves the use of an adder and an exclusive-OR gate, reduces the use of a compressor, saves related wiring resources and occupied areas, and simplifies the circuit design.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and together with the description, serve to explain the principles of the invention.
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings that are required to be used in the description of the embodiments or the related art will be briefly described below, and it will be apparent to those skilled in the art that other drawings can be obtained from these drawings without inventive effort.
Fig. 1 is a schematic diagram of a message expansion circuit in an SM3 algorithm hardware implementation circuit according to an embodiment of the present invention;
fig. 2 is a schematic diagram of a first compression circuit in an SM3 algorithm hardware implementation circuit according to an embodiment of the present invention;
fig. 3 is a schematic diagram of a second compression circuit in an SM3 algorithm hardware implementation circuit according to an embodiment of the present invention;
fig. 4 is a schematic diagram of an SM3 algorithm hardware implementation circuit according to an embodiment of the present invention.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments of the present invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Referring to fig. 1-4, the present application provides an SM3 algorithm hardware implementation circuit, comprising:
the message expansion circuit is used for receiving the input of the preset bit and carrying out iterative expansion on the input of the preset bit so as to obtain iterative expansion output;
The compression circuit is used for receiving the iteration expansion output of the message expansion circuit and compressing the iteration expansion output; the compression circuit is connected with the message expansion circuit.
In the embodiment of the application, the compression circuit receives the iteration expansion output of the message expansion circuit and compresses the iteration expansion output. In the message expansion circuit, the SM3 algorithm needs to provide 132 32-bit inputs, and the message originally only having 512 bits is subjected to 64 rounds of iterative expansion. Since the calculation mode is the same for every 32 inputs, only the flow chart of values obtained by performing iterative expansion is shown here. The circuit realizes that the original 16 messages with 32 bits respectively generate an extra 32-bit message by using 3 two-out data selectors and an adder. When the circuit actually operates, the sum value is calculated by only designing the value of the control (the value is controlled by an external time sequence circuit), and compared with the original wheel expansion circuit, the use of an exclusive OR gate circuit and related logic gate and wiring resources can be saved. In the compression circuit, 64 iterations (initial value is fixed value initial vector in first compression) are carried out by using 256-bit initial value, and each iteration receives the expansion message provided by the message expansion circuit to obtain 256-bit hash value. The compression circuit regards the 256-bit variables as 8 32-bit variables in turn, and one iteration compression will produce new 8 32-bit variables. Only the calculation of the values of E and A is needed in the circuit, and the other 6 variables are simply assigned or assigned after cyclic shift without any resource.
Illustratively, the message expansion circuit includes: the device comprises a first input port wi+7, a second input port wi+10, a first data selector, a register C0, an exclusive-OR and an output port Pi, wherein the first data selector is respectively connected with the first input port wi+7, the second input port wi+10, the register C0 and the exclusive-OR, and the exclusive-OR is connected with the output port Pi.
In the embodiment of the present application, the data of the first input port wi+7 and the second input port wi+10 are processed by the first data selector, the register C0 and the exclusive or and then output through the output port Pi.
Illustratively, the message expansion circuit further comprises: the device comprises a third input port Wi, a fourth input port wi+3, a second data selector and a first expansion chip, wherein the fourth input port wi+3 is connected with the first expansion chip, and the second data selector is respectively connected with the third input port Wi, the first expansion chip, the register C0 and the exclusive OR.
In the embodiment of the present application, after the data of the fourth input port wi+3 enters the first expansion chip, the data of the fourth input port Wi and the data of the third input port Wi enter the second data selector together.
Illustratively, the message expansion circuit further comprises: the device comprises a fifth input port wi+13, a sixth input port WP, a third data selector and a second expansion chip, wherein the fifth input port wi+13 is connected with the second expansion chip, and the third data selector is respectively connected with the fifth input port wi+13, the second expansion chip, the register C0 and the exclusive OR.
In the embodiment of the present application, after the data of the fifth input port wi+13 enters the second expansion chip, the data enters the third data selector together with the data of the sixth input port WP.
Illustratively, the compression circuit includes: the device comprises a first compression circuit and a second compression circuit, wherein the first compression circuit is connected with the second compression circuit.
In the embodiment of the application, the first compression circuit and the second compression circuit work together to iteratively expand the output of the received message expansion circuit and compress the output.
Illustratively, the first compression circuit includes: the first compression input port A < 12, the second compression input port H+Wj, the first compression data selector, the first adder compressor, the first compression register, the second compression register and the first compression output port En, wherein the first compression input port is respectively connected with the first compression register and the first compression data selector, the first compression data selector is respectively connected with the second compression input port and the first adder compressor, and the second compression register is respectively connected with the first adder compressor, the first compression register and the first compression output port En.
In the embodiment of the application, the input data of the first compression input port A < 12 and the second compression input port H+Wj are processed and then output by the first compression output port En.
Illustratively, the first compression circuit further comprises: a third compressed input port E, a fourth compressed input port GGj (E, F, G) and a second compressed data selector 3-2CSA, wherein the second compressed data selector is connected to the third compressed input port, the fourth compressed input port and the first adder-compressor, respectively.
In the embodiment of the present application, the data input by the third compressed input port E and the fourth compressed input port GGj (E, F, G) enter the second compressed data selector 3-2 CSA.
Illustratively, the first compression circuit further comprises: a fifth compressed input port Tj < j), a sixth compressed input port SS1, and a third compressed data selector, wherein the third compressed data selector is connected to the fifth compressed input port, the sixth compressed input port, and the first adder-compressor, respectively.
In the embodiment of the present application, the data input from the fifth compressed input port Tj < j and the sixth compressed input port SS1 enter the third compressed data selector.
Illustratively, the second compression circuit includes: the first partial compression input port H, the second partial compression input port Wj', the first partial compression data selector, the second addition compressor 4-2CSA, the first partial compression register and the first partial compression output port An, wherein the first partial compression data selector is respectively connected with the first partial compression input port, the second partial compression input port and the second addition compressor, and the first partial compression register is respectively connected with the second addition compressor and the first partial compression output port.
In the embodiment of the present application, the input data of the first compression input port H and the second compression input port Wj' are processed and then output by the first compression output port An.
Illustratively, the second compression circuit further comprises: the system comprises a third partial compression input port Wj, a fourth partial compression input port D and a second partial compression data selector, wherein the second partial compression data selector is respectively connected with the second addition compressor, the third partial compression input port and the fourth partial compression input port.
In the embodiment of the present application, the data input by the third compression input port Wj and the fourth compression input port D enter the second compression data selector.
The schematic diagrams of the compression circuit proposed by the patent are shown in fig. 2 and 3. The compression circuit is split into two independent circuit modules which are used for realizing and calculating the relevant intermediate value respectively. Intermediate values include the calculation of the sum. The main advantages are: firstly, through using 3-2 compressor, alternative data selector and 4-2 add compressor, through compressing 2 variables into 2 variables earlier and then adding, reduce the use of adder for the critical path reduces, has simplified circuit structure, has improved the functioning speed. And secondly, the sum is calculated by controlling three alternative data selectors, sharing the same 3-2 compressor and then carrying out addition operation. And the four input ends are formed by adding two 0s, so that the four input ends can be compressed by sharing a 4-2 addition compressor with the calculation of the A value, and the resource is greatly saved. The overall architecture of the resulting compression circuit is shown in fig. 4.
The SM3 algorithm hardware implementation circuit provided by the application saves the use of an adder and an exclusive-OR gate, reduces the use of a compressor, saves related wiring resources and occupied areas, and simplifies the circuit design.
In the present application, the terms "upper", "lower", "left", "right", "front", "rear", "top", "bottom", "inner", "outer", "vertical", "horizontal", "lateral", "longitudinal", and the like refer to the directions or positional relationships based on the directions or positional relationships shown in the drawings. These terms are only used to better describe the present application and its embodiments and are not intended to limit the scope of the indicated devices, elements or components to the particular orientations or to configure and operate in the particular orientations.
Also, some of the terms described above may be used to indicate other meanings in addition to orientation or positional relationships, for example, the term "upper" may also be used to indicate some sort of attachment or connection in some cases. The specific meaning of these terms in the present application will be understood by those of ordinary skill in the art according to the specific circumstances.
Furthermore, the terms "mounted," "configured," "provided," "connected," and "connected" are to be construed broadly. For example, it may be a fixed connection, a removable connection, or a unitary construction; may be a mechanical connection, or an electrical connection; may be directly connected, or indirectly connected through intervening media, or may be in internal communication between two devices, elements, or components. The specific meaning of the above terms in the present application can be understood by those of ordinary skill in the art according to the specific circumstances.
Furthermore, the terms "first," "second," and the like, are used primarily to distinguish between different devices, elements, or components (the particular species and configurations may be the same or different), and are not used to indicate or imply the relative importance and number of devices, elements, or components indicated. Unless otherwise indicated, the meaning of "a plurality" is two or more.
The foregoing is only a specific embodiment of the invention to enable those skilled in the art to understand or practice the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
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| CN202411069896.9A CN118972039A (en) | 2024-08-06 | 2024-08-06 | A hardware implementation circuit for SM3 algorithm |
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| CN202411069896.9A CN118972039A (en) | 2024-08-06 | 2024-08-06 | A hardware implementation circuit for SM3 algorithm |
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