CN116881188B - Method, equipment and medium for chip-to-chip interface interconnection - Google Patents

Abstract

This application provides a method, equipment and medium for chip-to-wafer interface interconnection. It can meet the needs of high data transmission rate and high data transmission reliability, and can also flexibly adapt to the requirements of various protocols, rules, strategies, etc. in terms of data transmission, flow control, scheduling functions, bandwidth, data channels, etc.

Description

Method, equipment and medium for chip-to-chip interface interconnection

Technical field

The present application relates to the field of chip design technology, and in particular to a method, equipment and medium for chip-to-wafer interface interconnection.

Background technique

With the advancement of semiconductor technology and the growth of chip design scale, the chip area is getting larger and larger. It becomes more difficult to improve the performance of system on chip (SOC), that is, system on chip, and it also faces leakage. Problems include increased current, increased difficulty in heat dissipation, and slow growth of the chip clock frequency. Breakthroughs in semiconductor processes also make it difficult for SOC to achieve optimal performance and extremely low power consumption, and it also faces rising chip manufacturing costs and declining manufacturing yields. In order to use existing process technology to manufacture chips with performance and power consumption that meet the requirements, the SOC is split into multiple wafers (die), and packaging and interconnection technologies are used to build chipsets or multi-chip modules. For example, through chiplet technology, each functional block originally integrated in the same system single chip is separated, manufactured separately, and finally integrated and packaged into a system chipset through packaging and interconnection technology. The data interconnection between multiple encapsulated chips must ensure accuracy, and the die-to-die interface interconnection also needs to have high data bandwidth, low latency and high reliability to meet the needs of networks, large-scale applications, etc. Application needs in fields such as large-scale data centers and artificial intelligence. However, the chip-to-chip interface interconnection method in the prior art is difficult to meet the requirements for high data transmission rate and high data transmission reliability.

To this end, this application provides a chip-to-wafer interface interconnection method, equipment and medium to solve technical problems in the existing technology.

Contents of the invention

In a first aspect, the present application provides a chip-to-wafer interface interconnection method. Each wafer of the plurality of wafers includes a wafer-to-wafer interface for data interconnection between the wafer and another wafer of the plurality of wafers relative to the wafer, the method is applied to a first wafer, the second wafer A wafer is any wafer among the plurality of wafers, the wafer-to-wafer interface of the first wafer includes an interface cache, a protocol processing unit and a transmission interface, and the method includes: in response to data transmission of the first wafer , input the first data to be sent to the interface cache; through the protocol processing unit, perform data cutting on the first data to be sent to obtain the cut data, and perform cyclic redundancy check calculation and generation on the cut data Cyclic redundancy calculation results, add the cyclic redundancy calculation results to the cut data to perform assembly and striping distribution to obtain the distributed data, perform encoding operations on the distributed data to obtain the encoded data, and The encoded data is scrambled and framed to obtain the second data to be sent; the second data to be sent is sent through the transmission interface, and in response to the data reception of the first chip, the second data to be sent is obtained through the transmission interface The first data to be received is; through the protocol processing unit, the first data to be received is framed and descrambled and then decoded to obtain decoded data, and the decoded data is subjected to data aggregation processing to obtain aggregated data. , perform cyclic redundancy check and data combination on the aggregated data to obtain the second data to be received; input the second data to be received into the interface cache.

Through the first aspect of this application, the requirements for high data transmission rate and high data transmission reliability can be met, and various protocols, rules, strategies, etc. can be flexibly adapted to such aspects as data transmission, flow control, scheduling functions, bandwidth, Requirements for data channels, etc.

In a possible implementation of the first aspect of the application, the encoding operation is based on a first encoding scheme, the decoding operation is based on a first decoding scheme, and the first encoding scheme corresponds to the first decoding scheme.

In a possible implementation of the first aspect of the present application, the first encoding scheme is 64/67 encoding, and the first decoding scheme is 64/67 decoding.

In a possible implementation of the first aspect of the application, the first data to be sent comes from a user data interface associated with the first chip, and the second data to be received is sent to the user Data interface.

In a possible implementation of the first aspect of the present application, the second data to be received undergoes rate adaptation processing before being sent to the user data interface.

In a possible implementation of the first aspect of the application, the second data to be sent is sent to a transmission interface of a wafer-to-wafer interface of a second wafer relative to the first wafer.

In a possible implementation of the first aspect of the present application, the protocol processing unit adds the cyclic redundancy calculation result to the cut data to perform assembly and striping distribution to obtain the The distributed data includes: adding the cyclic redundancy calculation result to the cut data through the protocol processing unit to assemble and stripe the distributed data according to the setting of the burst length to obtain the distributed data.

In a possible implementation of the first aspect of the application, the transmission interface is a serializer-deserializer interface.

In a possible implementation of the first aspect of this application, the protocol processing unit is an Interlaken protocol processing unit.

In a possible implementation of the first aspect of the present application, through the protocol processing unit, at least before performing data cutting on the first data to be sent to obtain the cut data, all the data in the interface cache are processed. The first data to be sent is subjected to rate adaptation processing.

In a possible implementation of the first aspect of the present application, through the protocol processing unit, the cyclic redundancy check calculation is performed on the cut data to generate the cyclic redundancy calculation result synchronously. The control field is used to record the description information of the cut data.

In a possible implementation of the first aspect of the application, the plurality of wafers are homogeneous wafers or heterogeneous wafers.

In a possible implementation of the first aspect of the application, the plurality of chips correspond to functional blocks in the same system single chip, and the plurality of chips are packaged together through respective chip-to-wafer interfaces to form a The system chipset corresponding to the system single chip.

In a possible implementation of the first aspect of the application, the plurality of wafers are packaged together using die technology.

In a possible implementation of the first aspect of the application, the encoding operation is based on a first encoding scheme, the encoded data includes a plurality of pre-compression data, and the sizes of the plurality of pre-compression data are all A numerical value of bits, the first numerical value is based on the first encoding scheme, wherein scrambling and framing the encoded data to obtain the second data to be sent includes: The pre-compression data is compressed and transcoded respectively to obtain a plurality of compressed data corresponding to the plurality of pre-compression data, and forward error correction calculation is performed on the plurality of pre-compression data to generate a redundant error correction code. The redundant error correction code is added to the plurality of compressed data to update the encoded data, and the updated encoded data is scrambled and framed to obtain the second data to be sent.

In a possible implementation of the first aspect of this application, the first encoding scheme is 64/67 encoding, and the first numerical value is 67.

In a possible implementation of the first aspect of the present application, the size of the encoded data before the update is consistent with the size of the encoded data after the update, and the plurality of compressed data correspond to The data field in the plurality of pre-compression data, the redundant error correction code generated by performing forward error correction calculation on the plurality of pre-compression data corresponds to the bit field used for synchronization in the plurality of pre-compression data. .

In a possible implementation of the first aspect of the present application, the decoding operation is based on a first decoding scheme, and the first encoding scheme corresponds to the first decoding scheme, wherein the decoded data is subjected to data processing. The aggregation process to obtain the aggregated data includes: decompressing and reverse transcoding the decoded data and then performing a forward error correction check, and then performing data aggregation processing to obtain the aggregated data.

In a possible implementation of the first aspect of the application, the plurality of pre-compression data are compressed and transcoded respectively to obtain the plurality of post-compression data corresponding to the plurality of pre-compression data, The method includes: compressing a bit field used for synchronization in the plurality of pre-compressed data to transmit the redundant error correction code, and maintaining a data field in the plurality of pre-compressed data.

In a possible implementation of the first aspect of the present application, the link transmission bandwidth of the transmission interface associated with the plurality of pre-compression data is equal to the link transmission bandwidth of the transmission interface associated with the plurality of post-compression data. The associated link transmission bandwidth.

In a possible implementation of the first aspect of the present application, the plurality of pre-compression data are compressed and transcoded respectively to obtain the plurality of post-compression data corresponding to the plurality of pre-compression data. Based on the first encoding scheme, the first encoding scheme is based on a die-to-die interface interconnect protocol associated with the protocol processing unit.

In a second aspect, embodiments of the present application also provide a computer device. The computer device includes a memory, a processor, and a computer program stored on the memory and executable on the processor. The processor executes The computer program implements a method according to any implementation of any of the above aspects.

In a third aspect, embodiments of the present application also provide a computer-readable storage medium that stores computer instructions. When the computer instructions are run on a computer device, the computer device causes the computer device to execute the above-mentioned method. Any method of achieving either aspect.

In a fourth aspect, embodiments of the present application further provide a computer program product. The computer program product includes instructions stored on a computer-readable storage medium. When the instructions are run on a computer device, the computer device executes A method according to any implementation of any of the above aspects.

Description of the drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed to be used in the description of the embodiments will be briefly introduced below. Obviously, the drawings in the following description are some embodiments of the present application, which are of great significance to this field. Ordinary technicians can also obtain other drawings based on these drawings without exerting creative work.

Figure 1 is a schematic diagram of a system chipset obtained by integrating multiple interconnected chips according to an embodiment of the present application;

Figure 2 is a schematic diagram of multiple chips interconnected through a chip-to-wafer interface according to an embodiment of the present application;

FIG. 3 is another schematic diagram of multiple chips interconnected through a chip-to-wafer interface according to an embodiment of the present application;

Figure 4 is a schematic flowchart of a chip-to-wafer interface interconnection method provided by an embodiment of the present application;

Figure 5 is a schematic flowchart of a data sending process based on a first encoding scheme through a chip-to-wafer interface according to an embodiment of the present application;

FIG. 6 is a schematic flowchart of a data receiving process based on a first decoding scheme through a chip-to-wafer interface according to an embodiment of the present application.

Detailed ways

The embodiments of the present application will be described in further detail below with reference to the accompanying drawings.

It should be understood that in the description of this application, "at least one" refers to one or more than one, and "plurality" refers to two or more. In addition, words such as "first" and "second", unless otherwise stated, are only used for the purpose of distinguishing and describing, and cannot be understood as indicating or implying relative importance, nor can they be understood as indicating or implying order.

FIG. 1 is a schematic diagram of a system chipset obtained by integrating multiple interconnected chips according to an embodiment of the present application. As shown in FIG. 1 , the system chipset 110 includes four chips, namely chip A 102 , chip B 104 , chip C 106 and chip D 108 . Among them, the four wafers included in the system chipset 110 shown in FIG. 1 , namely wafer A 102 , wafer B 104 , wafer C 106 and wafer D 108 , all belong to dies. A chip, also called a bare die or die, is a small unpackaged integrated circuit body made of semiconductor materials. A wafer can be understood as the grain of the chip before it is packaged. It is a small piece cut by laser from a silicon wafer. Each wafer is an independent functional chip. A wafer is packaged as a unit into a chip. The chip cannot be used directly because it is not packaged, has no pins and does not have a heat sink. System on chip refers to the realization of the functions of the entire system on a single chip, also called system on chip or system on chip (SOC). With the rapid growth of chip design scale, system functions have become richer and more complex, and the area of a single chip has also grown rapidly. To realize the functions of the entire system on a single chip, that is, to prepare a system single chip, is facing increasing challenges. , For example, performance improvement becomes more difficult, heat dissipation processing becomes more difficult, leakage current increases, and the chip clock main frequency increases more slowly, etc. Moreover, the increase in chip area and chip design complexity has also brought about the problem of declining manufacturing yield. In order to improve performance while controlling costs and power consumption, the functions of the entire system that were originally implemented on a single system chip are split and implemented through multiple chips, and packaging and interconnection technologies are used to build chipsets or multi-chips. module. For example, through chiplet technology, each functional block originally integrated in the same system single chip is separated, manufactured separately, and finally integrated and packaged into a system chipset through packaging and interconnection technology.

Continuing to refer to FIG. 1 , the system chipset 110 shown in FIG. 1 can correspond to the functions of the entire system. The functions of the system implemented by the system chipset 110 may originally be implemented on a single chip, that is, through a system single chip. However, after the functions of the system chipset 110 are split into four chips in Figure 1, that is, Wafer A 102, wafer B 104, wafer C 106 and wafer D 108 are implemented. Wafer A 102, wafer B 104, wafer C 106 and wafer D 108 are interconnected with each other through die to die interfaces to implement data interconnection. It can be seen from Figure 1 that any one of wafer A 102, wafer B 104, wafer C 106 and wafer D 108 has a wafer-to-wafer interface interconnection relationship with the other three wafers (a bidirectional arrow is used in Figure 1 Shows a die-to-die interface interconnect relationship). The interconnection interface between chips is used for data interconnection between chips, and also corresponds to the chip-to-wafer interface interconnection. It must meet the characteristics of high data bandwidth, low latency and high reliability before it can be used to integrate and package multiple chips to meet the requirements of Chip applications in areas such as networks, hyperscale data centers and artificial intelligence. Here, wafer-to-wafer interface interconnection means interconnecting one wafer to another wafer for packaging together, each wafer including at least one module with a physical interface. One die with a common interface can communicate with another die over short distance wires. Chip-to-chip interface interconnection can be divided into two cases: homogeneous die and heterogeneous die. Among them, homogeneous wafers mainly perform wafer splitting and interconnect the data of two or more equal or homogeneous wafers so that these smaller wafers behave like a single wafer. For example, the four wafers in Figure 1, namely wafer A102, wafer B 104, wafer C 106 and wafer D 108, may all be central processing units (Central Processing Units). Heterogeneous chips are mainly packaged and integrated, integrating different functions into a unified packaged chipset. For example, wafer A 102 and wafer B 104 in FIG. 1 may be central processing units, while wafer C 106 and wafer D 108 may be graphics processing units (GPU) or neural-network processing units. NPU), tensor processing unit (TPU) or data processing unit (DPU). Therefore, different semiconductor manufacturing processes and different integrated packaging methods may affect the relevant details of chip-to-wafer interface interconnection. For example, a chip-to-chip interface interconnect may be used for data interconnection between a CPU chip and another CPU chip, or between a CPU chip and a neural network processor chip. Data interconnection. In addition, chip-to-chip interface interconnection generally uses specific protocols, rules, strategies, etc. to standardize the details of high-speed data transmission between chips. For example, optimization or requirements can be made in traffic control, scheduling functions, bandwidth, data channels and other related aspects to better meet business scenarios such as networks, ultra-large-scale data centers and artificial intelligence. For example, die-to-die interface interconnects may use protocols that support multi-channel transmission and may have data transmission bandwidths of 10 gigabits per second (Gbps) to 300 Gbps or higher. Chip-to-chip interface interconnects may also need to support serializer-deserializer (SERializer/DESerializer, SERDES). SERDES means that multiple low-speed parallel signals are converted into high-speed serial signals at the transmitting end and then transmitted in a differential manner, and high-speed serial signals are converted into low-speed parallel signals at the receiving end. In order to support SERDES, a clock data recovery (CDR) circuit needs to be integrated at the receiving end. The CDR circuit is used to recover the clock signal from the data edge information and perform sampling to recover the data signal. Because multiple chip packages need to be integrated together, the chip-to-chip interface interconnection is also integrated within the chipset, such as the data interconnection between chip A 102, chip B 104, chip C 106 and chip D 108 shown in Figure 1 Integrated inside the system chipset 110. This means that when problems occur in the data interconnection between chips, such as data transmission errors, data loss, etc., it is difficult to locate the problem and make corrections. However, as the requirements for data transmission rates between chips become higher and higher, it also brings greater challenges to ensuring the reliability and accuracy of data transmission between chips. To this end, embodiments of the present application provide a method, device and medium for chip-to-wafer interface interconnection, so that the chip-to-wafer interface interconnection method can meet the requirements of high data transmission rate and high data transmission reliability.

FIG. 2 is a schematic diagram of multiple chips interconnected through a chip-to-wafer interface according to an embodiment of the present application. As shown in Figure 2, data interconnection is achieved between chip E 210 and chip F 220 through respective chip-to-wafer interfaces. Specifically, die E 210 includes die-to-die interface E 212, peripheral component interconnect fast interface E 214, high bandwidth memory interface E 216, and Ethernet interface E 218. Die F 220 includes die-to-die interface F 222 , Peripheral Component Interconnect Fast interface F 224 , high-bandwidth memory interface F 226 , and Ethernet interface F 228 . Among them, the wafer-to-wafer interface E 212 included in the wafer E 210 is used to physically connect with the wafer-to-wafer interface F 222 included in the wafer F 220, thereby realizing data interconnection between the wafer E 210 and the wafer F 220. The peripheral component interconnect express E 214 included in the chip E 210 and the peripheral component interconnect express F 224 included in the chip F 220 are both used to support the peripheral component interconnect express (PCIE) standard, for example, for connecting to PCIE. Standard equipment that can be used to connect servers and high-performance computing centers. The high-bandwidth memory interface E216 included in the chip E 210 and the high-bandwidth memory interface F 226 included in the chip F 220 are both used to connect high-bandwidth memory (HighBandwidth Memory, HBM) and can be used for network switching, network message forwarding and graphics. Processor and other business scenarios. The Ethernet interface E 218 included in the chip E 210 and the Ethernet interface F 228 included in the chip F 220 are both used to provide functions related to Ethernet (ethernet), such as access to an Ethernet network card. The chip E 210 and the chip F 220 shown in Figure 2 each include a variety of interfaces with different functions, so that they can be used in various business scenarios. For example, the PCIE bus can be accessed through the fast peripheral component interconnection interface E 214 included in the chip E 210 Or access the HBM or the like through the high-bandwidth memory interface F 226 included in the chip F 220 . The data interconnection between wafers is realized through the physical connection between wafer E 210 and wafer F 220 through the wafer-to-wafer interface E 212 included in wafer E 210 and the wafer-to-wafer interface F 222 included in wafer F 220, so that Chip E 210 and chip F 220 behave like one chip to the outside world, which improves performance while controlling cost and power consumption. The wafer-to-wafer interface interconnection between wafer E 210 and wafer F 220 is the data interconnection between the wafer-to-wafer interface E 212 included in wafer E 210 and the wafer-to-wafer interface F 222 included in wafer F 220, It needs to meet the output transmission requirements put forward by specific protocols, rules, policies, etc., and may also need to meet requirements in terms of flow control, scheduling functions, bandwidth, data channels, etc.

FIG. 3 is another schematic diagram of multiple chips interconnected through a chip-to-wafer interface according to an embodiment of the present application. As shown in FIG. 3 , die G 310 includes a first die-to-die interface G 312 , a second die-to-die interface G 313 , a high-bandwidth memory interface G 316 , and an Ethernet interface G 318 . Wafer H 320 includes a first wafer-to-wafer interface H 322, a second wafer-to-wafer interface H 323, a high bandwidth memory interface H 326, and an Ethernet interface H 328. The data interconnection between the wafers is realized through the physical connection between the wafer G 310 and the wafer H320 through the first wafer-to-wafer interface G 312 included in the wafer G 310 and the first wafer-to-wafer interface H 322 included in the wafer H 320, so that Chip G 310 and chip H320 behave like one chip to the outside world, which improves performance while controlling cost and power consumption. In addition, the wafer G 310 can also be connected to another wafer through the second wafer-to-wafer interface G 313, and the wafer H 320 can also be connected to another wafer through the second wafer-to-wafer interface H 323. The chip-to-chip interface interconnection between chip G 310 and chip H 320 needs to meet the output transmission requirements of specific protocols, rules, policies, etc., and may also require improvements in flow control, scheduling functions, bandwidth, data channels, etc. fulfil requirements.

Referring to Figure 1, Figure 2 and Figure 3, chip-to-wafer interface interconnection means interconnecting one chip to another chip for packaging together. Each chip includes at least one module with a physical interface. One die with a common interface can communicate with another die over short distance wires. Depending on how multiple chips are integrated and packaged into a chipset, and also based on the functional division and interface layout of multiple chips, a chip may have one or more chip-to-chip interfaces, and each chip-to-chip interface may also use a specific protocol. , rules, policies, etc., to meet the requirements in data transmission, flow control, scheduling functions, bandwidth, data channels, etc. These protocols, rules, strategies, etc. may also impose requirements on specific details of chip-to-chip interface interconnection, such as the number of communication channels, control word structure, data encoding and data decoding, flow control options, etc. To this end, it is necessary to provide a chip-to-chip interface interconnection method that can meet the needs of high data transmission rate and high data transmission reliability, and can also flexibly adapt to various protocols, rules, policies, etc., such as data transmission, traffic Requirements for control, scheduling functions, bandwidth, data channels, etc. Detailed description is given below in conjunction with Figure 4.

FIG. 4 is a schematic flowchart of a chip-to-wafer interface interconnection method provided by an embodiment of the present application. Wherein, the wafer-to-wafer interface interconnection method shown in Figure 4 is applicable to multiple wafers, and each wafer in the multiple wafers includes a wafer-to-wafer interface for the wafer and another of the multiple wafers relative to the wafer. Data interconnection between chips. The method is applied to a first wafer, which is any wafer among the plurality of wafers, and the wafer-to-wafer interface of the first wafer includes an interface cache, a protocol processing unit and a transmission interface. As shown in Figure 4, the method includes the following steps.

Step S402: In response to the data transmission of the first chip, input the first data to be sent to the interface cache.

Step S404: Use the protocol processing unit to perform data cutting on the first data to be sent to obtain cut data, perform cyclic redundancy check calculation on the cut data to generate a cyclic redundancy calculation result, and convert the cyclic redundancy calculation result to the cut data. The redundant calculation results are added to the cut data to assemble and stripe the distributed data to obtain the distributed data. The distributed data is encoded to obtain the encoded data. The encoded data is scrambled and grouped. The frame gets the second data to be sent.

Step S406: Send the second data to be sent through the transmission interface.

Step S408: In response to the data reception of the first chip, obtain the first data to be received through the transmission interface.

Step S410: Use the protocol processing unit to frame and descramble the first data to be received and then perform a decoding operation to obtain decoded data. Perform data aggregation processing on the decoded data to obtain aggregated data. The aggregated data is subjected to cyclic redundancy check and data combination to obtain the second data to be received.

Step S412: Input the second data to be received into the interface cache.

The method of wafer-to-wafer interface interconnection shown in Figure 4 is applicable to a plurality of wafers, each wafer of the plurality of wafers including a wafer-to-wafer interface for that wafer and another wafer of the plurality of wafers relative to the wafer. data interconnection between. The method is applied to a first wafer, which is any wafer among the plurality of wafers, and the wafer-to-wafer interface of the first wafer includes an interface cache, a protocol processing unit and a transmission interface. Multiple chips correspond to the combination of multiple functional blocks to form a chip, and the interface between each functional block is a chip-to-chip interface. The first wafer is any one of the plurality of wafers, and the wafer-to-wafer interface of the first wafer provides data interconnection between the first wafer and another wafer. Referring to the above steps, in step S402, in response to the data transmission of the first chip, the first data to be sent is input into the interface buffer. Here, the first chip may receive data from the user side and input the data from the user side into the interface cache. In some embodiments, rate adaptation processing can be performed through the interface cache, which contributes to the overall stability and reliability of data transmission. Next, in step S404, the protocol processing unit performs data cutting on the first data to be sent to obtain cut data. The chip-to-chip interface of the first chip may adopt specific protocols, rules, strategies, etc., to meet relevant requirements in data transmission, flow control, scheduling functions, bandwidth, data channels, etc. These protocols, rules, strategies, etc. may also impose requirements on specific details of chip-to-chip interface interconnection, such as the number of communication channels, control word structure, data encoding and data decoding, flow control options, etc. Here, the protocol processing unit is mainly used to provide necessary processing functions to meet the protocols, rules, or strategies adopted by the chip-to-wafer interface of the first chip in terms of data transmission, flow control, scheduling functions, bandwidth, data requirements for channels, etc. In step S404, the protocol processing unit performs data segmentation on the first data to be sent to obtain segmented data. This means that data is cut at the protocol layer. This takes into account the setting of the burst length and the need for control word assembly in the subsequent process. The length of data transmitted at one time is called the burst length. Generally speaking, data segmentation is performed by segmenting data in units of fixed bits (for example, 64 bits). Perform cyclic redundancy check calculation on the cut data to generate a cyclic redundancy calculation result. The cyclic redundancy check calculation is performed to generate the cyclic redundancy calculation result for the purpose of the cyclic redundancy check (CRC) of the subsequent process. CRC uses a hash function that can generate a short fixed-digit check code based on data such as data packets or files to check errors that may occur after data transmission or storage. The check code can be calculated before the data is transmitted or saved and appended to the data so that the receiver can verify whether the data has changed. In step S404, the cyclic redundancy calculation result is added to the cut data to perform assembly and striping distribution to obtain distributed data. Here, assembly means data cutting and control word assembly. In some embodiments, the protocol control word and the data word representing the data to be transmitted are assembled together with the setting of the burst length on the basis of data cutting. Striping means that according to the requirements of data channels and channelized data transmission, the distributed data can be sent through multiple channels. For example, each channel can correspond to a SERDES physical link. Therefore, in response to the data transmission of the first wafer, the first data to be sent is input to the interface cache, and then is cut by the data to obtain the cut data, and then the cyclic redundancy calculation result is added to the cut data. The post-data is then assembled and striped for distribution to obtain the post-distribution data. This completes the conversion from the first data to be sent to the distributed data, and also reflects the details of control at the protocol layer, which can be used to meet requirements such as the number of communication channels and control word structure. Next, in step S404, an encoding operation is performed on the distributed data to obtain encoded data, and the encoded data is scrambled and framed to obtain second data to be sent. Encoding operation means performing frame layer control word assembly, which includes adding a synchronization word as a meta-frame synchronization header to determine the meta-frame position. It should be understood that encoding operations are generally based on specific protocols, rules, strategies, etc. adopted by the chip-to-wafer interface of the first chip. For example, the protocol may stipulate a specific encoding format, requiring the original data to be encoded according to a certain The rules are written into data in a specific encoding format. In some embodiments, performing an encoding operation means encoding 64-bit data into 67-bit data. After the encoding operation is performed to obtain the encoded data, the encoded data is scrambled and framed to obtain the second data to be sent. This helps enhance data integrity and link stability. Finally, in step S406, the second data to be sent is sent through the transmission interface. In some embodiments, the transmission interface is connected to multiple SERDES channels, and the second data to be sent can be aligned and then sent out through the multiple SERDES channels.

Continuing to refer to FIG. 4 and the above steps, in step S408, in response to the data reception of the first chip, the first data to be received is obtained through the transmission interface. Next, in step S410, the protocol processing unit performs framing and descrambling on the first data to be received and then performs a decoding operation to obtain decoded data, and performs data aggregation processing on the decoded data to obtain aggregated data. , perform cyclic redundancy check and data combination on the aggregated data to obtain the second data to be received. In this way, after the first data to be received received from the transmission interface, for example, the data received through the SERDES interface, is framed and descrambled, frame positioning and descrambling are completed. Then, the decoding operation is performed, and the decoded data undergoes data aggregation processing. Finally, the user data is restored through cyclic redundancy check and data combination, and finally written into the data cache. It can be sent to the user-side interface after rate adaptation adjustment.

In this way, a chip-to-chip interface interconnection method shown in Figure 4 can meet the needs of high data transmission rate and high data transmission reliability, and can also flexibly adapt to various protocols, rules, strategies, etc., such as data transmission , flow control, scheduling functions, bandwidth, data channels, etc. requirements. In the wafer-to-wafer interface interconnection method shown in Figure 4, the encoding operation and the decoding operation may be based on the specific protocol adopted by the wafer-to-wafer interface of the first wafer, for example, encoding according to the encoding format and rules specified therein and decoding. Generally, the interface between chips requires a large data transmission bandwidth, and also has flow control and channelized transmission characteristics. In the business scenario of network chips, in order to achieve high-speed digital communication transmission, a combination of a specific communication protocol interface and SERDES can be used at the interface between chips.

In a possible implementation, the encoding operation is based on a first encoding scheme, the decoding operation is based on a first decoding scheme, and the first encoding scheme corresponds to the first decoding scheme. In some embodiments, the first encoding scheme is 64/67 encoding and the first decoding scheme is 64/67 decoding. In this way, through the first encoding scheme and the first decoding scheme corresponding to each other, data transmission and data reception of the wafer-to-wafer interface of the first wafer can be achieved. Among them, 64/67 encoding means that the original data is compiled into data in a specific encoding format according to certain rules, that is, 64-bit data is encoded into 67-bit data. 64/67 decoding means decoding 67-bit data into 64-bit data.

In a possible implementation, the first data to be sent comes from a user data interface associated with the first chip, and the second data to be received is sent to the user data interface. In some embodiments, the second data to be received undergoes rate adaptation processing before being sent to the user data interface. In this way, through rate adaptation processing, it contributes to the overall stability and reliability of data transmission.

In a possible implementation, the second data to be sent is sent to a transmission interface of a wafer-to-wafer interface of a second wafer relative to the first wafer. In this way, data interconnection between the first chip and the second chip is achieved.

In a possible implementation, the protocol processing unit adds the cyclic redundancy calculation result to the cut data to assemble and stripe the distributed data to obtain the distributed data, including: The protocol processing unit adds the cyclic redundancy calculation result to the cut data to assemble and stripe the distributed data according to the setting of the burst length to obtain the distributed data. In this way, on the basis of data cutting, the protocol control word and the data word representing the data to be transmitted are assembled together with the setting of the burst length. Striping means that according to the requirements of data channels and channelized data transmission, the distributed data can be sent through multiple channels. For example, each channel can correspond to a SERDES physical link. Therefore, adding the cyclic redundancy calculation result to the cut data to assemble and stripe the distributed data according to the setting of the burst length means that the setting of the burst length is combined, that is, Setting the data length for one transmission will facilitate subsequent data transmission through multiple channels such as multiple SERDES channels.

In a possible implementation, the transmission interface is a serializer-deserializer interface. In a possible implementation, the protocol processing unit is an Interlaken protocol processing unit. Generally, the interface between chips requires a large data transmission bandwidth, and also has flow control and channelized transmission characteristics. In the business scenario of network chips, in order to achieve high-speed digital communication transmission, a combination of a specific communication protocol interface and SERDES can be used at the interface between chips. As mentioned above, in the wafer-to-wafer interface interconnection method shown in Figure 4, the encoding operation and decoding operation may be based on the specific protocol adopted by the wafer-to-wafer interface of the first wafer, for example, according to the encoding format specified therein and rules for encoding and decoding. For example, the Interlaken protocol specifies a specific encoding format of 64/67 encoding, which means that when the protocol processing unit is the Interlaken protocol processing unit, the chip-to-wafer interface of the first chip is based on the Interlaken protocol. The data is interconnected, so the original data needs to be compiled into data in a specific encoding format according to certain rules, that is, 64-bit data is encoded into 67-bit data. It should be understood that the Interlaken protocol processing unit is optimized for the Interlaken protocol. The protocol processing unit may also adapt to other inter-chip communication protocols, such as XAUI protocol and PCIE protocol. Depending on the specific protocol used, as well as the settings of the transmission interface, etc., the corresponding encoding scheme and decoding scheme can be used, so that various protocols, rules, strategies, etc. can be flexibly adapted to data transmission, flow control, scheduling functions, etc. Bandwidth, data channel, etc. requirements.

In a possible implementation, through the protocol processing unit, at least before performing data cutting on the first data to be sent to obtain the cut data, the first data to be sent in the interface cache is processed. Rate adaptation processing. In this way, through rate adaptation processing, it contributes to the overall stability and reliability of data transmission.

In a possible implementation, through the protocol processing unit, during the process of performing cyclic redundancy check calculation on the cut data to generate the cyclic redundancy calculation result, a control field is synchronously generated for recording the Description information of the cut data. In this way, the generated control fields can be used for data cutting and control word assembly. For example, the control field may record description information of the cut data to reflect protocol layer control details, such as control word structure, etc.

In a possible implementation, the plurality of wafers are homogeneous wafers or heterogeneous wafers. In a possible implementation, the plurality of chips correspond to functional blocks in the same system single chip, and the plurality of chips are packaged together through respective chip-to-wafer interfaces to form a system corresponding to the system single chip. System chipset. In a possible implementation, the plurality of wafers are packaged together using die technology. It should be understood that different semiconductor manufacturing processes and different integrated packaging methods may affect the relevant details of the chip-to-wafer interface interconnection. For example, chip-to-chip interface interconnection may be used for data interconnection between homogeneous chips, such as a CPU chip and another CPU chip, or may be used for heterogeneous chips, such as a CPU chip and a neural network chip. Data interconnection between chips of a network processor.

Continuing to refer to Figure 4, a chip-to-chip interface interconnection method shown in Figure 4 can meet the requirements of high data transmission rate and high data transmission reliability, and can also flexibly adapt to various protocols, rules, strategies, etc. Such as data transmission, flow control, scheduling functions, bandwidth, data channels, etc. requirements. In the wafer-to-wafer interface interconnection method shown in Figure 4, the encoding operation and the decoding operation may be based on the specific protocol adopted by the wafer-to-wafer interface of the first wafer, for example, encoding according to the encoding format and rules specified therein and decoding. With higher requirements on data transmission bandwidth and data transmission rate, it also brings greater challenges in data transmission reliability and data error correction. Moreover, it is also necessary to consider that the specific encoding scheme and decoding scheme adopted may change due to the protocols, rules, strategies, etc. used in the chip-to-chip interface. Therefore, it is necessary to provide a universal data protection in the protocol layer processing part. The mechanism can flexibly enhance data protection according to the requirements of specific communication protocols and specific encoding and decoding schemes, including enhancing the error detection of link data and providing an error correction mechanism, thereby improving the high-speed data of the interconnection interface between chips. The reliability of transmission meets the application requirements in fields such as networks, large-scale data centers, and artificial intelligence. These improvements are detailed below.

In a possible implementation, the encoding operation is based on a first encoding scheme, the encoded data includes a plurality of pre-compression data, and the sizes of the plurality of pre-compression data are all bits of the first value, so The first value is based on the first encoding scheme, wherein scrambling and framing the encoded data to obtain the second data to be sent includes: performing compression and conversion on the plurality of pre-compression data respectively. The code obtains a plurality of compressed data corresponding to the plurality of pre-compression data, performs forward error correction calculation on the plurality of pre-compression data to generate a redundant error correction code, and converts the redundant error correction code into The plurality of compressed data are added to update the encoded data, and the updated encoded data are scrambled and framed to obtain the second data to be sent. In this way, forward error correction (FEC) technology is used to control transmission errors in the communication system and perform error recovery by sending additional information along with the data to reduce the bit error rate. Specifically, FEC technology is used to enhance the data to be sent and add a certain redundant error correction code before sending it together, so that the receiver can perform error detection and error correction on the received data based on the error correction code. In this way, on the basis of the plurality of pre-compression data included in the encoded data, the plurality of pre-compression data are compressed and transcoded respectively to obtain a plurality of compressed data corresponding to the plurality of pre-compression data. data, and performs forward error correction calculation on the plurality of pre-compressed data to generate redundant error correction codes, and adds the redundant error correction codes to the plurality of compressed data to update the encoded data. In this way, by using FEC technology to generate redundant error correction codes, data protection is enhanced, the bit error rate of interface data transmission between chips can be reduced, and the multiple pre-compression data are also compressed and transcoded respectively to obtain the same The multiple pre-compression data correspond to multiple compressed data one-to-one, thus reducing the data scale, so that the redundant error correction code can be added to the multiple compressed data subsequently to update the encoded data. , for example, redundant data fields can be added at the end of the data to be sent, thereby reducing the impact on data transmission bandwidth. Finally, the updated encoded data is scrambled and framed to obtain the second data to be sent, which not only enhances data protection but also reduces the impact on data transmission bandwidth. It should be noted that the encoding operation is based on the first encoding scheme, the sizes of the plurality of pre-compressed data are all bits of a first value, and the first value is based on the first encoding scheme. Therefore, the above-mentioned enhanced data protection mechanism can adapt to the first encoding scheme specified by the communication protocol, and therefore can flexibly enhance data protection according to the requirements of the specific communication protocol and the specific encoding and decoding scheme. In some embodiments, the first encoding scheme is 64/67 encoding and the first value is 67. That is to say, the sizes of the plurality of pre-compressed data are all 67 bits.

Further, in some embodiments, the size of the encoded data before the update is consistent with the size of the encoded data after the update, and the plurality of compressed data correspond to the plurality of pre-compressed data. The data field, the redundant error correction code generated by performing forward error correction calculation on the plurality of pre-compression data corresponds to the bit field used for synchronization in the plurality of pre-compression data. In this way, after performing an encoding operation based on the first encoding scheme to obtain a plurality of pre-compression data included in the encoded data, the plurality of pre-compression data are compressed and transcoded respectively to obtain the same data as the plurality of pre-compression data. Multiple compressed data corresponding to one. Furthermore, the size of the encoded data before the update is consistent with the size of the encoded data after the update. This means that when FEC technology is used to generate redundant error correction codes and the redundant error correction codes are added to the plurality of compressed data to update the encoded data, the size of the data is not changed, but through compression Transcoding obtains a compressed data space for transmitting the redundant data field of the FEC algorithm, which is the FEC error correction code. Moreover, the plurality of compressed data correspond to the data fields in the plurality of pre-compressed data, which means that on the premise of keeping the data field unchanged, the redundant part is used to store the error correction code, so the overall encoding The size of the final data remains unchanged before and after the update. For example, assuming that the plurality of pre-compression data are four data with a size of 67 bits each (for example, the first value is 67), after compression, the four data with a size of 67 bits each become 261 bits. , then the error correction code occupies 7 bits. This means that the size of the encoded data before the update is four 67-bit data, that is, 268 bits, and the size of the encoded data after the update is 261 bits plus The 7 bits occupied by the error correction code are therefore still 268 bits. In this way, the FEC error correction mechanism is introduced without changing the link transmission bandwidth. By adding corresponding reverse transcoding and FEC decoding operations at the receiving end, data protection can be enhanced. In some embodiments, the FEC algorithm may be an RS (536, 522) algorithm, and the corresponding redundant error correction code is 140 bits, which can protect 5220 bits of data. That is to say, at the sending end, the redundant error correction code (size is 140 bits) is calculated based on the input data block (size is 5220 bits), and the redundant error correction code is combined at the end of the data block and then transmitted together. At the receiving end, based on the frame delimited FEC data block and retrograde FEC check calculation, if the data in the data field is found to be incorrect, the error can be corrected based on the error correction code to recover the correct data. Data protection schemes using this FEC algorithm can correct up to 70 bit errors in the data field.

Further, in a possible implementation, the decoding operation is based on a first decoding scheme, the first encoding scheme corresponds to the first decoding scheme, wherein the decoded data is subjected to data aggregation processing to obtain the aggregation The post-data includes: decompressing and reverse transcoding the decoded data, then performing forward error correction check, and then performing data aggregation processing to obtain the post-aggregation data. In this way, on the basis of using FEC technology to enhance data protection at the sending end, corresponding reverse transcoding and FEC decoding operations are also performed at the receiving end (for example, the compressed synchronization header bits used for synchronization can be restored and added to the receiving end). Corresponding data block position), thus establishing a universal data protection mechanism for data interconnection between chips. On the one hand, FEC technology is used to generate redundant error correction codes and the redundant error correction codes are added to the multiple compression The post-data thereby updates the encoded data, so that errors in the data domain can be corrected through the redundant error correction code generated by the FEC algorithm and data transmission reliability is provided. On the other hand, compression and transcoding are used to ensure the overall encoded data. The size before and after the update remains unchanged, thus avoiding the increase in link transmission bandwidth due to the introduction of redundant error correction codes, and the use of redundant data fields does not affect the data field itself (the multiple pre-compression data The redundant error correction code generated by forward error correction calculation corresponds to the bit field used for synchronization in the plurality of pre-compression data), and FEC protection is achieved while keeping the link transmission bandwidth unchanged. In addition, both encoding operations and decoding operations can be combined with the requirements of specific communication protocols. For example, the Interlaken protocol stipulates that the first encoding scheme is a specific encoding format such as 64/67 encoding, and corresponding compression and transcoding can be performed. For example, four data of 67 bits each are compressed and transcoded to obtain 261 bits. , thereby providing 7 bits for the redundant error correction code. In other words, the appropriate FEC algorithm can be flexibly adopted according to the requirements of the specific communication protocol and the specific encoding and decoding scheme, so that it can adapt to the first encoding scheme specifically specified by the communication protocol, and therefore can flexibly be used according to the specific communication protocol. requirements and specific encoding and decoding schemes to enhance data protection. In addition, by selecting the first decoding scheme corresponding to the first encoding scheme, on the basis of using FEC technology to strengthen data protection at the sending end, the corresponding reverse transcoding and FEC decoding operations are also performed at the receiving end, thus establishing a chip The universal data protection mechanism for data interconnection can flexibly enhance data protection according to the requirements of specific communication protocols and specific encoding and decoding schemes, including enhancing error detection of link data and providing error correction mechanisms, thereby It can improve the reliability of high-speed data transmission of interconnect interfaces between chips and meet application needs in fields such as networks, large-scale data centers, and artificial intelligence.

Further, in a possible implementation, performing compression and transcoding on the plurality of pre-compression data to obtain the plurality of post-compression data corresponding to the one-to-one correspondence with the plurality of pre-compression data includes: compressing the The bit field used for synchronization in the plurality of pre-compression data is used to transmit the redundant error correction code, and the data field in the plurality of pre-compression data is maintained. In some embodiments, the link transmission bandwidth of the transmission interface associated with the plurality of pre-compression data is equal to the link transmission bandwidth of the transmission interface associated with the plurality of post-compression data. In some embodiments, performing compression and transcoding on the plurality of pre-compression data to obtain the plurality of post-compression data corresponding to the plurality of pre-compression data is based on the first encoding scheme, and the The first encoding scheme is based on a die-to-die interface interconnect protocol associated with the protocol processing unit. In some embodiments, the first decoding scheme is also based on a die-to-die interface interconnect protocol associated with the protocol processing unit. In this way, the appropriate FEC algorithm can be flexibly adopted according to the requirements of the specific communication protocol and the specific encoding and decoding scheme, so that the first encoding scheme specified by the communication protocol can be adapted, and therefore the FEC algorithm can be flexibly adopted according to the requirements of the specific communication protocol. requirements as well as specific encoding and decoding schemes to enhance data protection. In addition, by selecting the first decoding scheme corresponding to the first encoding scheme, on the basis of using FEC technology to strengthen data protection at the sending end, the corresponding reverse transcoding and FEC decoding operations are also performed at the receiving end, thus establishing a chip The universal data protection mechanism for data interconnection can flexibly enhance data protection according to the requirements of specific communication protocols and specific encoding and decoding schemes, including enhancing error detection of link data and providing error correction mechanisms, thereby It can improve the reliability of high-speed data transmission of interconnect interfaces between chips and meet application needs in fields such as networks, large-scale data centers, and artificial intelligence.

FIG. 5 is a schematic flowchart of a data sending process based on a first encoding scheme through a chip-to-wafer interface according to an embodiment of the present application. As shown in Figure 5, the data transmission process through the wafer-to-wafer interface and based on the first encoding scheme consists of the following steps.

Step S502: Data caching.

Step S504: Data cutting.

Step S506: Calculate cyclic redundancy check and generate control words.

Step S508: Assembly and striping processing.

Step S510: Encoding based on the first encoding scheme.

Step S512: Compress and transcode based on the first encoding scheme.

Step S514: Forward error correction calculation.

Step S516: scrambling and framing.

For the data sending process through the chip-to-chip interface shown in Figure 5 and based on the first encoding scheme, you can refer to the chip-to-chip interface interconnection method shown in Figure 4, so it can meet the requirements of high data transmission rate and high data transmission reliability. It can also flexibly adapt to the requirements of various protocols, rules, strategies, etc. in terms of data transmission, flow control, scheduling functions, bandwidth, data channels, etc. Further, the data sending process through the chip-to-wafer interface and based on the first encoding scheme shown in Figure 5 also includes compression and transcoding based on the first encoding scheme in step S512 and forward error correction calculation in step S514. Therefore, at the protocol layer The processing part introduces a universal data protection mechanism based on FEC technology, which can flexibly enhance data protection according to the requirements of specific communication protocols and specific coding and decoding schemes, including the ability to enhance error detection of link data and provide error correction mechanism, which can improve the reliability of high-speed data transmission of interconnect interfaces between chips and meet application needs in fields such as networks, large-scale data centers, and artificial intelligence.

FIG. 6 is a schematic flowchart of a data receiving process based on a first decoding scheme through a chip-to-wafer interface according to an embodiment of the present application. As shown in Figure 6, the data reception process through the chip-to-wafer interface and based on the first decoding scheme consists of the following steps.

Step S602: Framing and descrambling.

Step S604: Decode based on the first decoding scheme.

Step S606: Decompress and reverse transcode based on the first decoding scheme.

Step S608: Forward error correction verification.

Step S610: Data aggregation processing.

Step S612: Cyclic redundancy check.

Step S614: Data combination.

Step S616: Data caching.

For the data receiving process shown in Figure 6 through the chip-to-chip interface and based on the first decoding scheme, reference can be made to the chip-to-chip interface interconnection method shown in Figure 4, which reflects the corresponding operations taken at the receiving end. And further, the data reception process shown in Figure 6 is performed through the chip-to-wafer interface and based on the first decoding scheme, decompression and reverse transcoding based on the first decoding scheme in step S606 and forward error correction verification in step S608 , so in the protocol layer processing part, on the basis of using FEC technology to strengthen data protection at the sending end, the receiving end also performs corresponding reverse transcoding and FEC decoding operations, thus establishing a common data for data interconnection between chips. protection mechanism.

Referring to Figures 5 and 6, the data transmission process shown in Figure 5 through the chip-to-wafer interface and based on the first encoding scheme, compression and transcoding based on the first encoding scheme in step S512 and forward error correction calculation in step S514, Figure The data receiving process shown in 6 is performed through the chip-to-wafer interface and based on the first decoding scheme. In step S606, the data is decompressed and reversely transcoded based on the first decoding scheme and in step S608, the forward error correction is performed. Therefore, the Flexibly adopt the appropriate FEC algorithm according to the requirements of the specific communication protocol and the specific encoding and decoding scheme, so that it can adapt to the first encoding scheme specified by the communication protocol, so it can flexibly adopt the appropriate FEC algorithm according to the requirements of the specific communication protocol and the specific encoding and decoding scheme. Encoding and decoding schemes to enhance data protection. By selecting the first decoding scheme corresponding to the first encoding scheme, on the basis of using FEC technology to enhance data protection at the transmitting end, the corresponding reverse transcoding and FEC decoding operations are also performed at the receiving end, thus establishing an inter-chip The universal data protection mechanism of data interconnection can flexibly enhance data protection according to the requirements of specific communication protocols and specific encoding and decoding schemes, including enhancing error detection of link data and providing error correction mechanisms, which can improve The reliability of high-speed data transmission of interconnect interfaces between chips meets the application needs in fields such as networks, large-scale data centers, and artificial intelligence.

Referring to FIGS. 1 to 6 , embodiments of the present application provide a chip-to-wafer interface interconnection method. Each wafer of the plurality of wafers includes a wafer-to-wafer interface for data interconnection between the wafer and another wafer of the plurality of wafers relative to the wafer, the method is applied to a first wafer, the second wafer A wafer is any wafer among the plurality of wafers, the wafer-to-wafer interface of the first wafer includes an interface cache, a protocol processing unit and a transmission interface, and the method includes: in response to data transmission of the first wafer , input the first data to be sent to the interface cache; through the protocol processing unit, perform data cutting on the first data to be sent to obtain the cut data, and perform cyclic redundancy check calculation and generation on the cut data The cyclic redundancy calculation result is added to the cut data to perform assembly and striping distribution to obtain the distributed data, and the distributed data is obtained by encoding the distributed data based on the first encoding scheme. Encoded data including a plurality of pre-compression data, compressing and transcoding the plurality of pre-compression data respectively to obtain a plurality of compressed data corresponding to the plurality of pre-compression data, and performing compression on the plurality of compressed data Perform forward error correction calculations on the previous data to generate redundant error correction codes, add the redundant error correction codes to the plurality of compressed data to update the encoded data, and scramble the updated encoded data. The second data to be sent is obtained by coding and framing, wherein the size of the coded data before updating is consistent with the size of the coded data after updating; the second data to be sent is sent through the transmission interface. Send the second data, in response to the data reception of the first chip, obtain the first data to be received through the transmission interface; frame and descramble the first data to be received through the protocol processing unit, and then Perform a decoding operation based on the first decoding scheme to obtain decoded data, perform data aggregation processing on the decoded data to obtain aggregated data, perform cyclic redundancy check and data combination on the aggregated data to obtain the second data to be received, The first encoding scheme corresponds to the first decoding scheme; the second data to be received is input into the interface cache.

The methods and devices provided in the embodiments of the present application are based on the same inventive concept. Since the principles of the methods and devices for solving problems are similar, the embodiments, implementations, examples or implementations of the methods and devices can be referred to each other, and there are no duplications. Again. An embodiment of the present application also provides a system that includes multiple computing devices. The structure of each computing device may refer to the structure of the computing device described above. The functions or operations that can be implemented by the system can be referred to the specific implementation steps in the above method embodiment and/or the specific functions described in the above device embodiment, and will not be described again here.

Embodiments of the present application also provide a computer-readable storage medium. Computer instructions are stored in the computer-readable storage medium. When the computer instructions are run on a computer device (such as one or more processors), the above can be implemented. Method steps in method embodiments. The specific implementation of the processor of the computer-readable storage medium in executing the above method steps may refer to the specific operations described in the above method embodiments and/or the specific functions described in the above device embodiments, which will not be described again here.

Those skilled in the art will understand that embodiments of the present application may be provided as methods, systems, or computer program products. The application may take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment that combines software and hardware aspects. The embodiments of the present application may be implemented in whole or in part through software, hardware, firmware, or any other combination. When implemented using software, the above-described embodiments may be implemented in whole or in part in the form of a computer program product. The application may take the form of a computer program product embodied on one or more computer-usable storage media embodying computer-usable program code therein. The computer program product includes one or more computer instructions. When the computer program instructions are loaded or executed on a computer, the processes or functions described in the embodiments of the present application are generated in whole or in part. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices. Computer instructions may be stored in or transmitted from one computer-readable storage medium to another computer-readable storage medium, e.g., computer instructions may be transmitted from a website, computer, server or data center via a wired link (e.g. Coaxial cable, optical fiber, digital subscriber line) or wireless (such as infrared, wireless, microwave, etc.) means to transmit to another website, computer, server or data center. Computer-readable storage media can be any available media that can be accessed by the computer, or data storage devices such as servers and data centers that contain one or more sets of available media. Available media may be magnetic media (such as floppy disks, hard disks, tapes), optical media, or semiconductor media. The semiconductor medium may be a solid state drive, or it may be random access memory, flash memory, read-only memory, erasable programmable read-only memory, electrically erasable programmable read-only memory, a register, or any other form of suitable storage medium.

The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the application. Each process and/or block in the flowchart illustrations and/or block diagrams, and combinations of processes and/or blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing device to produce a machine, such that the instructions executed by the processor of the computer or other programmable data processing device produce a use A device for realizing the functions specified in one process or multiple processes of the flowchart and/or one block or multiple blocks of the block diagram. These computer program instructions may also be stored in a computer-readable memory that causes a computer or other programmable data processing apparatus to operate in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including the instruction means, the instructions The device implements the functions specified in a process or processes of the flowchart and/or a block or blocks of the block diagram. These computer program instructions may also be loaded onto a computer or other programmable data processing device, causing a series of operating steps to be performed on the computer or other programmable device to produce computer-implemented processing, thereby executing on the computer or other programmable device. Instructions provide steps for implementing the functions specified in a process or processes of a flowchart diagram and/or a block or blocks of a block diagram.

In the above embodiments, each embodiment is described with its own emphasis. For parts that are not described in detail in a certain embodiment, please refer to the relevant descriptions of other embodiments. Obviously, those skilled in the art can make various changes and modifications to the embodiments of the present application without departing from the spirit and scope of the embodiments of the present application. The steps in the methods of the embodiments of this application can be sequentially adjusted, merged or deleted according to actual needs; the modules in the system of the embodiments of this application can be divided, merged or deleted according to actual needs. If these modifications and variations of the embodiments of the present application fall within the scope of the claims of this application and equivalent technologies, this application is also intended to include these modifications and variations.

Claims (15)

1. A method of wafer-to-wafer interface interconnection, wherein each wafer of a plurality of wafers includes a wafer-to-wafer interface for data interconnection between the wafer and another wafer of the plurality of wafers relative to the wafer, the method being applied to a first wafer that is any wafer of the plurality of wafers, the wafer-to-wafer interface of the first wafer including an interface cache, a protocol processing unit, and a transport interface, the method comprising:

Responding to the data transmission of the first wafer, and inputting first data to be transmitted to the interface cache;

performing data cutting on the first data to be sent through the protocol processing unit to obtain cut data, performing cyclic redundancy check calculation on the cut data to generate a cyclic redundancy calculation result, adding the cyclic redundancy calculation result into the cut data to perform assembling and striping distribution to obtain distributed data, performing coding operation on the distributed data based on a first coding scheme to obtain coded data comprising a plurality of compressed data, performing compression transcoding on the plurality of compressed data to obtain a plurality of compressed data which are in one-to-one correspondence with the plurality of compressed data, performing forward error correction calculation on the plurality of compressed data to generate a redundancy error correction code, adding the redundancy error correction code into the plurality of compressed data to update the coded data, and performing scrambling and framing on the updated coded data to obtain second data to be sent, wherein the size of the coded data before updating is consistent with the size of the updated coded data;

Transmitting the second data to be transmitted through the transmission interface,

responding to the data receiving of the first wafer, and acquiring first data to be received through the transmission interface;

the protocol processing unit is used for framing and descrambling the first data to be received, then carrying out decoding operation based on a first decoding scheme to obtain decoded data, carrying out data aggregation processing on the decoded data to obtain aggregated data, and carrying out cyclic redundancy check and data combination on the aggregated data to obtain second data to be received, wherein the first coding scheme corresponds to the first decoding scheme;

and inputting the second data to be received to the interface cache.

2. The method according to claim 1, wherein adding, by the protocol processing unit, the cyclic redundancy calculation result to the cut data to perform assembling and striping distribution to obtain the distributed data, comprises: and adding the cyclic redundancy calculation result into the cut data through the protocol processing unit so as to assemble and stripe the data according to the burst length setting to obtain the distributed data.

3. The method of claim 1, wherein the transmission interface is a serializer deserializer interface.

4. The method of claim 1, wherein the protocol processing unit is an Interlaken protocol processing unit.

5. The method of claim 1, wherein the plurality of wafers are homogenous wafers or heterogeneous wafers.

6. The method of claim 1, wherein the plurality of wafers correspond to functional blocks in a same system single wafer, the plurality of wafers being packaged together through respective wafer-to-wafer interfaces to form a system chipset corresponding to the system single wafer.

7. The method of claim 1, wherein the plurality of wafers are packaged together by a die technique.

8. The method of claim 1, wherein the plurality of pre-compression data sizes are each bits of a first value, the first value being based on the first encoding scheme.

9. The method of claim 8, wherein the plurality of compressed data corresponds to a data field in the plurality of pre-compressed data, and wherein the redundant error correction code generated by performing forward error correction calculations on the plurality of pre-compressed data corresponds to a bit field for synchronization in the plurality of pre-compressed data.

10. The method of claim 8, wherein performing data aggregation on the decoded data to obtain aggregated data comprises: and decompressing and reversely transcoding the decoded data, then carrying out forward error correction test, and then carrying out data aggregation processing to obtain the aggregated data.

11. The method of claim 9, wherein performing compression transcoding on the plurality of pre-compression data to obtain the plurality of post-compression data that corresponds one-to-one to the plurality of pre-compression data, respectively, comprises:

compressing bit fields for synchronization in the plurality of pre-compression data for transmission of the redundant error correction code, and maintaining data fields in the plurality of pre-compression data.

12. The method of claim 11, wherein a link transmission bandwidth of the transmission interface associated with the plurality of pre-compressed data is equal to a link transmission bandwidth of the transmission interface associated with the plurality of post-compressed data.

13. The method of claim 12, wherein compression transcoding the plurality of pre-compression data to the plurality of pre-compression data in one-to-one correspondence with the plurality of pre-compression data is based on the first encoding scheme, the first encoding scheme being based on a wafer-to-wafer interface interconnect protocol associated with the protocol processing unit.

14. A computer device, characterized in that it comprises a memory, a processor and a computer program stored on the memory and executable on the processor, which processor implements the method according to any of claims 1 to 13 when executing the computer program.

15. A computer readable storage medium storing computer instructions which, when run on a computer device, cause the computer device to perform the method of any one of claims 1 to 13.