CN116614110B - Four-node overturning-resistant latch circuit and module based on reinforcement technology - Google Patents

Abstract

The invention relates to the technical field of integrated circuit design, in particular to a four-node flip latch resistant latch circuit based on reinforcement technology and a module packaged based on the four-node flip latch resistant latch circuit. The storage nodes X0, X3, X4, X7, X8 and X11 are all surrounded by PMOS transistors to form polarity reinforcement, so that overturn is effectively avoided. The invention uses source isolation technology to make the storage nodes X1, X2, X5, X6, X9 and X10 only generate the voltage pulses of 1-0 and 0-0, which can effectively reduce the number of sensitive nodes of the circuit and improve the stability of the circuit. The invention constructs the C unit part with multi-stage input, and can ensure the correct output of Q under the cooperation of the multi-node bombarded. The circuit has complete SNU, DNU, TNU, QNU resistance, low delay, low power consumption and small area.

Description

Four-node overturning-resistant latch circuit and module based on reinforcement technology

Technical Field

The invention relates to the technical field of integrated circuit design, in particular to a four-node flip latch resistant latch circuit (QNURDL latch) based on a reinforcement technology and a module based on the four-node flip latch resistant latch circuit package.

Background

With the progress of the world technology level and the vigorous development of aerospace industry in various countries, the on-orbit working time of the spacecraft is also increased. The environment of the outer space is different from the earth, and the main thing is that the outer space is not protected by the atmosphere, and the spacecraft can work in various ray radiation environments for a long time by exposing, so that the electronic chips in the electronic equipment can be influenced, and some reactions can be caused, so that the working state of the spacecraft can be changed.

The radiation environment is the greatest threat to normal operation of the spacecraft, with single event upset (SINGLE EVENT Upset, SEU) caused by the radiation environment being the greatest cause of failure of the spacecraft. However, in highly integrated nano CMOS technology, due to charge sharing, high energy impinging particles can change the logic states of adjacent dual and even tri-nodes simultaneously, resulting in multi-node flipping (MNU), including dual node flipping (DNU), tri-node flipping (TNU), and quad-node flipping (QNU).

In order to improve the resistance of the unit to multi-node flipping, the prior art mainly includes the following schemes:

1) The C-unit based structure unit (LCTNURL latch for short) shown in FIG. 1 has 12 nodes in total, and the radiation resistance of the circuit is improved in a mode of interlocking different C units. However, the fast data channel is not adopted to reduce the transmission delay, so the circuit delay is larger, and the circuit does not have the capability of resisting four-node overturn.

2) An inverter-based structure unit (LCTNUT latch for short) as shown in fig. 2, which has a relatively small number of tubes and thus low power consumption, has 11 nodes in total and has a three-node flip-flop resistance by interlocking between different inverters, and has a low delay due to the fact that the transmission gate is used to reduce the transmission delay. Although the circuit performance is superior, the four-node flip-flop resistance is not provided.

3) The C-cell based structure shown in fig. 3 (SCLCRL LATCH for short) has 14 nodes in total, and improves the radiation resistance of the circuit by interlocking between different C-cells, the structure has three-node flip resistance, the number of tubes used in the circuit is relatively small, so the power consumption is low, and the structure adopts a fast data channel to reduce the transmission delay, so the circuit delay is smaller than that of the circuit in fig. 1, but the circuit does not have four-node flip resistance.

4) As shown in fig. 4, a C-cell-based structure unit (abbreviated as LSEDUT latch) is provided, in which a C-cell and an inverter are connected to each other, to improve the resistance performance of a node, and finally, a C-cell with a multi-stage input is used to output, and the circuit uses a transmission gate to reduce the delay of a circuit, and uses a clocked C-cell and an inverter to reduce the contention of data stored in a pipe in a transparent mode. Although the circuit has smaller delay and resistance to four-node inversion, the circuit uses more pipes and consumes larger power.

Disclosure of Invention

Based on the above, it is necessary to provide a four-node flip latch circuit and module based on reinforcement technology, aiming at the problem that the existing latch cannot achieve better matching in the node flip resistance, the power consumption index, the area overhead and the delay index.

The invention is realized by adopting the following technical scheme:

in a first aspect, the invention provides a four-node flip latch based on reinforcement technology, which comprises a pull-up tube part, a pull-down tube part, an inverter I, an inverter II, a transmission tube part, a C unit part and a transmission gate.

The pull-up transistor portion includes 18 PMOS transistors P1-P12, P14, P15, P18, P19, P22, P23 for pulling up the storage nodes X0-X11. The pull-down pipe part comprises 6 PMOS pipes P13, P16, P17, P20, P21, P24 and 12 NMOS pipes N1-N12, and is used for pulling down storage nodes X0-X11. Wherein X0, X3, X4, X7, X8 and X11 are all surrounded by PMOS transistors to form a polar reinforcement, and P2 and P14, P3 and P15, P6 and P18, P7 and P19, P10 and P22, and P11 and P23 form a source isolation reinforcement.

The inverter one includes 1 NMOS transistor N39, 1 PMOS transistor P39 for inverting the input signal D into the inverted input signal DN. The inverter II includes 1 NMOS transistor N40 and 1 PMOS transistor P40 for inverting the clock signal CLK to the inverted clock signal CLKB.

The transmission tube portion includes 12 NMOS transistors N13-N24, each connected to CLK. Wherein, X0, X2, X4, X6, X8 and X10 are correspondingly connected with D through N13, N15, N17, N19, N21 and N23, and X1, X3, X5, X7, X9 and X11 are correspondingly connected with DN through N14, N16, N18, N20, N22 and N24.

The C unit part comprises a C unit I, a C unit II, a C unit III, a C unit IV, a C unit five and a C unit six. The first C unit includes 2 PMOS transistors P25, P26 and 2 NMOS transistors N25, N26 for outputting the intermediate signal X12 according to X3, X5. The second C unit includes 2 PMOS transistors P27, P28 and 2 NMOS transistors N27, N28 for outputting the intermediate signal X13 according to X7, X9. The C unit three includes 2 PMOS transistors P29, P30, 2 NMOS transistors N29, N30 for outputting the intermediate signal X14 according to X11, X1. The C unit four includes 2 PMOS transistors P31, P32, 2 NMOS transistors N31, N32 for outputting the intermediate signal X15 according to X12, X13. The C unit five includes 2 PMOS transistors P33, P34, 2 NMOS transistors N33, N34 for outputting the intermediate signal X16 according to X13, X14. The C unit six comprises 3 PMOS transistors P35-P37 and 3 NMOS transistors N35-N37 for outputting an output signal Q according to X15, X16, CLK and CLKB.

The transfer gate includes 1 NMOS transistor N38, 1 PMOS transistor P38 for turning on or off according to CLK. When clk=1, the transfer gate is open, the anti-four node flip latch is transparent, and D outputs Q directly through the transfer gate. When clk=0, the transfer gate is turned off, the latch circuit is turned on in the hold mode, D, DN is stored in X0, X1, X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, and Q is output through the C cell portion.

Implementation of such a four-node flip-latch resistant latch circuit based on reinforcement techniques is in accordance with methods or processes of embodiments of the present disclosure.

In a second aspect, the invention discloses a four-node flip-latch resistant latch module, which is packaged by adopting the four-node flip-latch resistant latch circuit disclosed in the first aspect.

Implementation of such a four-node flip-latch resistant module is in accordance with methods or processes of embodiments of the present disclosure.

Compared with the prior art, the invention has the following beneficial effects:

the circuit of the invention has complete SNU, DNU, TNU, QNU resistance, lower delay, lower power consumption and smaller area.

2, The storage nodes X0, X3, X4, X7, X8 and X11 are all surrounded by PMOS transistors to form polarity reinforcement, so that even if space particles bombard the sensitive node PMOS transistors, only positive pulses of '1-1' and '0-1' are generated on the X0, X3, X4, X7, X8 and X11, and the pulses cannot influence the states of other transistors due to the existence of gate capacitors, and the overturn of the X0, X3, X4, X7, X8 and X11 is effectively avoided.

The invention uses source isolation technology to make the storage nodes X1, X2, X5, X6, X9 and X10 generate only voltage pulses of 1-0 and 0-0, which can effectively reduce the number of sensitive nodes of the circuit and improve the stability of the circuit, and if other non-critical nodes are bombarded by particles, the whole circuit is less susceptible.

The invention constructs C unit part with multiple stages of inputs, which effectively improves radiation resistance of circuit, when the inputs are identical, the output is the opposite phase of the input, when the inputs are not identical, the output keeps the last value unchanged, and can cooperate to ensure correct output of Q when multiple nodes are bombarded.

Drawings

In order to more clearly illustrate the embodiments of the invention or the technical solutions of the prior art, the drawings which are used in the description of the embodiments or the prior art will be briefly described, it being obvious that the drawings in the description below are only some embodiments of the invention, and that other drawings can be obtained from these drawings without inventive faculty for a person skilled in the art.

FIG. 1 is a circuit diagram of LCTNURL latch mentioned in the background of the invention;

FIG. 2 is a circuit diagram of LCTNUT latch mentioned in the background of the invention;

FIG. 3 is a circuit diagram of SCLCRL LATCH mentioned in the background of the invention;

FIG. 4 is a circuit diagram of LSEDUT latch mentioned in the background of the invention;

FIG. 5 is a circuit configuration diagram of QNURDL latch provided in embodiment 1 of the present invention;

FIG. 6 is a timing diagram of the single, dual, and three node bombardment resistant waveforms of QNURDL latch of FIG. 5;

FIG. 7 is a timing waveform diagram of the four-node bombardment resistance of QNURDL latch of FIG. 5;

FIG. 8 is a graph of delay time versus the QNURDL latch and four other latches of FIG. 5;

FIG. 9 is a graph of static power consumption versus QNURDL latch and the other four latches of FIG. 5.

Detailed Description

The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.

It is noted that when an element is referred to as being "mounted to" another element, it can be directly on the other element or intervening elements may also be present. When an element is referred to as being "disposed on" another element, it can be directly on the other element or intervening elements may also be present. When an element is referred to as being "secured to" another element, it can be directly secured to the other element or intervening elements may also be present.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "or/and" as used herein includes any and all combinations of one or more of the associated listed items.

Example 1

Referring to fig. 5, a circuit configuration diagram of QNURDL latch provided in embodiment 1 is shown. Generally, TNURH latch include 40 NMOS tubes, 40 PMOS tubes. The 40 NMOS transistors are sequentially designated as N1-N40, and the 40 PMOS transistors are sequentially designated as P1-P40.

Functionally, TNURH latch includes a pull-up tube section, a pull-down tube section, an inverter one, an inverter two, a transfer tube section, a C cell section, and a transfer gate.

The 18 PMOS transistors P1 to P12, P14, P15, P18, P19, P22, and P23 are used as pull-up transistors to form pull-up transistor portions, and pull-up storage nodes X0 to X11. The 6 PMOS tubes P13, P16, P17, P20, P21, P24 and 12 NMOS tubes N1-N12 are used as pull-down tubes to form pull-down tube parts, and pull down storage nodes X0-X11.

Specifically, the sources of P1-P12 are connected with VDD, and the sources of N1-N12 are grounded GND;

X0 is connected with the drain electrode of P1, the source electrode of P13, the grid electrode of P2, the grid electrode of P4 and the source electrode of N13;

x1 is connected with the grid electrode of N1, the drain electrode of P14, the drain electrode of N2, the grid electrode of P15, the grid electrode of N3, the grid electrode of P16, the source electrode of N14, the grid electrode of P30 and the grid electrode of N29;

X2 is connected with the grid electrode of P13, the grid electrode of P14, the grid electrode of N2, the drain electrode of P15, the drain electrode of N3, the grid electrode of N4 and the source electrode of N15;

x3 is connected with the grid electrode of P1, the grid electrode of P3, the drain electrode of P4, the source electrode of P16, the source electrode of N16, the grid electrode of P25 and the grid electrode of N26;

X4 is connected with the drain electrode of P5, the source electrode of P17, the grid electrode of P6, the grid electrode of P8 and the source electrode of N17;

x5 is connected with the grid electrode of N5, the drain electrode of P18, the drain electrode of N6, the grid electrode of P19, the grid electrode of N7, the grid electrode of P20, the source electrode of N18, the grid electrode of P26 and the grid electrode of N25;

x6 is connected with the grid electrode of P17, the grid electrode of P18, the grid electrode of N6, the drain electrode of P19, the drain electrode of N7, the grid electrode of N8 and the source electrode of N19;

x7 is connected with the grid electrode of P5, the grid electrode of P7, the drain electrode of P8, the source electrode of P20, the source stage of N20, the grid electrode of P27 and the grid electrode of N28;

X8 is connected with the drain electrode of P9, the source electrode of P21, the grid electrode of P10, the grid electrode of P12 and the source electrode of N21;

X9 is connected with the grid electrode of N9, the drain electrode of P22, the drain electrode of N10, the grid electrode of P23, the grid electrode of N11, the grid electrode of P24, the source electrode of N22, the grid electrode of P28 and the grid electrode of N27;

X10 is connected with the grid electrode of P21, the grid electrode of P22, the grid electrode of N10, the drain electrode of P23, the drain electrode of N11, the grid electrode of N12 and the source electrode of N23;

X11 connects the gate of P9, the gate of P11, the drain of P12, the source of P24, the source of N24, the gate of P29, the gate of N30.

The storage part is formed by the upper tube drawing part and the lower tube drawing part, and can be divided into three storage subunits with the same structure, as shown in fig. 5, X0-X3 are positioned in a first storage subunit, X4-X7 are positioned in a second storage subunit, and X8-X11 are positioned in a third storage subunit.

The above adopts polarity reinforcement and source isolation reinforcement:

X0, X3, X4, X7, X8, X11 are all surrounded by PMOS transistors forming a polarity reinforcement, more specifically referred to as a P-type polarity reinforcement structure. According to the polarity reinforcing principle, the space particles bombard the sensitive node PMOS tube, and only voltage pulses of 1-1 and 0-1 are generated on X0, X3, X4, X7, X8 and X11, namely only forward pulses are generated, and the states of other transistors cannot be influenced by the pulses due to the existence of gate capacitors, so that the overturn of X0, X3, X4, X7, X8 and X11 is effectively avoided.

The P2 and P14 stacks, i.e., the uppermost PMOS transistor is isolated from the underlying PMOS transistor using shallow trench isolation techniques, forming a source isolation reinforcement. P3 and P15, P6 and P18, P7 and P19, P10 and P22, and P11 and P23 also form source isolation reinforcements in the same way. Only the voltage pulses of '1-0' and '0-0' are generated on X1, X2, X5, X6, X9 and X10, namely only negative pulse is generated, and the pulse cannot influence the states of other transistors due to the existence of gate capacitance, so that the overturn of X1, X2, X5, X6, X9 and X10 is effectively avoided.

The 1 NMOS transistor N39 and the 1 PMOS transistor P39 form an inverter I for inverting the input signal D into the inverted input signal DN, and the 1 NMOS transistor N40 and the 1 PMOS transistor P40 form an inverter II for inverting the clock signal CLK into the inverted clock signal CLKB.

Specifically, the source electrode of P39 is connected with VDD, the gate electrode is connected with D, the drain electrode is connected with DN, the source electrode of N39 is grounded GND, the gate electrode is connected with the gate electrode of P39, and the drain electrode is connected with the drain electrode of P39. The source electrode of P40 is connected with VDD, the grid electrode is connected with CLK, the drain electrode is connected with CLKB, the source electrode of N40 is grounded GND, the grid electrode is connected with the grid electrode of P40, and the drain electrode is connected with the drain electrode of P40.

The 12 NMOS transistors N13 to N24 constitute a transmission tube portion. N13 to N24 are all connected with CLK. X0, X2, X4, X6, X8 and X10 are correspondingly connected with D through N13, N15, N17, N19, N21 and N23, and X1, X3, X5, X7, X9 and X11 are correspondingly connected with DN through N14, N16, N18, N20, N22 and N24.

Specifically, the drain connection D, the gate connection CLK, the source connection X0 of N13, the drain connection DN, the gate connection CLK, the source connection X1 of N14, the drain connection D, the gate connection CLK, the source connection X2 of N15, the drain connection DN, the gate connection CLK, the source connection X3 of N16, the drain connection D, the gate connection CLK, the source connection X4 of N17, the drain connection DN, the gate connection CLK, the source connection X5 of N18, the drain connection D, the gate connection CLK, the source connection X6 of N19, the drain connection DN, the gate connection CLK, the source connection X7 of N20, the drain connection D, the gate connection CLK, the source connection X8 of N21, the drain connection DN, the gate connection CLK, the drain connection D, the gate connection CLK of N9 of N23, the source connection X10 of N24, the drain connection DN, the gate connection CLK, the source connection X11 of N11.

The C cell portion includes six C cells. Wherein, 2 PMOS transistors P25, P26 and 2 NMOS transistors N25, N26 constitute a C unit one (abbreviated as CE 1) for outputting the intermediate signal X12 according to X3, X5. The 2 PMOS transistors P27, P28 and the 2 NMOS transistors N27, N28 constitute a C-cell two (abbreviated as CE 2) for outputting the intermediate signal X13 according to X7, X9. The 2 PMOS transistors P29, P30 and the 2 NMOS transistors N29, N30 constitute a C-cell three (abbreviated as CE 3) for outputting the intermediate signal X14 according to X11, X1. The 2 PMOS transistors P31, P32 and the 2 NMOS transistors N31, N32 constitute a C unit four (abbreviated as CE 4) for outputting the intermediate signal X15 according to X12, X13. The 2 PMOS transistors P33, P34 and the 2 NMOS transistors N33, N34 constitute a C unit five (abbreviated as CE 5) for outputting the intermediate signal X16 according to X13, X14. The 3 PMOS transistors P35-P37 and the 3 NMOS transistors N35-N37 form a C unit six (called CE6 for short) for outputting an output signal Q according to X15, X16, CLK and CLKB.

When the input values of the C units are the same, the C units serve as inverters, namely when all the input values of the C units are the same, the output values of the C units are the inversions of the input values. But when the input value of the C cell changes, its output may temporarily hold the previous value (enter a high impedance state). This means that if the change in the value input by the C-unit is caused by an error, the C-unit can intercept this error.

The specific connection relation of the C unit part is as follows:

The source electrode of P25 is connected with VDD, the grid electrode is connected with X3, the source electrode of P26 is connected with the drain electrode of P25, the grid electrode is connected with X5, the drain electrode of N25 is connected with the drain electrode of P26, the grid electrode is connected with the grid electrode of P26, the source electrode of N26 is connected with GND, the grid electrode is connected with the grid electrode of P25, and the drain electrode is connected with the source electrode of N25.

The source electrode of P27 is connected with VDD, the grid electrode is connected with X7, the source electrode of P28 is connected with the drain electrode of P27, the grid electrode is connected with X9, the drain electrode of N27 is connected with the drain electrode of P28, the grid electrode is connected with the grid electrode of P28, the source electrode of N28 is connected with GND, the grid electrode is connected with the grid electrode of P27, and the drain electrode is connected with the source electrode of N27.

The source electrode of P29 is connected with VDD, the grid electrode is connected with X11, the source electrode of P30 is connected with the drain electrode of P29, the grid electrode is connected with X1, the drain electrode of N29 is connected with the drain electrode of P30, the grid electrode is connected with the grid electrode of P30, the source electrode of N30 is connected with GND, the grid electrode is connected with the grid electrode of P29, and the drain electrode is connected with the source electrode of N29.

The source electrode of P31 is connected with VDD, the grid electrode is connected with X12, the source electrode of P32 is connected with the drain electrode of P31, the grid electrode is connected with X13, the drain electrode of N31 is connected with the drain electrode of P32, the grid electrode is connected with the grid electrode of P32, the source electrode of N32 is connected with GND, the grid electrode is connected with the grid electrode of P31, and the drain electrode is connected with the source electrode of N31.

The source electrode of P33 is connected with VDD, the grid electrode is connected with X13, the source electrode of P34 is connected with the drain electrode of P33, the grid electrode is connected with X14, the drain electrode of N33 is connected with the drain electrode of P34, the grid electrode is connected with the grid electrode of P34, the source electrode of N34 is connected with GND, the grid electrode is connected with the grid electrode of P33, and the drain electrode is connected with the source electrode of N33.

The source electrode of P35 is connected with VDD, the gate electrode is connected with X15, the source electrode of P36 is connected with the drain electrode of P35, the gate electrode is connected with X16, the source electrode of P37 is connected with the drain electrode of P36, the gate electrode is connected with CLK, the drain electrode of N35 is connected with the drain electrode of P37, the gate electrode is connected with CLKB, the gate electrode of N36 is connected with the gate electrode of P36, the drain electrode is connected with the source electrode of N35, the source electrode of N37 is connected with GND, the gate electrode is connected with the gate electrode of P35, and the drain electrode is connected with the source electrode of N36.

1 NMOS transistor N38, 1 PMOS transistor P38 constitute a transmission gate for turning on or off according to CLK, thereby reducing D to Q delay:

Specifically, the gate of N38 is connected to CLK, the drain is connected to D, the source is connected to Q, the gate of P38 is connected to CLKB, the drain is connected to the source of N38, and the source is connected to the drain of N38.

When clk=1, the transmission gate is open, QNURDL latch is in transparent mode, D outputs Q directly through the transmission gate, so P19, N17 are closed at this time. Taking d=0 as an example, when x0=x2=x4=x6=x8=x10=0, x1=x3=x5=x7=x9=x11=1, P2, P4, P6, P8, P10, P12, P13, P14, P17, P18, P21, P22, N1, N3, N5, N7, N9, N11 are opened, P1, P3, P5, P7, P9, P11, P15, P16, P19, P20, P23, P24, N2, N4, N6, N8, N10, N12 are closed, and thus the feedback loop is rapidly established, which can latch these internal storage nodes so that these storage values remain unchanged unless D rises to 1.

When clk=0, the transfer gate is turned off, QNURDL latch is in the hold mode, D, DN is stored in X0, X1, X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, Q is output through the C unit portion, N13 to N24 are turned off, and the transfer tube portion is not written with a value, so that the previous stored value of each node in the interior is kept unchanged, and the path from D to Q is interrupted. The C cell portion is enabled and the corresponding stored value is output to Q through the C cell portion, so the latch value on Q will be retained until the next transparent mode occurs.

Bombardment occurs in the hold mode (clk=0, clkb=1, when P37, N35 is on in CE 6). In general, QNURDL latch either restores the storage node when it is bombarded, or fault tolerance is performed by the action of the C unit (mainly CE1, CE2, CE3, CE4, CE 5) even if some storage nodes cannot be restored, ensuring the correct output of Q.

In general, the three storage subunits corresponding to X0-X11 are consistent, so that the sensitivity degree of the internal storage node corresponding to each storage subunit is also consistent, and therefore, X0-X11 belong to the same type of storage node, namely the internal storage node. X12-X14 are all generated by internal storage nodes, so the three nodes belong to the same type of storage node, namely an intermediate storage node. X15 and X16 are generated by the intermediate storage nodes, so that the two nodes belong to the same type of storage node, namely a regeneration storage node. Q is a single type of node-the output node.

In this embodiment 1, the gate lengths of all the MOS transistors are 65nm, the gate widths of P13, P16, P17, P20, P21, P24, N1, N4, N5, N8, N9, N12 are 420nm, and the gate widths of all the other MOS transistors are 140nm.

For QNURDL latch anti-flip capability, taking the example of stored data x0=x2=x4=x6=x8=x10=0, x1=x3=x5=x7=x9=x11=1, P2, P4, P6, P8, P10, P12, P13, P14, P17, P18, P21, P22, N1, N3, N5, N7, N9, N11 are turned on, P1, P3, P5, P7, P9, P11, P15, P16, P19, P20, P23, P24, N2, N4, N6, N8, N10, N12 are turned off. In this state QNURDL latch has a total of 12 sensitive nodes, X0, X1, X4, X5, X8, X9, X12, X13, X14, X15, X16, Q, respectively.

(1) The bombardment is carried out on X0, X1, X4, X5, X8, X9, X12, X13, X14, X15, X16 and Q respectively and independently, and the total number of the cases is 12, and the cases can be divided into four main categories according to the node types. The results show that recovery can be achieved, so that the correct output of Q can be ensured. The TNURH latch shows complete resistance to SNU.

Class 1.1 i.e. the internal storage nodes are bombarded.

Taking X0 as an example, when X0 is bombarded, turning from "0" to "1" will cause P2 and P4 to be turned off. However, since the states of the pull-up pipe P15 and the pull-down pipe N3 of X2 are not changed, the stored value of X2 is not changed. Considering that the states of the pull-up tube P14 and the pull-down tube N2 of the node X1 and X1 will not change, so that the stored value of X1 will not be affected, and similarly the states of the pull-down tubes P16 and N4 of X3 will not change, so that the pull-up tube P1 of X0 remains closed, the pull-down tubes P13 and N1 of X0 remain open, X0 will discharge through the pull-down tubes P13 and N1, and return to the correct logic value "0" again, and the error will not affect the correctness of the output Q value.

Taking X1 as an example, when X1 is bombarded, turning from "1" to "0" will cause P15 and P16 to open and N1 and N3 to close, but X0, X2, X3 are unchanged from the other pull-up and pull-down tubes, so that the three storage node values are unchanged, the pull-down tube N2 of X1 continues to be closed, the pull-up tubes P2 and P14 of X1 continue to remain open, and X1 returns from the error value "0" to the correct value "1".

The remaining similar cases are not described in detail.

Class 1.2. Intermediate storage nodes are bombarded.

Taking X12 as an example, when X12 is bombarded, the transition from "0" to "1" will not affect the values of other nodes, and the inputs X3 and X5 of X12 will not have a transition in error, so X12 will be pulled back by X3 and X5 to the correct logic value "0", so the error will not affect the output Q value.

The remaining similar cases are not described in detail.

Class 1.3. Regeneration storage nodes are bombarded.

Taking X15 as an example, when X15 is flipped from "1" to "0", the error will not affect other nodes, but the inputs X12 and X13 of X15 are not flipped, so X15 will be pulled back to the correct logic value "1" by X12 and X13, so the error will not affect the output Q value.

The remaining similar cases are not described in detail.

Class 1.4 output nodes are bombarded. When Q is bombarded, the transition from "0" to "1" will not affect the values of other nodes, and the inputs X15 and X16 of Q will not have the transition in error, so Q will be pulled back to the correct logic value "0" by X15 and X16, so even if the SNU occurs in Q, it will be pulled back to the correct output value by other nodes again.

As shown in FIG. 6, the four above cases are shown, specifically in Table one.

Table 1 cases after Single node bombardment

(2) As shown in fig. 6, the bombardment was performed on any two points of X0, X1, X4, X5, X8, X9, X12, X13, X14, X15, X16, Q, and the total 66 cases were divided into three major categories. The results show that recovery can be achieved, so that the correct output of Q can be ensured. The TNURH latch can be completely anti-DNU.

For convenience of explanation, the intermediate storage node, the regenerated storage node, and the output node are collectively referred to as external nodes.

Class 2.1. Two internal storage nodes are flipped and the external node is not flipped.

Class 2.1 is divided into two subclasses:

The first is that two nodes are in the same storage subunit, in this case, the internally flipped node cannot be recovered, but the whole circuit outputs through the C unit part, so that the error flip of the output Q is not caused, and taking the < X0, X1> node pair flip as an example, when X0 is flipped from 0 to 1 and X1 is flipped from 1 to 0, the logic disorder in the first storage subunit where X0 and X1 are located is caused, and the two nodes cannot recover the correct value, but the error is not transferred to Q because of the interception of the error by CE 1-CE 6, so that the Q still maintains the correct logic value. The remaining similar cases are not described in detail.

The second is that two nodes are located in two different storage subunits, and the storage subunits can resist any single-node overturn, so that the overturned nodes can recover by the internal circuit, and the correctness of the output node Q is not affected.

Class 2.2, one internal storage node flipped and one external node flipped.

Taking the example of the node pair inversion of < X0, X12>, assuming that X0 is inverted from "0" to "1", X12 is inverted from "0" to "1", the anti-SNU analysis shows that the inversion of X0 can restore itself and does not cause logic disorder of other storage nodes, X12 is controlled by X3 and X5, and the two nodes are not inverted, so that the inverted X12 is pulled back to the correct "0" from the wrong "1", and therefore the inversion of the two nodes does not transfer the wrong value to Q, and Q still maintains the correct logic value. The remaining similar cases are not described in detail.

Class 2.3 internal storage node is not flipped and two external nodes are flipped.

Taking the example of the node pair inversion of < X12, X13>, assuming that X12 is inverted from "0" to "1" and X13 is inverted from "0" to "1", the two nodes are taken as the input node pair of CE4, and the inversion can cause the logic value of X15 to be inverted, but since one input value is not logically wrong in the inputs of CE5 and CE6, the outputs of the two C units cannot be wrong, namely, the wrong inversion of the node pair cannot be transmitted to Q, and the Q still keeps the correct output. And X12 and X13 are controlled by X3, X5 and X7, X9, respectively, and their inputs are not wrong, so the correct input value will pull it back to the correct logic value.

As shown in FIG. 6, the three general cases are shown, see Table II.

Cases after the table dual-node is bombarded

(3) As shown in fig. 6, four kinds of bombardment were performed on any three points of X0, X1, X4, X5, X8, X9, X12, X13, X14, X15, X16, and Q, and 220 kinds of cases were divided into four kinds. The results show that recovery can be achieved, so that the correct output of Q can be ensured. This indicates TNURH latch that complete anti-TNU was possible.

For convenience of explanation, the intermediate storage node, the regenerated storage node, and the output node are collectively referred to as external nodes.

Class 3.1 three internal storage nodes are flipped and the external nodes are not flipped.

Class 3.1 is divided into two subclasses:

The first is that three flip nodes are located in two storage subunits. Taking < X0, X1, X4> as an example, assuming that X0 is flipped from "0" to "1", X1 is flipped from "1" to "0", and X4 is flipped from "0" to "1", in the first storage subunit where X0, X1 are located, two sensitive nodes are flipped together, there is no way to perform self-recovery inside the unit, and in the second storage subunit where X4 is located, only one sensitive node is flipped, so that the inside of the unit can perform self-recovery. However, since the output terminal relies on the C unit to perform error blocking, whether or not recovery is performed, the error is eventually filtered by the C unit without affecting the accuracy of Q. The remaining similar cases are not described in detail.

The second case is where three flip nodes are located in three storage subunits. Taking < X0, X4, X8> as an example, assuming that X0 is turned from "0" to "1", X4 is turned from "0" to "1", and X8 is turned from "0" to "1", the three turned nodes can recover themselves in the storage sub-units where they are located, and finally the correctness of Q is not affected. The remaining similar cases are not described in detail.

Class 3.2 two internal storage nodes are flipped and one external node is flipped.

Two classes of internal storage node inversion are also described in anti-DNU, and only one of them is taken as an example, and the description is not repeated here:

taking < X0, X1, X12> as an example, assuming that X0 is flipped from "0" to "1", X1 is flipped from "1" to "0", and X12 is flipped from "0" to "1", since X0, X1 are both in the first storage subunit and flipped at the same time, the two nodes cannot self-recover inside the first storage subunit, and X12 is controlled by X3, X5 together, the two nodes are not flipped, so that X12 will be pulled back to the correct value, and the error value of X1 will not affect the correctness of X14 due to the effect of the C unit, so that the error of the whole circuit will not be transferred to Q, i.e., the whole circuit will maintain the correct Q. The remaining similar cases are not described in detail.

Class 3.3 one internal storage node flipped and two external nodes flipped.

Taking < X0, X12, X13> as an example, assume that X0 is flipped from "0" to "1", X12 is flipped from "0" to "1", and X13 is flipped from "0" to "1". As can be seen from SNU resistance analysis, X0 is flipped in the first memory subunit, and self-recovery is enabled, but the inputs of X12 and X13 are not flipped, so that X12 and X13 will be pulled back to the correct values by the correct inputs, and the wrong values will not be transferred to Q, so that the whole circuit will maintain the correct Q. The remaining similar cases are not described in detail.

Class 3.4 internal storage node is not flipped and three external nodes are flipped.

Taking < X12, X13, X14> as an example, assuming that X12 is flipped from "0" to "1", X13 is flipped from "0" to "1", and X14 is flipped from "0" to "1", the node group as the full input of CE4 and CE5 will cause X15 and X16 to flip, and finally Q to flip, but since all input values of the node group are erroneously flipped, the node group will be pulled back to the correct logic value by the correct input, in turn pulling back the flipped X15 and X16 to the correct value, and further pulling back Q to the correct value, so the output of Q remains correct. The remaining similar cases are not described in detail.

As shown in FIG. 6, the four general cases are shown, see Table III in detail.

Cases after three nodes of the table are bombarded

(4) Four points of X0, X1, X4, X5, X8, X9, X12, X13, X14, X15, X16 and Q are bombarded, and 495 cases are divided into five main categories. The results show that recovery can be achieved, so that the correct output of Q can be ensured. The instructions TNURH latch may be fully resistant to QNU.

For convenience of explanation, the intermediate storage node, the regenerated storage node, and the output node are collectively referred to as external nodes.

Class 4.1 four internal storage nodes are flipped and external nodes are not flipped.

Class 4.1 is divided into two subclasses:

The first is that four flip nodes are located in two storage subunits. Taking < X0, X1, X4, X5> as an example, assuming that X0 is turned from "0" to "1", X1 is turned from "1" to "0", X4 is turned from "0" to "1", and X5 is turned from "1" to "0", two sensitive nodes are turned in each storage subunit, and recovery of node values in the unit is impossible, but since Q is based on the output of the C unit portion, an internal error value is intercepted by the C unit portion and is not transferred to Q, and Q maintains correct output. The remaining similar cases are not described in detail.

The second is that four flip nodes are located in three storage subunits. Taking < X0, X1, X4, X8> as an example, assuming that X0 is turned from "0" to "1", X1 is turned from "1" to "0", X4 is turned from "0" to "1", and X8 is turned from "0" to "1", two sensitive nodes in the first storage subunit where X0 and X1 are located are turned at the same time, self-recovery cannot be performed inside, and the second storage subunit where X4 is located and the third storage subunit where X8 is located are all turned only one sensitive node, so self-recovery can be performed inside. An internal unrecoverable flip error is intercepted by the C cell portion of the multi-stage input, the error value is not transferred to Q, and Q remains correctly output. The remaining similar cases are not described in detail.

Class 4.2 three internal storage nodes are flipped and one external node is flipped.

The case of three internal storage nodes flipped is referred to as class 3.1 and is not repeated here, only one of which is taken as an example:

taking < X0, X1, X4, X12> as an example, assuming that X0 is flipped from "0" to "1", X1 is flipped from "1" to "0", X4 is flipped from "0" to "1", and X12 is flipped from "0" to "1", since X0, X1 are in the first memory subunit and are flipped at the same time, the two nodes cannot self-recover inside the first memory subunit. In the second storage subunit where X4 is located, only one sensitive node is flipped, so that the inside of the second storage subunit can be recovered. X12 is commonly controlled by X3, X5, and the two nodes do not flip, so X12 is pulled back to the correct value. The Q output is still correct because the internal unrecoverable error is not output to Q due to the obstruction of the multi-stage input C cell. The remaining similar cases are not described in detail.

Class 4.3 two internal storage nodes are flipped and two external nodes are flipped.

The case of two internal storage nodes flipped is referred to as class 2.1 and is not repeated here, only one of which is taken as an example:

taking < X0, X1, X12, X13> as an example, assuming that X0 is flipped from "0" to "1", X1 is flipped from "1" to "0", X12 is flipped from "0" to "1", and X13 is flipped from "0" to "1", since X0, X1 are in the same memory subunit and flipped at the same time, the two nodes cannot self-recover within the memory Chu Zi units. None of the outputs X3, X5 and X13 of X12, X7 and X9, are wrong, so the two nodes will be pulled back to the correct value by the correct input value, and eventually Q will also remain correct. The remaining similar cases are not described in detail.

Class 4.4. One internal storage node flipped and three external nodes flipped.

Taking < X0, X12, X13, X14> as an example, X12, X13, X14 as the full inputs to CE4 and CE5 would result in X15 and X16 flipping, and finally Q flipping. However, according to the SNU resistance analysis, the X0 is flipped in the storage subunit of the first storage subunit, so that the self-recovery can be performed, and the correct values of other nodes are not affected, that is, all the inputs of X12 to X14 are correct values, so that the correct logic values of X12 to X14 will be pulled back by the correct inputs, and the flipped X15 and X16 will be pulled back to the correct values in turn, so that the Q is pulled back to the correct values, and the output of Q is still correct. The remaining similar cases are not described in detail.

Class 4.5 internal storage nodes are not flipped and four external nodes are flipped.

Taking < X12, X13, X14, X15> as an example, assuming that X12 is turned from "0" to "1", X13 is turned from "0" to "1", X14 is turned from "0" to "1", and X15 is turned from "1" to "0", Q will be turned when the turning occurs, but since no turning occurs in CE1 to CE3, X12, X13, X14, X15, X16 will be pulled back to the correct value in order, and finally Q will be output correctly.

As shown in FIG. 7, the five general cases described above are illustrated, see Table IV in particular.

Cases after four nodes of the table are bombarded

In addition, the inventor also carries out simulation comparison on TNURH latch latches with 4 latches proposed in the background technology.

First, refer to Table five, which is a comparative table of anti-roll over capability.

Table five-antibody turnover capacity comparison table

It is apparent that only LSEDUT latch and QNURDL latch possess full SNU/DNU/TNU/QNU resistance. However, LSEDUT latch total MOS tubes are required to be built, while TNURH latch only requires 80 MOS tubes, so that the area cost is obviously reduced.

Then, referring to FIG. 8, the delay of QNURDL latch is close to LSEDUT latch, slightly greater than LCTNUT latch, much less than LCTNURL latch, SCLCRL LATCH. The QNURDL latch also has the advantage of low latency with full anti-SNU/DNU/TNU/QNU capability.

Referring again to FIG. 9, QNURDL latch consumes less power than LSEDUT latch, although greater than LCTNURL latch, LCTNUT latch, SCLCRL LATCH. The QNURDL latch also has the advantage of low power consumption with full anti-SNU/DNU/TNU/QNU capability.

In addition, the delay power consumption product of LSEDUT latch and QNURDL latch was compared, and the delay power consumption product of LSEDUT latch and 6.58181,QNURDL latch was 5.89107, respectively. It is appreciated that a portion of the delay sacrificed by QNURDL latch may result in a greater reduction in power consumption, and therefore QNURDL latch may also be advantageous over LSEDUT latch.

Example 2

The embodiment 2 discloses a four-node flip latch resistant module, which is formed by packaging the four-node flip latch resistant circuit of the embodiment 1. The mode of packaging into a module is easier to popularize and apply the four-node flip latch resistant circuit.

The pins of the four-node flip latch resistant module comprise 5 pins, namely a first pin, a second pin, a third pin, a fourth pin and a fifth pin.

The first pin is used to connect VDD. Specifically, the first pins are connected to the sources of P1-P12.

The second pin is used for grounding GND. Specifically, the second pins are connected to the sources of N1-N12.

The third pin is used for inputting a clock signal CLK. Specifically, the third pin is connected to the gates of N38, P40, N40, P37, N13-N24.

The fourth pin is used for inputting an input signal D. Specifically, the fourth pin is connected with the drain electrode of N38 and the source electrode of P38, the fourth pin is connected with the grid electrodes of P39 and N39, and the fourth pin is connected with the source electrodes of N13, N15, N17, N19, N21 and N23.

The fifth pin is used for outputting an output signal Q. Specifically, the fifth pin is connected to the drains of P37 and N35.

The technical features of the above-described embodiments may be arbitrarily combined, and all possible combinations of the technical features in the above-described embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.

The above examples illustrate only a few embodiments of the invention, which are described in detail and are not to be construed as limiting the scope of the invention. It should be noted that it will be apparent to those skilled in the art that several variations and modifications can be made without departing from the spirit of the invention, which are all within the scope of the invention. Accordingly, the scope of protection of the present invention is to be determined by the appended claims.

Claims (10)

1. A four-node flip latch resistant latch based on reinforcement techniques, comprising:

The pull-up tube part comprises 18 PMOS transistors P1-P12, P14, P15, P18, P19, P22 and P23 and is used for pulling up storage nodes X0-X11;

A pull-down transistor section including 6 PMOS transistors P13, P16, P17, P20, P21, P24, and 12 NMOS transistors N1 to N12 for pulling down the storage nodes X0 to X11;

Wherein X0, X3, X4, X7, X8 and X11 are all surrounded by PMOS transistors to form a polar reinforcement, P2 and P14, P3 and P15, P6 and P18, P7 and P19, P10 and P22, P11 and P23 form a source isolation reinforcement;

an inverter I including 1 NMOS transistor N39, 1 PMOS transistor P39 for inverting the input signal D into an inverted input signal DN;

An inverter II including 1 NMOS transistor N40, 1 PMOS transistor P40 for inverting the clock signal CLK to an inverted clock signal CLKB;

The transmission tube part comprises 12 NMOS transistors N13-N24 which are all connected with CLK, wherein X0, X2, X4, X6, X8 and X10 are correspondingly connected with D through N13, N15, N17, N19, N21 and N23, and X1, X3, X5, X7, X9 and X11 are correspondingly connected with DN through N14, N16, N18, N20, N22 and N24;

The C unit part comprises a C unit I, a C unit II, a C unit III, a C unit IV, a C unit V and a C unit VI, wherein the C unit I comprises 2 PMOS transistors P25, P26 and 2 NMOS transistors N25 and N26 and is used for outputting an intermediate signal X12 according to X3 and X5, the C unit II comprises 2 PMOS transistors P27, P28 and 2 NMOS transistors N27 and N28 and is used for outputting an intermediate signal X13 according to X7 and X9, the C unit III comprises 2 PMOS transistors P29, P30 and 2 NMOS transistors N29 and N30 and is used for outputting an intermediate signal X14 according to X11 and X1, the C unit IV comprises 2 PMOS transistors P31, P32 and 2 NMOS transistors N31 and N32 and is used for outputting an intermediate signal X15 according to X12 and X13, the C unit III comprises 2 PMOS transistors P33, P34 and 2 NMOS transistors N33 and N34 and is used for outputting an intermediate signal X13 and X14 according to X7 and X9, and the C unit III comprises 2 NMOS transistors N29 and N30 and is used for outputting an intermediate signal X37 to X3 and a signal X35;

And

The transmission gate comprises 1 NMOS transistor N38 and 1 PMOS transistor P38, and is used for being opened or closed according to CLK, when CLK=1, the transmission gate is opened, the four-node flip latch resistant circuit is in a transparent mode, D directly outputs Q through the transmission gate, when CLK=0, the transmission gate is closed, the four-node flip latch resistant circuit is in a holding mode, D, DN is correspondingly stored in X0, X1, X2, X3, X4, X5, X6, X7, X8, X9, X10 and X11, and Q is output through the C unit part.

2. The four-node flip latch-based reinforcement technology according to claim 1, wherein the sources of P1-P12 are connected to VDD;

X0 is connected with the drain electrode of P1, the source electrode of P13, the grid electrode of P2, the grid electrode of P4 and the source electrode of N13;

x1 is connected with the grid electrode of N1, the drain electrode of P14, the drain electrode of N2, the grid electrode of P15, the grid electrode of N3, the grid electrode of P16, the source electrode of N14, the grid electrode of P30 and the grid electrode of N29;

X2 is connected with the grid electrode of P13, the grid electrode of P14, the grid electrode of N2, the drain electrode of P15, the drain electrode of N3, the grid electrode of N4 and the source electrode of N15;

x3 is connected with the grid electrode of P1, the grid electrode of P3, the drain electrode of P4, the source electrode of P16, the source electrode of N16, the grid electrode of P25 and the grid electrode of N26;

X4 is connected with the drain electrode of P5, the source electrode of P17, the grid electrode of P6, the grid electrode of P8 and the source electrode of N17;

x5 is connected with the grid electrode of N5, the drain electrode of P18, the drain electrode of N6, the grid electrode of P19, the grid electrode of N7, the grid electrode of P20, the source electrode of N18, the grid electrode of P26 and the grid electrode of N25;

x6 is connected with the grid electrode of P17, the grid electrode of P18, the grid electrode of N6, the drain electrode of P19, the drain electrode of N7, the grid electrode of N8 and the source electrode of N19;

x7 is connected with the grid electrode of P5, the grid electrode of P7, the drain electrode of P8, the source electrode of P20, the source stage of N20, the grid electrode of P27 and the grid electrode of N28;

X8 is connected with the drain electrode of P9, the source electrode of P21, the grid electrode of P10, the grid electrode of P12 and the source electrode of N21;

X9 is connected with the grid electrode of N9, the drain electrode of P22, the drain electrode of N10, the grid electrode of P23, the grid electrode of N11, the grid electrode of P24, the source electrode of N22, the grid electrode of P28 and the grid electrode of N27;

X10 is connected with the grid electrode of P21, the grid electrode of P22, the grid electrode of N10, the drain electrode of P23, the drain electrode of N11, the grid electrode of N12 and the source electrode of N23;

X11 connects the gate of P9, the gate of P11, the drain of P12, the source of P24, the source of N24, the gate of P29, the gate of N30.

3. The four-node flip-latch-based reinforcement technique of claim 2, wherein P39 has a source connected VDD, a gate connected D, and a drain connected DN;

the source electrode of N39 is grounded GND, the grid electrode is connected with the grid electrode of P39, and the drain electrode is connected with the drain electrode of P39.

4. The four-node flip-latch-based reinforcement technique of claim 3, wherein P40 has a source connected VDD, a gate connected CLK, and a drain connected CLKB;

the source electrode of the N40 is grounded GND, the grid electrode is connected with the grid electrode of the P40, and the drain electrode is connected with the drain electrode of the P40.

5. The four-node flip-latch-based reinforcement technique of claim 4, wherein,

The drain connection D of N13, the drain connection DN of N14, the gate connection CLK, the drain connection D of N15, the gate connection CLK, the drain connection DN of N16, the gate connection CLK, the drain connection D of N17, the gate connection CLK, the drain connection DN of N18, the gate connection CLK, the drain connection D of N19, the gate connection CLK, the drain connection DN of N20, the gate connection CLK, the drain connection D of N21, the gate connection CLK, the drain connection DN of N22, the gate connection CLK, the drain connection D of N23, the gate connection CLK, the drain connection DN of N24, and the gate connection CLK.

6. The four-node flip latch based on the reinforcement technology according to claim 4, wherein the source of P25 is connected to VDD, the gate is connected to X3, the source of P26 is connected to the drain of P25, the gate is connected to X5, the drain is connected to X12, the drain of N25 is connected to the drain of P26, the gate is connected to the gate of P26, the source of N26 is connected to GND, the gate is connected to the gate of P25, and the drain is connected to the source of N25;

The source electrode of P27 is connected with VDD, the grid electrode is connected with X7, the source electrode of P28 is connected with the drain electrode of P27, the grid electrode is connected with X9, the drain electrode of N27 is connected with the drain electrode of P28, the grid electrode is connected with the grid electrode of P28, the source electrode of N28 is connected with GND, the grid electrode is connected with the grid electrode of P27, and the drain electrode is connected with the source electrode of N27;

The source electrode of P29 is connected with VDD, the grid electrode is connected with X11, the source electrode of P30 is connected with the drain electrode of P29, the grid electrode is connected with X1, the drain electrode of N29 is connected with the drain electrode of P30, the grid electrode is connected with the grid electrode of P30, the source electrode of N30 is connected with GND, the grid electrode is connected with the grid electrode of P29, and the drain electrode is connected with the source electrode of N29;

the source electrode of P31 is connected with VDD, the grid electrode is connected with X12, the source electrode of P32 is connected with the drain electrode of P31, the grid electrode is connected with X13, the drain electrode of N31 is connected with the drain electrode of P32, the grid electrode is connected with the grid electrode of P32, the source electrode of N32 is connected with GND, the grid electrode is connected with the grid electrode of P31, and the drain electrode is connected with the source electrode of N31;

the source electrode of P33 is connected with VDD, the grid electrode is connected with X13, the source electrode of P34 is connected with the drain electrode of P33, the grid electrode is connected with X14, the drain electrode of N33 is connected with the drain electrode of P34, the grid electrode is connected with the grid electrode of P34, the source electrode of N34 is connected with GND, the grid electrode is connected with the grid electrode of P33, and the drain electrode is connected with the source electrode of N33;

the source electrode of P35 is connected with VDD, the gate electrode is connected with X15, the source electrode of P36 is connected with the drain electrode of P35, the gate electrode is connected with X16, the source electrode of P37 is connected with the drain electrode of P36, the gate electrode is connected with CLK, the drain electrode of N35 is connected with the drain electrode of P37, the gate electrode is connected with CLKB, the gate electrode of N36 is connected with the gate electrode of P36, the drain electrode is connected with the source electrode of N35, the source electrode of N37 is connected with GND, the gate electrode is connected with the gate electrode of P35, and the drain electrode is connected with the source electrode of N36.

7. The four-node flip-latch-based reinforcement technique according to claim 6, wherein the gate of N38 is connected CLK, the drain is connected D, and the source is connected Q;

The P38 gate is connected to CLKB, the drain is connected to the source of N38, and the source is connected to the drain of N38.

8. The four-node flip latch based on the reinforcement technology according to claim 1, wherein gate lengths of all MOS transistors are 65nm, gate widths of P13, P16, P17, P20, P21, P24, N1, N4, N5, N8, N9, N12 are 420nm, and gate widths of all other MOS transistors are 140nm.

9. A four-node flip-latch resistant latch module packaged using the four-node flip-latch resistant latch circuit of any one of claims 1-8.

10. The four-node flip-latch resistant to claim 9, wherein pins of the four-node flip-latch resistant to latch comprises:

a first pin for connecting VDD;

A second pin for grounding GND;

a third pin for inputting a clock signal CLK;

A fourth pin for inputting the input signal D, and

And a fifth pin for outputting an output signal Q.