CN115828839A - System-level verification system and method for SOC (System on chip) - Google Patents

Abstract

The invention provides a system level verification system and a method of an SOC chip, which comprises the following steps: a hardware platform top layer, a verification platform and a script file; the verification platform is connected with the top layer of the hardware platform through a GPI interface, completes the excitation drive of the verification platform on hardware in the SOC chip system to be tested, and acquires hardware data; the script file specifies a design code and a verification code in the SOC chip system to be tested and specifies a simulation type; and the top layer of the hardware platform is used for operating hardware in the SOC chip system to be tested. The verification system and the test case are both realized by Python without introducing other languages and scripts, the establishment of a complex UVM verification environment is omitted, the environment is easy to establish, a test method with bus behavior as an excitation inlet and a test method with c program as an excitation inlet can be realized simultaneously, the verification method takes random constraint and coverage rate drive as principles, and the method has the characteristics of flexibility, high efficiency, rapid convergence and high verification efficiency.

Description

System and method for SOC chip system-level verification

technical field

The invention relates to a verification system and method, in particular to a SOC chip system-level verification system and method.

Background technique

IP reuse makes SOC design simpler and faster, but it still needs to be verified at the system level. The traditional testbench cannot achieve flexible random constraints and self-check results. Building a UVM verification environment from 0 requires a lot of time to build a verification platform in the early stage. .

Contents of the invention

Purpose of the invention: The technical problem to be solved by the present invention is to provide a SOC chip system-level verification system and method for the deficiencies of the prior art.

In order to solve the above technical problems, the present invention discloses a SOC chip system-level verification system and method, including: a hardware platform top layer, a verification platform and a script file;

Wherein, the verification platform is connected with the top layer of the hardware platform through the GPI interface, completes the excitation drive of the hardware in the SOC chip system to be tested by the verification platform, and obtains hardware data; the script file specifies the design code and verification in the SOC chip system to be tested code, and specify the emulation type; the top layer of the hardware platform is used to run the hardware in the SOC chip system to be tested.

The top layer of the hardware platform includes: the design to be tested is the SOC chip system to be tested and an external device model; the top layer of the hardware platform runs in an emulator.

The verification platform includes: test cases, incentive models and scoreboards.

The test case includes two types of coroutines, that is, the coroutines of public configuration and the coroutines related to specific functions: the process configuration is performed according to the workflow of different functional modules, and the coroutines access the hierarchical path of hardware signals in the top layer of the hardware platform Complete the drive and acquisition of hardware signals, and usually communicate with the hardware platform at the signal level;

The stimulus model is used for the signal bundle following the set protocol: the communication bus, which completes the driving of the stimulus and the collection of the response according to the interface protocol, and communicates with the hardware platform at the signal bundle level.

The scoreboard judges whether the response data is correct by comparing the similarities and differences between the response data collected from the SOC chip system to be tested and the expected value, gives the mark of whether the test case is passed or not, and prints the conclusion.

Described script file is used for setting test parameter, comprises: by setting the top-level module of SOC chip system to be tested and the file list designation code that contains all codes; Designate the verification code that participates in emulation by the name of definition test case; Through global variable Definitions differentiate between emulation types.

The test parameters set by the script file include: pre-simulation, post-simulation, whether to keep the waveform file and the scale of the regression test.

The test cases are classified according to the scenarios, and the specific methods are as follows:

Verify processor-related scenarios: adopt C+Python, use C language and Python language to construct the operation of the software part and the incentive of the hardware part respectively;

Scenarios that ignore processor participation: skip the cpu startup program in the SOC chip system to be tested, and only use the random constraint characteristics of the cocotb verification framework to build incentives for the hardware part.

A kind of SOC chip system-level verification method adopts a kind of SOC chip system-level verification system to verify, comprising the following steps:

Step 1: Specify the test case by assigning global variables, and start the operation; use the simulation tool to compile the RTL code in the SOC chip system to be tested; run the compiled code to start the simulation, and use the GPI interface to verify the simulation control of the hardware platform by the platform;

Step 2: If the global variable is defined as the CPU participation value, the CPU loads the instruction corresponding to the test case through flash after power-on, and converts it into a hardware behavior; otherwise, reset the CPU to make it stop working, and directly execute the Python in the test case Code, the stimulus source is the bus model to simulate the behavior of the CPU;

Step 3: If the CPU participates, control the CPU to configure the relevant functions of the design under test in the SOC chip system under test according to the verification scenario, and let the CPU respond to feedback information from other devices; if no CPU control is required, in the Python test case Make the SOC chip system under test enter the working mode required by the verification scenario through bus configuration;

Step 4: Generate and send signal-level incentives: According to the scenario and functional requirements, generate random data and send it to the hardware interface through the hierarchical path of the signal in the hardware platform;

Step 5: Generate and send signal bundle excitation: According to the scene and functional requirements, generate random data for each signal in the signal bundle, and drive the excitation data to the corresponding hardware interface of the signal bundle according to the behavior timing requirements defined in the excitation model. Make it meet the behavior specification of the interface;

Step 6: Response collection and judgment, the incentive model collects the response according to the timing requirements, and judges whether the response is the expected data in the scoreboard. If it is correct, it will give the test case pass mark, and wait for all the codes to be executed to end the simulation. If it is wrong, then Print an error message and end the simulation.

Beneficial effect:

In the present invention, both the verification system and the test cases are implemented using Python, without introducing other languages and scripts, and eliminating the need to establish a complicated UVM verification environment. The environment is easy to build, and can simultaneously implement bus behavior as the incentive entry and c program as the excitation entry. The test method, the verification method is based on the principle of random constraints and coverage drive, and has the characteristics of flexibility, high efficiency, fast convergence, and high verification efficiency.

1) The verification system is based on the python language and the cocotb verification framework to achieve the purpose of SOC verification. Verifiers do not need to have SV/UVM verification background. The python/cocotb learning cycle is short and the verification is more efficient.

2) The test cases are divided into two categories according to the functional characteristics of the verification. The use cases that do not require the participation of the CPU use the bus behavior as the injection stimulus, otherwise the stimulus is injected by reading the c program, and the processor is transformed into the hardware behavior of the SOC. The former is skipped The CPU startup process improves the verification efficiency.

3) Create a class for the top-level interface of the SOC, and instantiate the drive or acquisition of the signal directly in the test case, which is more concise and efficient than the interface transmission in UVM.

4) The developed script file can realize many functions, such as specifying the design code, verification code and hardware platform entry, distinguishing the simulation type, such as pre-simulation and post-simulation, and other resource-saving behaviors, such as whether to keep the waveform file, The scale of the regression test, etc., can achieve efficient use of resources on the premise of achieving the purpose of verification.

5) When there is no IP level verification environment, this verification method can quickly verify functions such as bus connection, concurrent access, interrupt connection, interrupt response, clock, and reset.

6) The system is based on the principle of random constraints and coverage-driven technology, and has the characteristics of flexibility, high efficiency, fast convergence, and high verification efficiency.

Description of drawings

The advantages of the above and/or other aspects of the present invention will become clearer as the present invention will be further described in detail in conjunction with the accompanying drawings and specific embodiments.

FIG. 1 is a schematic diagram of the system architecture of the present invention.

Fig. 2 is a schematic flow chart of the verification method in the present invention.

Detailed ways

The present invention proposes a SOC chip system-level verification system and method, wherein:

1. The verification system, as shown in Figure 1:

The system includes the top layer of the hardware platform, verification platform and script files. The verification platform is connected to the top layer of the hardware platform through the GPI interface to realize the incentive drive of the hardware and obtain hardware data. The script file specifies the design code and verification code of the SOC to be tested, and specifies the simulation type. ;

1) The top layer of the hardware platform includes the design to be tested (that is, the SOC chip system to be tested) and the external device model. The top layer of the entire hardware platform runs in the emulator (generally, both the verification platform and the hardware platform run in the emulator, so one side After the code is modified, it needs to be recompiled), such as: VCS. In the present invention, the modification of the verification code will not cause the recompilation of the whole system.

2) The verification platform is written in Python code, including: test cases, incentive models, and scoreboards for result checking; the test cases include multiple coroutines, which are mainly divided into public configuration coroutines and specific function-related coroutines : The work configuration process of different functional modules, the coroutine can realize the driving and collection of hardware signals by accessing the hierarchical path of hardware signals in the hardware platform, and usually communicates with the hardware platform at the signal level; the incentive model is used to follow the specific Signal beam of the protocol: communication bus, complete the driving of the stimulus and the collection of the response according to the interface protocol. The scoreboard judges whether the response data is correct by comparing the similarities and differences between the response data collected from the SOC chip system to be tested and the expected value. Give the flag and conclusion print of whether the test case is passed or not.

3) The script file specifies the design code by setting the top-level module of the SOC chip system to be tested and the file list containing all codes, specifies the verification code participating in the simulation by defining the name of the test case, and distinguishes the simulation type by the definition of the global variable, such as Pre-simulation, post-simulation, whether to keep waveform files, the scale of regression testing, etc.

2. Test case classification to improve verification efficiency

1) Verify processor-related scenarios: use C+Python to verify processor-related scenarios, use C language and Python language to construct the incentives for the hardware part and the operations for the software part, respectively.

2) Scenarios where processor participation can be ignored: skip the cpu startup program, and only use the random constraint feature of cocotb to build random verification cases.

3. Verification method, as shown in Figure 2:

Step 1: Specify the test case by assigning global variables, and start the operation; use the simulation tool to compile the RTL code of the SOC to be tested; run the compiled code to start the simulation, and use the GPI interface in Figure 1 to verify the simulation control of the platform on the hardware platform;

Step 2: If the global variable is defined as the CPU participation value, the CPU will load the instruction corresponding to the test case through flash after power-on, and convert it into hardware behavior; otherwise, reset the CPU to make it stop working, and directly execute the code in the test case , the excitation source is the bus model to simulate the behavior of the CPU;

Step 3: If the CPU participates, control the CPU to configure the relevant functions of the design under test according to the verification scenario, and the CPU responds to feedback information from other devices such as (interrupt); if no CPU control is required, it needs to be configured in the Python test case through the bus. The working mode required for the SOC under test to enter the verification scenario;

Step 4: Generate and send signal-level incentives: According to the scenario and functional requirements, a certain range of random data is generated and sent to the hardware interface through the hierarchical path of the signal in the hardware platform;

Step 5: Generate and send signal beam excitation: According to the scene and functional requirements, generate a certain range of random data for each signal in the signal beam, and drive the excitation data to the signal sequentially or simultaneously according to the behavior timing requirements defined in the excitation model Bundle multiple corresponding hardware interfaces to make them meet the interface behavior specification, such as the communication protocol of the bus.

Step 6: Response collection and judgment, the incentive model collects the response according to the timing requirements, and judges whether the response is the expected data in the scoreboard. If it is correct, it will give the test case pass mark, and wait for all the codes to be executed to end the simulation. If it is wrong, then Print an error message and end the simulation.

A SOC chip system-level verification system and method, wherein the verification system is based on the COCOTB open source framework, implemented using Python, easy to build, and does not need to establish a complicated UVM verification environment.

The system can use the bus behavior as the injection stimulus or read the c program injection stimulus through different test cases. Under the premise of no IPlevel verification environment and related tests, the bus connection, concurrent access, interrupt connection, interrupt response, When verifying functions such as clock and reset, the bus model, clock model, and reset model developed in the system can be used as reference models for comparison.

The system traverses all state spaces using random constrained functions, and builds a functional coverage model to converge the coverage to the delivery level.

(1) Verification system composition:

Dut part: rtl file and filelist

Python part: Use cases for testing different functions, repeated configuration processes in different test cases, and classes that constitute environment components.

Other models: external device models for simulation

Makefile: guides compilation and simulation, and distinguishes pre-simulation, post-simulation, and regression behaviors.

(2) Verification process

1. Verify environment setup

2. Script development: pre-simulation, post-simulation, regression testing

3. Verification plan

4. Test case development and pre-simulation

5. Regression testing

6. Post-simulation

In a specific implementation, the present application provides a computer storage medium and a corresponding data processing unit, wherein the computer storage medium can store a computer program, and when the computer program is executed by the data processing unit, it can run a SOC chip system level provided by the present invention The content of the invention of the verification system and method and some or all steps in each embodiment. The storage medium may be a magnetic disk, an optical disk, a read-only memory (read-only memory, ROM) or a random access memory (random access memory, RAM), etc.

Those skilled in the art can clearly understand that the technical solutions in the embodiments of the present invention can be implemented by means of computer programs and their corresponding general-purpose hardware platforms. Based on this understanding, the essence of the technical solutions in the embodiments of the present invention or the part that contributes to the prior art can be embodied in the form of a computer program, that is, a software product, and the computer program software product can be stored in a storage medium. Including several instructions to make a device including a data processing unit (which may be a personal computer, server, single-chip microcomputer, MUU or network device, etc.) execute the methods described in various embodiments or some parts of the embodiments of the present invention.

The present invention provides an idea and method of a SOC chip system-level verification system and method. There are many methods and approaches to specifically realize the technical solution. The above is only a preferred embodiment of the present invention. Those of ordinary skill may make some improvements and modifications without departing from the principle of the present invention, and these improvements and modifications shall also be regarded as the protection scope of the present invention. All components that are not specified in this embodiment can be realized by existing technologies.

Claims (10)

1. A kind of SOC chip system-level verification system, is characterized in that, comprises: hardware platform top layer, verification platform and script file; Wherein, the verification platform is connected with the top layer of the hardware platform through the GPI interface, completes the excitation drive of the hardware in the SOC chip system to be tested by the verification platform, and obtains hardware data; the script file specifies the design code and verification in the SOC chip system to be tested code, and specify the emulation type; the top layer of the hardware platform is used to run the hardware in the SOC chip system to be tested. 2. according to a kind of SOC chip system-level verification system described in claim 1, it is characterized in that, described hardware platform top layer comprises: design to be tested is the equipment model of SOC chip system to be tested and outside; Described hardware platform The top layer runs in an emulator. 3. according to a kind of SOC chip system-level verification system described in claim 2, it is characterized in that, described verification platform comprises: test case, incentive model and scoreboard. 4. according to a kind of SOC chip system-level verification system described in claim 3, it is characterized in that, described test case comprises two types of coroutines, the coroutines of public configuration and the coroutines of specific function: according to different functions The workflow of the module is configured, and the coroutine completes the driving and collection of hardware signals by accessing the hierarchical path of hardware signals in the top layer of the hardware platform, and usually communicates with the hardware platform at the signal level. 5. according to a kind of SOC chip system-level verification system described in claim 4, it is characterized in that, described excitation model is used for following the signal bundle of setting agreement: communication bus, completes the driving and the response of excitation according to interface agreement Acquisition, communication with the hardware platform at the signal beam level. 6. according to a kind of SOC chip system-level verification system described in claim 5, it is characterized in that, described scoreboard judges response by comparing the similarities and differences of response data and expected value collected from the SOC chip system to be tested Whether the data is correct, give the mark of whether the test case is passed or not, and print the conclusion. 7. according to a kind of SOC chip system-level verification system described in claim 6, it is characterized in that, described script file is used for setting test parameter, comprises: by setting the top-level module of SOC chip system to be tested and comprising all codes The design code is specified in the file list; the verification code participating in the simulation is specified by defining the name of the test case; the simulation type is distinguished by the definition of the global variable. 8. according to a kind of SOC chip system-level verification system described in claim 7, it is characterized in that, the test parameter that described script file is provided with, comprises: the scale of pre-simulation, post-simulation, need to keep waveform file and regression test . 9. according to a kind of SOC chip system-level verification system described in claim 8, it is characterized in that, described test case, classifies according to scene, concrete method is as follows: Verify processor-related scenarios: adopt C+Python, use C language and Python language to construct the operation of the software part and the incentive of the hardware part respectively; Scenarios that ignore processor participation: skip the cpu startup program in the SOC chip system to be tested, and only use the random constraint characteristics of the cocotb verification framework to build incentives for the hardware part. 10. A kind of SOC chip system-level verification method is characterized in that, adopts a kind of SOC chip system-level verification system as described in claim 9, verifies, comprises the following steps: Step 1: Specify the test case by assigning global variables, and start the operation; use the simulation tool to compile the RTL code in the SOC chip system to be tested; run the compiled code to start the simulation, and use the GPI interface to verify the simulation control of the hardware platform by the platform; Step 2: If the global variable is defined as the CPU participation value, the CPU loads the instruction corresponding to the test case through flash after power-on, and converts it into a hardware behavior; otherwise, reset the CPU to make it stop working, and directly execute the Python in the test case Code, the stimulus source is the bus model to simulate the behavior of the CPU; Step 3: If the CPU participates, control the CPU to configure the relevant functions of the design under test in the SOC chip system under test according to the verification scenario, and let the CPU respond to feedback information from other devices; if no CPU control is required, in the Python test case Make the SOC chip system under test enter the working mode required by the verification scenario through bus configuration; Step 4: Generate and send signal-level incentives: According to the scenario and functional requirements, generate random data and send it to the hardware interface through the hierarchical path of the signal in the hardware platform; Step 5: Generate and send signal bundle excitation: According to the scene and functional requirements, generate random data for each signal in the signal bundle, and drive the excitation data to the corresponding hardware interface of the signal bundle according to the behavior timing requirements defined in the excitation model. Make it meet the behavior specification of the interface; Step 6: Response collection and judgment, the incentive model collects the response according to the timing requirements, and judges whether the response is the expected data in the scoreboard. If it is correct, it will give the test case pass mark, and wait for all the codes to be executed to end the simulation. If it is wrong, then Print an error message and end the simulation.

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