CN115391845B - Key management device and method - Google Patents

Abstract

This application relates to the technical field of key security, and discloses a key management device and method, wherein the device includes: a key storage unit for storing keys; an isolation circuit for receiving an operation request from a processor: When the operation request is a read operation for the key, the isolation circuit denies access to the encryption interval address of the key storage unit; when the operation request is a write operation for the key, The isolation circuit passes the write operation to the key storage unit. The embodiment of the present application can implement safe and reliable key management in a simple manner.

Description

Key management device and method

technical field

The present application relates to the technical field of key security, in particular to a key management device and method.

Background technique

Keys have a wide range of applications in information security. For example, chips or various electronic devices can use keys to encrypt information to ensure information security.

In some existing solutions, the key is managed by a third-party trusted platform, that is, the key is stored on the third-party trusted management platform, and the negotiation and distribution of the key depend on the third-party trusted platform. When the device When you need to use the key, you need to send the relevant request to the third-party trusted platform.

In other existing solutions, key management is realized through local software/hardware solutions.

For example, in solutions such as ARM ATZ or Intel SGX, the working environment of the processor is divided into a secure environment and a non-secure environment. The key is stored in the secure environment, and the non-secure environment cannot directly access the secure environment. When using the key, the relevant request needs to be initiated by the non-secure environment.

For example, there is also a solution that utilizes local storage media to manage keys. Encrypt the key to be stored with an encryption key (such as a private key) and store the generated encrypted information in the storage medium of the device. When using the key, read the decryption key (such as the public key) corresponding to the encryption key from the one-time storage unit (such as OTP/Efuse) of the device, and use the decryption key to decrypt the encrypted information to obtain the key for use.

It should be noted that the above introduction to the technical background is only for the convenience of a clear and complete description of the technical solution of the present application, and for the convenience of understanding by those skilled in the art. It cannot be considered that the above technical solutions are known to those skilled in the art just because these solutions are described in the background technology section of this application.

Contents of the invention

The applicant found that in the above-mentioned existing key management solutions, there are the following problems:

For a solution managed by a third-party trusted platform, key-related communication between the device and the third-party trusted platform, including key request and distribution, is vulnerable to sniffing by hackers, and there is a risk of interception of communication information , and even if there is encrypted communication between the device and the third-party trusted platform, it is easy for those who understand the key solution to implement replay attacks, and information security is threatened; in addition, the management rules of the third-party trusted platform are often cumbersome , the setting of its communication is not universal, and the key management scheme cannot be fully realized according to the privatization needs of customers.

For solutions such as ARM ATZ or Intel SGX, although ARM ATZ or Intel SGX divides the secure environment and non-secure environment to ensure key security, on the one hand, ATZ and SGX require complex software stack assistance; on the other hand, The device is in a safe environment during the first stage of the startup process. If an attacker suspends the startup of the device at this time, the attacker can use external Jtag or other memory scanning tools to brute-force scan all security areas, and the key storage will no longer be safe. .

For solutions that use local storage media to manage keys, an attacker can read the one-time storage unit and the storage media, and thus, the attacker may analyze the encryption key through a brute force attack.

Aiming at at least one of the above problems or similar problems, the embodiments of the present application provide a key management device and method, which can prevent illegal access to keys in a simple manner and improve the security and reliability of key management.

The embodiment of the first aspect of the present application provides a key management device, the device comprising:

a key storage unit for storing keys;

Isolation circuit for receiving operation requests from the processor:

In the case that the operation request is a read operation for the key, the isolation circuit denies access to the encryption interval address of the key storage unit;

If the operation request is a write operation for a key, the isolation circuit transfers the write operation to the key storage unit.

In one or more embodiments,

The key storage unit also includes a check circuit, the check circuit checks the received write operation, and if the check passes, writes the key in the write operation into The key storage unit.

In one or more embodiments,

The key management device further includes an encryption and decryption circuit, which is connected to the key storage unit and uses the key stored in the key storage unit to perform encryption or decryption.

In one or more embodiments,

The isolation circuit includes:

A security identification module, the security identification module identifies whether the operation address in the operation request is an encryption interval address; and

A request identification module, when the security identification module identifies that the operation address is an encryption interval address, the request identification module identifies whether the operation request is a read operation or a write operation, and if the identification result is a write operation In the case of , the write operation is passed to the key storage unit, and in the case of the identification result being a read operation, the read operation is not passed to the key storage unit.

In one or more embodiments,

The isolation circuit also includes a filtering module. When the security identification module recognizes that the operation address is an address in an unencrypted range, the filtering module receives the operation request, and the identification result of the request identification module is In the case of a read operation, the filter module receives the read operation identified by the request identification module.

In one or more embodiments,

The filtering module returns a failure response message.

In one or more embodiments,

The isolation circuit also includes a collection module, which collects operation requests of the bus, and inputs the collected operation requests into the security identification module.

In one or more embodiments,

The key storage unit includes a static random access register and a one-time storage unit, the static random access register stores a symmetric encryption algorithm key and a certificate, and the one-time storage unit stores an asymmetric encryption algorithm public key.

In one or more embodiments, the device further includes:

The verification circuit does not perform the verification when the one-time memory unit is performing a write operation for the first time.

In one or more embodiments,

The symmetric encryption algorithm key and/or the certificate are updated periodically.

In one or more embodiments,

When the verification circuit receives the write operation, it triggers the encryption and decryption circuit to verify the signature in the write operation, and if the signature verification passes, the AND in the write operation The key corresponding to the signature is written into the key storage unit.

In one or more embodiments,

The processor allocates memory for the write operation or the read operation, and the verification result of the verification circuit is verification failure or the isolation circuit rejects the read operation or the allocation of the memory When the time exceeds a predetermined time, the processor releases the memory.

In one or more embodiments, the key management device further includes:

a memory unit for temporarily storing data processed by the processor;

a direct memory access unit for data transfer between different regions of the memory unit or between the memory unit and the encryption and decryption circuit; and

A bus, the processor, the encryption and decryption circuit, the memory unit and the direct memory access unit are connected to the bus.

The embodiment of the second aspect of the present application provides a key management method, the method is applied to a key management device, the key management device includes a storage unit for storing keys, and the method includes:

In the case that the operation request from the processor is a read operation for the key, the isolation circuit denies access to the encryption interval address of the key storage unit;

If the operation request is a write operation for a key, the isolation circuit transfers the write operation to the key storage unit.

The embodiment of the third aspect of the present application provides a chip, and the chip includes the key management device described in the embodiment of the first aspect.

The embodiment of the fourth aspect of the present application provides an electronic device, and the electronic device includes the key management apparatus described in the embodiment of the first aspect.

One of the beneficial effects of the embodiments of the present application is that the isolation circuit rejects the operation request from the processor from accessing the encryption interval address of the key storage unit. In this way, unauthorized access to the key can be prevented in a simple manner, and the security and reliability of the key management can be increased.

With reference to the following description and accompanying drawings, specific embodiments of the present application are disclosed in detail, indicating the manner in which the principles of the application may be employed. It should be understood that the embodiments of the present application are not limited thereby in scope. Embodiments of the present application encompass many changes, modifications and equivalents within the spirit and scope of the appended claims. Features described and/or illustrated with respect to one embodiment can be used in the same or similar manner in one or more other embodiments, in combination with, or instead of features in other embodiments .

Description of drawings

The drawings described herein are for illustration purposes only and are not intended to limit the scope of the present disclosure in any way. In addition, the shapes and proportional dimensions of the components in the drawings are only schematic and are used to help the understanding of the present application, and do not specifically limit the shapes and proportional dimensions of the various components of the present application. Under the teaching of this application, those skilled in the art can select various possible shapes and proportional dimensions according to specific situations to implement this application.

FIG. 1 is a schematic diagram of a key management device according to an embodiment of the present application;

Fig. 2 is another schematic diagram of the key management device of the embodiment of the present application;

Fig. 3 is a schematic diagram of the isolation circuit of the embodiment of the present application;

Fig. 4 is a schematic diagram of the request data format of the embodiment of the present application;

FIG. 5 is another schematic diagram of a key management device according to an embodiment of the present application;

FIG. 6 is a schematic diagram of a processing flow of a write operation in an embodiment of the present application;

FIG. 7 is a schematic diagram of a processing flow of a read operation in an embodiment of the present application;

Fig. 8 is a schematic diagram of a key management method according to an embodiment of the present application.

detailed description

The technical scheme of the application will be described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be understood that these embodiments are only used to illustrate the application and not to limit the scope of the application. After reading the application, those skilled in the art Modifications to various equivalent forms of the present application all fall within the scope defined by the appended claims of the present application.

In this embodiment of the application, the terms "first", "second", etc. are used to distinguish different elements from the title, but do not indicate the spatial arrangement or time order of these elements, and these elements should not be referred to by these terms restricted. The term "and/or" includes any and all combinations of one or more of the associated listed items. The terms "comprising", "including", "having" and the like refer to the presence of stated features, elements, elements or components, but do not exclude the presence or addition of one or more other features, elements, elements or components.

Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the technical field to which this application belongs. The terminology used herein in the description of the application is only for the purpose of describing specific embodiments, and is not intended to limit the application. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.

Embodiments of the first aspect

The embodiment of the first aspect of the present application provides a key management device, and FIG. 1 is a schematic diagram of the key management device according to the embodiment of the present application.

As shown in FIG. 1 , a key management device 100 includes a key storage unit 101 and an isolation circuit 102 .

In the embodiment of the present application, the key storage unit 101 is used to store the key, and the isolation circuit 102 is used to receive the operation request from the processor 200. When the operation request is a read operation for the key, the isolation circuit 102 Deny access to the encryption interval address of the key storage unit 101 , and if the operation request is a write operation for a key, the isolation circuit 102 transfers the write operation to the key storage unit 101 .

It can be seen from the above embodiments that the key storage unit in the key management device 100 is connected to the isolation circuit, and the processor's operation request for the key storage unit is determined by the isolation circuit whether it can be transmitted to the key storage unit, and the key management device 100 passes The isolation circuit 102 rejects the read operation from the processor 200 on the encrypted interval address of the key storage unit. In this way, unauthorized access to the key can be prevented in a simple manner, and the security and reliability of the key management can be increased.

For example, compared with the existing solution of key management through a third-party trusted platform, the embodiment of the present application uses local software and hardware management for key management, which can avoid key correlation with the third-party trusted platform. Some defects in communication, such as the possibility of being sniffed by hackers or replay attacks, can also save the cumbersome communication restrictions with third-party trusted platforms.

In addition, compared with the existing software/hardware management solutions, the embodiment of the present application also has the advantage of implementing safe and reliable key management in a simple manner.

For example, compared with solutions such as ARM ATZ or Intel SGX, the embodiment of the present application does not need to divide the security environment and the non-security environment, so there is no need for complex software stack assistance. In addition, solutions such as ARM ATZ or Intel SGX have a startup process The risk of the key leaking due to violent scanning by the attacker, but in the embodiment of this application, the hardware isolation circuit prevents illegal access to the key, and the attacker cannot obtain the key in the key storage unit through violent scanning. key.

For another example, compared with the existing solutions that use local storage media to manage keys, in the embodiment of this application, the hardware isolation circuit rejects the read operation of the encryption interval address of the key storage unit from the processor, In other words, at least the encrypted address space in which the key is stored in the key storage unit is invisible to external software or devices, and an attacker cannot obtain the key in the key storage unit through brute force scanning.

In the embodiment of the present application, as shown in FIG. 1 , an isolation circuit 102 is provided between the key storage unit 101 and the processor 200, so that when the processor 200 performs read and write operations on the key storage unit 101 Next, the type of operation can be judged by the isolation circuit 102, and the reading of the encrypted interval address of the key storage unit 101 can be rejected, thereby preventing illegal access to the key in the key storage unit 101, with a simple way to achieve safe and reliable key management.

In this embodiment of the present application, the encrypted interval address is a storage unit in the key storage unit 101 that cannot be read by the external environment, and the external environment includes external software and hardware, such as a processor. In addition, the key storage unit may also include a storage unit of a non-encrypted zone address, in which various information may be stored, such as other keys and certificates that are different from the key stored in the encrypted zone address and are allowed to be accessed by the external environment. and other information, this application does not limit it.

Fig. 2 is another schematic diagram of the key management device according to the embodiment of the present application.

As shown in FIG. 2 , the key storage unit 101 may include a verification circuit 103. The verification circuit 103 verifies the received write operation. The key is written into the key storage unit 101.

Therefore, by verifying the writing operation through the verifying circuit 103 , illegal tampering of the key storage unit can be prevented, and the security and reliability of key management can be further improved. The verification circuit 103 can also be a verification unit, which realizes the verification function through software or a combination of software and hardware.

For example, compared with the existing solutions that use local storage media to manage keys, in the embodiment of the present application, the key writing operation can be verified through the verification circuit, and the attacker cannot maliciously tamper with the storage media, which can prevent The key is compromised, which can improve security performance.

As shown in Figure 2, in one or more embodiments, the key management device 100 further includes an encryption and decryption circuit 104, the encryption and decryption circuit 104 is connected to the key storage unit 101 and uses the key stored in the key storage unit 101 to perform encryption or decrypt. Thus, the hardware encryption and decryption is realized by the encryption and decryption circuit 104, and by hardware encryption and decryption, only the encryption and decryption circuit 104 performs the reading of the key during the encryption or decryption process, that is to say, during the encryption or decryption process, The key storage unit is invisible to external software/hardware modules, and attackers cannot see the confidential information on the key storage device at all, which eliminates the possibility of attacking through software and can further improve security performance. In one or more embodiments, the processor 200 can be a micro control unit MCU or a central processing unit CPU, etc., the present application is not limited to this, the processor implements corresponding functions by running software, for example, the processor runs the key Management software to realize key management. Key management software includes but not limited to commands such as key read operation, key write operation, encryption operation, and decryption operation. When the key management software is running, relevant commands are executed through the processor To control the relevant components to perform corresponding operations. The key management software will be exemplarily described later.

Each module of the key management device 100 and the processor 200 will be exemplarily described below.

In one or more embodiments, the key stored in the key storage unit can be understood as any information that needs to be kept secret, which can be the key of the chip or the device itself, such as a public key, a private key, or a key in a symmetric encryption algorithm. Keys, digital certificates (such as X.509 certificates generated based on public keys), etc., can also be the keys of the peer chip or device. The peer chip or device indicates that it can exchange information with the chip or device to which the key storage unit belongs. In addition, it may also be a key of a third-party chip or device, which is not limited in this application.

In one or more embodiments, the key storage unit 101 may include a static random access register SRAM and a one-time storage unit. The one-time storage unit is, for example, a One Time Programmable (OTP) memory, or an Efuse memory. This application There is no limit to this.

In one or more embodiments, the static random access register SRAM stores modifiable keys or key-related information, for example, SRAM can store keys of symmetric encryption algorithms, digital certificates, etc., keys of symmetric encryption algorithms Both digital certificates and digital certificates can be updated periodically or irregularly, thereby improving security performance.

In one or more embodiments, the one-time storage unit can be used to store a fixed key or key information, thereby further preventing the key from being tampered with and improving security performance. For example, the one-time storage unit may be used to store a public key of an asymmetric encryption algorithm, which may also be called a trusted root key, and the key information may be a digital certificate generated according to the trusted root key.

In one or more embodiments, the write operation of the one-time storage unit can be performed before the one-time storage unit leaves the factory, and the one-time storage unit does not pass the calibration when the first write operation is performed or the one-time storage unit is empty. Verify the circuit. After the one-time storage unit completes the write operation, the write operation can be verified by the verification circuit. For example, when the verification result of the verification circuit is that the object of the write operation is a one-time storage unit, the verification circuit can reject the A write operation of a one-time storage unit may return a write failure response signal.

In one or more embodiments, for the SRAM that stores the modifiable key or key information, when the SRAM is written into the SRAM, it can be verified by a verification circuit, and it is allowed to proceed if the verification is passed. corresponding write operation.

For example, in one or more embodiments, for the key or key information that needs to be written, the write operation needs to carry the digital signature of the sender of the key or key information, and the verification circuit first determines whether the digital signature is carried, If the judgment result is that the digital signature is not carried, the write operation is rejected, and a write failure response signal is returned. If the judgment result is that the digital signature is carried, the verification circuit verifies the digital signature, and the corresponding The key or key information is written to SRAM.

In the embodiment of this application, the digital signature includes performing hash digest encryption on the key or key information and encrypting with the sender's private key. The verification of the digital signature requires asymmetric decryption and hash digest encryption. Regarding digital For the signature, reference may be made to related technologies.

In one or more embodiments, the verification circuit can send a trigger signal to the encryption and decryption circuit to control the encryption and decryption circuit to verify the digital signature, and if the verification is successful, write the corresponding key or key information to Otherwise, the write operation is rejected and a write failure response signal is returned.

In one or more embodiments, the key storage unit itself includes a verification circuit to implement the verification function, that is, the verification circuit can be integrated into the key storage unit, which can improve integration and reduce chip area. But the present application is not limited thereto, and the verification circuit can also be integrated in the isolation circuit, for example.

In one or more embodiments, when the processor performs a corresponding operation, such as a write operation or a read operation, it may allocate memory for the corresponding operation to construct a corresponding request data format, and the request data format may include a key , digital signature and other confidential information, when the verification result of the verification circuit is a verification failure or the isolation circuit refuses to read the operation or the allocation time of the memory exceeds the predetermined time, the processor releases the memory. Keys, digital signatures, etc. stored in the memory can prevent the leakage of confidential information and improve security. In one or more embodiments, the verification circuit verifies the write operation, including verifying whether the write operation carries a digital certificate and verifying the digital certificate. The verification circuit can be connected to the encryption and decryption circuit, or The verification circuit can send a signal to trigger the encryption and decryption circuit to verify the digital certificate. In addition, the verification circuit can store the key or key information in the write operation, that is to say, the verification circuit can include a storage unit for Information storage, in addition, the verification circuit can connect the SRAM and OTP/Efuse in the key storage unit, so as to realize the writing of the key or key information.

In one or more embodiments, the verification circuit itself can only perform the verification operation, thus, the verification circuit can be connected to the isolation circuit, that is, the isolation circuit is used to check the address of the write operation, and only the write operation When the write address of the operation is the address of the storage unit that can perform write operation in the key storage unit, if the write address is the address of the SRAM memory, the isolation circuit will transfer the write operation to the verification circuit, thus, the calibration The verification circuit does not need the address checking function in advance, which can simplify the verification circuit.

In one or more embodiments, the isolation circuit checks the read operation, for example, checks the address of the key storage unit to be read by the read operation, so as to prevent the reading of the key storage unit that is prohibited from being accessed. The shielding function is implemented on the hardware, which can improve the reliability of preventing password sniffing and eliminating attacks.

In one or more embodiments, the isolation circuit can allow reading of the digital certificate stored in the SRAM and the trusted root key in the OTP/Efuse, that is to say, allow the reading of the stored digital certificate and the trusted root key The reading of the address space of the storage unit rejects the reading request of other address spaces of the storage unit, but this application is not limited thereto. For example, the isolation circuit can reject the reading request of all address spaces of the key storage unit. The application is not limited to this, and isolation circuits can be set as required.

In one or more embodiments, the isolation circuit can also check the write operation, for example, check the write address of the write operation. In this case, the data carried in the write operation, including the key or password The key information is temporarily stored in the verification circuit. When the check result of the isolation circuit for the write address is passed, for example, the write address is in the address space of the SRAM memory, the verification circuit is triggered to perform the verification operation, otherwise the write operation is returned Failed to answer.

That is to say, both the write operation and the read operation of the processor to the key storage unit can be checked through the isolation circuit.

Fig. 3 is a schematic diagram of the isolation circuit of the embodiment of the first aspect of the present application.

As shown in FIG. 3 , in one or more embodiments, the isolation circuit 102 may include a security identification module 302 and a request identification module 303 .

The security identification module 302 identifies whether the operation address in the operation request is an encrypted interval address;

The request identification module 303, when the security identification module 302 identifies that the operation address is an encryption interval address, the request identification module 303 identifies whether the operation request is a read operation or a write operation, and if the identification result is a write operation, write The input operation is passed to the key storage unit 101, and the read operation is not passed to the key storage unit 101 if the identification result is a read operation.

Thus, the isolation circuit 102 can prevent the processor from reading the encryption interval address of the key storage unit 101, and improve the security performance of the key management device.

But the present application is not limited thereto. For example, in the isolation circuit, the type of the read operation may also be firstly identified by the request identification module, and then the security identification module identifies whether it is an operation for an encrypted interval address, which is not limited by the present application.

As shown in FIG. 3 , in one or more embodiments, the isolation circuit 102 further includes a filter module 304, and when the security identification module 302 recognizes that the operation address is an address in a non-encrypted range, the filter module 304 receives the operation request. When the identification result of the request identification module 303 is a read operation, the filter module 304 receives the read operation identified by the request identification module 303, that is, by setting the operation request of the filter module 304 to the address of the non-encrypted interval and the encrypted interval The read operation of the address is processed, and the processing efficiency of the operation request is improved in a modular processing manner.

In one or more embodiments, the filtering module 304 returns a failure response message, that is, the filtering module 304 returns a failure response message when any message is received. But the present application is not limited thereto. For example, the filtering module can further classify the received messages. When accessing addresses of information such as keys and certificates, the filtering module can also read corresponding information according to the read operation and return it to the processor. This application does not limit this, and it can be set according to actual needs.

As shown in FIG. 3 , in one or more embodiments, the isolation circuit 102 can also include a collection module 301, the collection module 301 collects the operation request of the bus, and inputs the collected operation request into the safety identification module 302, the bus The operation request can include data request and address information.

In the embodiment of the present application, the acquisition module 301 can receive the request, for example, the acquisition module 301 can receive the request from the bus, that is to say, the isolation circuit 104 can be connected to the bus, but the application is not limited thereto, the acquisition module 301 can also The request is received from the processor, which is not limited in the present application and can be set according to actual needs. In this embodiment of the present application, the request may be a read request or a write request, and the request may include relevant data and/or addresses. The following is an example description of the request.

Fig. 4 is the data format of the request in the embodiment of the first aspect of the present application.

As shown in Figure 4, the request data format can include a request type field, a request service field, a data length field and a content field, wherein the length of the request type field can be 1 byte, and the length of the request service field can be 1 byte, The length of the data length field can be 2 bytes, and the length of the content field can be any value in the range of 0 to 64k bytes, but the application is not limited thereto, and the length of each field can also be set according to actual needs. No limit.

In the embodiment of this application, the request type field indicates the type of request, for example, 0x80 indicates a write request, that is, a write operation, and 0x81 indicates a read request, that is, a read operation. It is worth noting that the write request and the read request also It can be represented by other numerical values, which are only illustrated here.

In the embodiment of this application, the requested service field indicates the requested service, for example, 0x70 indicates the key of a symmetric encryption algorithm, 0x71 indicates a digital certificate, such as an X.509 certificate, and 0x72 indicates an asymmetric root key (public key), which is worth It should be noted that each service may also be represented by other numerical values, which are only described as examples here.

In this embodiment of the application, the data length field indicates the data length in the content field, in bytes.

In this embodiment of the application, the content field indicates the data or address carried by the request. For example, when the request type is a write request, the content field can store the key and digital signature of the symmetric encryption algorithm, or store the digital certificate and digital signature. Or other types of information that need to be kept secret. When the request type is a read request, the content field stores the memory address. When the key storage unit is successfully read, the memory address is used to store the read content. In addition, the content field may also carry the address of the key storage unit corresponding to the write operation or the read operation.

In this embodiment of the application, the security identification module 302 identifies the address space corresponding to the request. In one or more embodiments, the address space of the SRAM and OTP/Efuse that store the key is an encrypted area, and other address spaces are general address spaces , but the present application is not limited thereto, and the interval for storing secret information such as a key that is prohibited from being read can also be called an encryption interval, such as setting the address of the key for storing a symmetric encryption algorithm in the SRAM as an encryption interval, and storing public information in the SRAM The address of the key and the address of OTP/Efuse can belong to the general address space. This application does not limit this, and the corresponding address can be set as an encrypted area according to the information of prohibited access. That is to say, the encrypted area can only indicate the storage of prohibited access. Alternatively, the encryption interval can also refer to the interval for storing information that is prohibited from access and information that is relatively weaker in confidentiality than the information that is prohibited from access. It can be set according to actual needs. Generally speaking, the encryption interval represents Access-restricted intervals, where access-prohibited information means that access by external software or devices is prohibited, and can only be accessed through the encryption and decryption circuit of the key management device, such as the key of a symmetric encryption algorithm, and the confidentiality is relative to the access-prohibited information Weaker information may include, but not limited to, the public key and certificate of the asymmetric encryption key, for example.

In the embodiment of the present application, when the identification result of the security identification module 302 is an encrypted interval address, the request identification module 303 can perform the next step of processing; when the identification result of the security identification module 302 is a general interval address, the The filtering module 304 performs the next step of processing. Thus, regardless of the read operation or the write operation, the security identification module 302 can first identify whether the operation is aimed at the key storage unit, and according to the identification result, the next step is processed by different modules, which can avoid other uncontrollable The hardware randomly accesses the key storage unit, especially the encryption interval of the key storage unit, and the address of the key storage unit is carried in the request data format or the address written to the address register is wrong during request processing. In this case, it is possible to prevent the write operation from writing the key or key information to the wrong address, causing anomalies or security risks, and it is also possible to avoid accessing from inaccessible encryption areas, especially addresses that store keys such as asymmetric encryption Space to read information and cause security risks.

In the embodiment of the present application, when the identification result of the security identification module 302 is an encryption interval address, the request identification module 303 identifies the request type for the encryption interval address, that is, reading or writing, and if the identification result is an encryption interval address Under normal circumstances, the request identification module forwards the request, such as forwarding it to the verification circuit or sending a trigger signal to the verification circuit to perform a verification operation. When the identification result is read, the request identification module sends the read request Forward to the filtering module for processing.

In the embodiment of the present application, the filter module 304 filters the general address access and the request for reading data in the encrypted area. For example, for the general address, the filter module 304 can output a failure response, thereby preventing illegal address access from causing exceptions. For the request for reading data in the encrypted area, The filtering module 304 can also output a failure response, thereby preventing the encryption interval read data request, but the present application is not limited thereto. For example, for the encryption interval read data request, the filtering module 304 can further identify whether the encryption interval address is stored in the key storage unit. The address of the readable information (such as a key or a certificate), if yes, the filter module 304 can read the corresponding information from the key storage unit and return the read information to the memory specified in the read request data format address, or, the filtering module 304 can send a read command to the verification circuit to read the corresponding information and finally return the read information to the memory address specified in the read request data format, or the encryption and decryption circuit can read from the encryption The key storage unit reads the corresponding information and stores the read information in the memory address specified in the request data format, if not, the filter module 304 can output a failure response signal, thereby preventing the read request.

In one or more embodiments, the encryption and decryption circuit 104 implements hardware encryption and decryption, through hardware encryption and decryption, during the encryption or decryption process, only the encryption and decryption circuit 104 performs key reading, that is, during encryption Or during the decryption process, the key storage unit is invisible to external software/hardware modules, and the attacker cannot see the confidential information on the key storage device at all, eliminating the possibility of attacking through software and improving security performance.

In one or more embodiments, the encryption and decryption circuit 104 can perform various encryption and decryption operations, including but not limited to encryption and decryption of symmetric encryption algorithms (such as AES, SM4, etc.), encryption and decryption of asymmetric encryption algorithms, The encryption of the hash digest algorithm is not limited in this application, and can be set according to actual needs.

In the embodiment of this application, the key management device 100 can be applied to various chips and electronic devices. In one or more embodiments, in addition to the above-mentioned key storage unit 101, verification circuit 103, isolation circuit 102 and The encryption and decryption circuit 104, the key management device 100 may also include other components.

Fig. 5 is another schematic diagram of the key management device according to the embodiment of the present application.

As shown in FIG. 5 , the key management device 100 further includes a memory unit 105 , a direct memory access unit 106 and a bus 107 .

In the embodiment of the present application, the memory unit 105 is used to temporarily store data processed by the processor, including various generated request data, information read from the key storage unit, and the like. The memory unit may be a double rate synchronous dynamic random access memory (DDR), but the present application is not limited thereto, and the memory unit may also be other types of memory.

In the embodiment of the present application, the direct memory access unit 106 can be used to move data in the memory unit 105, the direct memory access unit 106 is DMA, and the DMA data channel includes data movement between different memory areas, such as memory area 1 and memory area 2, the DMA data channel can also include the data movement between the memory area and the encryption and decryption circuit, for example, between the memory area 1 and the encryption and decryption circuit, and between the memory area 2 and the encryption and decryption circuit, for example, you can first The data to be encrypted or decrypted in the memory area 1 is moved to the encryption and decryption circuit, and the encrypted or decrypted data is moved to the memory area 2 after the encryption and decryption circuit completes the encryption or decryption.

In the embodiment of the present application, the bus 107 is used for communication and data transmission between different components. For example, as shown in FIG. 107. But the application is not limited thereto. For example, the isolation circuit can also be connected to the bus 107, that is, the processor communicates and transmits data through the bus and the isolation circuit. This application does not limit this, and can be set according to actual needs.

Each component of the key management device 100 has been exemplarily described above, and the software processing flow of each operation of the key management device 100 for key management will be exemplarily described below.

FIG. 6 is a schematic diagram of a processing flow of a write operation in an embodiment of the present application.

As shown in Figure 6, the processing flow of the write operation includes the following steps:

Step 601, accept the certificate or negotiated key sent by the peer end, the key is, for example, an asymmetric encryption public key or a symmetric encryption key, or other keys or confidential information, which is not limited in this application .

Step 602, allocate memory, construct a request command, the request command is a write request command, the data format of the write request command is shown in Figure 3 above, and the specific content and length of each field of the write request command can be determined according to the settings .

Step 603, write the constructed command into the corresponding register so as to be executed by the processor.

In this step 603, the constructed command may be referred to as the write request data format, and in the case of writing the write request data format into the corresponding register, the execution flow of the processor may include that the corresponding register may receive Write the data to the address register, that is to say, write the address contained in the write request data format to the address register, the address represents the key storage unit to be written in the write operation corresponding to the write request data format Address, after that, the corresponding register can be written into the trigger register, thereby automatically triggering the request, and carrying the address of the key storage unit to the isolation circuit for further processing, including identification by the security identification module. For details, please refer to the above security identification Description of the modules and isolation circuits.

Step 604, within a certain period of time, poll the status register, for example, a timer can be set.

Step 605, judge whether the instruction is executed successfully or whether it times out through the status register, and if the judgment result is no, continue to execute step 604 until the instruction is executed successfully or times out, and then execute step 606.

In step 606, the memory allocated for constructing the request command is released, and the execution of the key writing request ends.

It can be seen that during the above-mentioned write operation process, the key management software is responsible for writing the request command into the register, and the key management software does not directly operate the key storage unit. The read operation of the encryption interval address of the storage unit. In this way, unauthorized access to the key can be prevented in a simple manner, and the security and reliability of the key management can be increased. In addition, in the case of a verification circuit, the write operation can also be verified by the verification circuit, so as to ensure that the source of the key written into the key storage unit is credible and has not been tampered with, further improving security performance.

In the embodiment of this application, the above-mentioned processing flow can be used for writing operations of various keys or key information, including the first burning request of OTP/Efuse, the writing request of digital certificates, and the writing of symmetric keys. Input requests, etc., wherein in the first programming request of OTP/Efuse, the verification circuit does not perform verification processing.

FIG. 7 is a schematic diagram of a processing flow of a read operation according to an embodiment of the present application.

As shown in Figure 7, the processing flow of the read operation includes the following steps:

Step 701, allocate memory, construct a request command, the request command is a read request command, the data format of the read request command is shown in Figure 4 above, and the specific content and length of each field of the read request command can be determined according to the settings , in this embodiment of the application, the key management software may trigger step 701 to construct a read request command after receiving a key read request message from the peer software or device.

In this embodiment of the application, the memory allocated in step 701 includes the storage space used to construct the read request command itself and the memory space pointed to by the content field of the read request command, where the content field in the read request command is The address of the memory pointed to is used to receive the information read from the key storage unit.

Step 702, write the constructed command into the corresponding register so as to be executed by the processor. For an exemplary description of the execution flow of the processor in step 702, reference may be made to the above description about step 603.

Step 703, within a certain period of time, poll the status register, for example, a timer can be set.

Step 704, judge whether the instruction is executed successfully or whether it times out through the status register, and if the judgment result is no, continue to execute step 703 until the instruction is executed successfully or times out, and then execute step 705.

Step 705, release the memory allocated for constructing the request command, including the memory space for constructing the request command application and the memory space for storing the read information, and the execution of the key reading request is completed, in which, the memory space for storing the read information is completed. The memory space of the read information should be released after the read information is sent to the peer software or device.

It can be seen that during the above read operation, the key management software is responsible for writing the read request command into the register, and the key management software does not directly operate the key storage unit. The embodiment of the present application can check the read operation through the isolation circuit , thereby preventing access to information stored in the encrypted address space and improving security performance.

In the embodiment of the present application, the above processing flow can be used for reading operations of various keys or key information, including OTP/Efuse read requests, digital certificate read requests, and the like.

In this embodiment of the application, the key management software also includes an encryption and decryption function. Taking the encryption function as an example, the encryption process includes: allocating memory, constructing an encryption request command, the memory includes the storage space for the encryption request command itself, and the storage of the data to be encrypted The space can also include the space for storing encrypted data, and the encryption request command is written into the corresponding register so that the processor can execute the corresponding encryption processing instruction, and then the key software management software polls the status register until the encryption succeeds or times out. If the encryption is successful, the encrypted data is extracted from the space where the encrypted data is stored. The processing flow of the decryption function of the key management software is similar and will not be introduced here.

It can be seen that during the above-mentioned encryption and decryption operation process, the key management software is responsible for writing the encryption request command or decryption request command into the register, and the embodiment of the present application uses the hardware encryption and decryption circuit to read the key from the key storage unit for encryption Or decryption, the key management software does not directly operate the key storage unit during the encryption or decryption process, that is, the key storage unit is invisible to the key management software, thereby preventing the key from being damaged during the encryption or decryption process. Possibility of leakage, improve safety performance.

It can be seen from the above embodiments that the key management device 100 rejects the read operation of the encrypted interval address of the key storage unit from the processor 200 through the isolation circuit 102 . In this way, unauthorized access to the key can be prevented in a simple manner, and the security and reliability of the key management can be increased.

Embodiments of the second aspect

The embodiment of the second aspect of the present application provides a key management method, which is applied to a key management device, and the key management device includes a storage unit for storing keys. The key management device has been described in detail, and its content is incorporated here, and will not be repeated here.

Fig. 8 is a schematic diagram of a key management method according to an embodiment of the present application.

As shown in Figure 8, in one or more embodiments, the key management method includes:

Step 801, in the case that the operation request from the processor is a read operation for the key, the isolation circuit denies access to the encryption interval address of the key storage unit;

Step 802, if the operation request is a write operation for the key, the isolation circuit transmits the write operation to the key storage unit.

It can be known from the above embodiments that the read operation of the encryption interval address of the key storage unit from the processor is rejected through the isolation circuit. In this way, unauthorized access to the key can be prevented in a simple manner, and the security and reliability of the key management can be increased.

In one or more embodiments, the key management method may further include, using the verification circuit in the key storage unit to verify the received write operation, and if the verification is passed, the write operation The key in is written to the key storage unit. Therefore, by verifying the writing operation through the verification circuit, illegal tampering of the key storage unit can be prevented, and the security and reliability of key management can be further improved.

In one or more embodiments, the key management method may further include that the encryption and decryption circuit connected to the key storage unit performs encryption or decryption using the key stored in the key storage unit. Thus, the hardware encryption and decryption is realized through the encryption and decryption circuit, and through the hardware encryption and decryption, only the encryption and decryption circuit reads the key during the encryption or decryption process, that is to say, during the encryption or decryption process, the key The storage unit is invisible to external software/hardware modules, and the attacker cannot see the confidential information on the key storage device at all, which eliminates the possibility of attacking through software and can further improve security performance.

In one or more embodiments, step 802 includes,

Step 8021, identifying whether the operation address in the operation request is an encryption interval address; and

Step 8022, if the identification result is that the operation address is an encryption interval address, identify whether the operation request is a read operation or a write operation, and if the identification result is a write operation, pass the write operation to the encryption The key storage unit does not pass the read operation to the key storage unit if the identification result is a read operation.

In one or more embodiments, step 802 also includes,

If it is identified in step 8021 that the operation address is an unencrypted range address, or in the case that the identification result in step 8022 is a read operation, the key management device returns a failure response message to the processor.

In one or more embodiments, step 802 also includes,

Collect the operation request of the bus, and input the collected operation request into step 8021 .

In one or more embodiments, the key management method further includes that the processor allocates memory for the write operation or the read operation, and the verification result of the verification circuit is that the verification fails or the isolation circuit rejects the read operation or the memory The processor frees the memory if the allocated time exceeds the predetermined time.

Embodiments of the third aspect

The embodiment of the third aspect of the present application provides a chip, which includes the key management device described in the embodiment of the first aspect. Since the embodiment of the first aspect has described the key management device in detail, it The content is incorporated here, and will not be repeated here.

In this embodiment of the application, a chip can also be called an integrated circuit (integrated circuit), a microcircuit (microcircuit), or a microchip (microchip), which can be used in various scenarios or achieve various purposes, for example, for encrypted streaming media The chip for receiving and processing, the chip for graphics processing (for example, graphics processing chip, etc.), but this application is not limited to this, and it can be any chip that has confidentiality requirements. Therefore, by making the chip include this application embodiment The advanced key management equipment can realize safe and reliable key management and ensure the security of the chip.

Embodiments of the fourth aspect

The embodiment of the fourth aspect of the present application provides an electronic device, the electronic device includes the key management device described in the embodiment of the first aspect, since the embodiment of the first aspect has described the key management device in detail , whose contents are incorporated here and will not be repeated here.

In the embodiment of the present application, the electronic device can be used in various scenarios or realize various uses. For example, the electronic device can be a computer, but this application does not limit this, and it can be any electronic device that requires confidentiality. equipment. Therefore, by making the electronic device include the key management device of the embodiment of the present application, safe and reliable key management can be realized and the security of the electronic device can be ensured. In one or more embodiments, the electronic device may include a chip, and the description of the embodiments of the third aspect may be found for the chip.

Although the present application provides the operation steps of the method described in the embodiments or flowcharts, more or less operation steps may be included based on routine or non-inventive efforts. The sequence of steps enumerated in the embodiments is only one of the execution sequences of many steps, and does not represent the only execution sequence. When executed by an actual device or client product, the methods shown in the embodiments or drawings may be executed sequentially or in parallel (for example, in a parallel processor or multi-thread processing environment).

Those skilled in the art should understand that the embodiments of the present application may be provided as methods, devices (systems), or computer program products. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware aspects. Moreover, the present application may adopt one or more computer-usable storage media (including but not limited to RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, register, hard disk, removable disk, CD) containing computer-usable program code therein. - ROM or any other form of storage medium known in the art) in the form of a computer program product.

The present application is described with reference to flowcharts and/or block diagrams of methods, devices (systems), and computer program products according to embodiments of the present application. It should be understood that each procedure and/or block in the flowchart and/or block diagram, and a combination of procedures and/or blocks in the flowchart and/or block diagram can be realized by computer program instructions. These computer program instructions may be provided to a general-purpose processor, digital signal processor (DSP), application-specific integrated circuit (ASIC), field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic device, discrete hardware Components, or any appropriate combination thereof to produce a machine, so that instructions executed by a processor of a computer or other programmable data processing device generate a process or multiple processes and/or a block or multiple blocks in the flowchart for realizing devices with the functions specified in the boxes.

These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing apparatus to operate in a specific manner, such that the instructions stored in the computer-readable memory produce an article of manufacture comprising instruction means, the instructions The device realizes the function specified in one or more procedures of the flowchart and/or one or more blocks of the block diagram.

These computer program instructions can also be loaded onto a computer or other programmable data processing device, causing a series of operational steps to be performed on the computer or other programmable device to produce a computer-implemented process, thereby The instructions provide steps for implementing the functions specified in the flow chart or blocks of the flowchart and/or the block or blocks of the block diagrams.

The specific embodiments described above have further described the purpose, technical solutions and beneficial effects of the application in detail. It should be understood that the above descriptions are only specific embodiments of the application and are not intended to limit the scope of the application. Scope of protection: All modifications, equivalent replacements, improvements, etc. made within the spirit and principles of this application shall be included within the scope of protection of this application.

Claims (16)

1. A key management device, characterized in that the key management device comprises: a key storage unit for storing keys; Isolation circuit for receiving operation requests from the processor: In the case that the operation request is a read operation for the key, the isolation circuit denies access to the encryption interval address of the key storage unit; If the operation request is a write operation for a key, the isolation circuit transfers the write operation to the key storage unit. 2. The key management device of claim 1, wherein: The key storage unit includes a verification circuit, and the verification circuit verifies the received write operation, and if the verification is passed, writes the key in the write operation into the the key storage unit. 3. The key management device according to claim 1 or 2, characterized in that, The key management device further includes an encryption and decryption circuit, which is connected to the key storage unit and uses the key stored in the key storage unit to perform encryption or decryption. 4. The key management device of claim 1, wherein: The isolation circuit includes: A security identification module, the security identification module identifies whether the operation address in the operation request is an encryption interval address; and A request identification module, when the security identification module identifies that the operation address is an encryption interval address, the request identification module identifies whether the operation request is a read operation or a write operation, and if the identification result is a write operation If the identification result is a read operation, the read operation is not passed to the key storage unit. 5. The key management device of claim 4, wherein: The isolation circuit also includes a filtering module. When the security identification module recognizes that the operation address is an address in an unencrypted range, the filtering module receives the operation request, and the identification result of the request identification module is In the case of a read operation, the filter module receives the read operation identified by the request identification module. 6. The key management device of claim 5, wherein: The filtering module returns a failure response message. 7. The key management device according to any one of claims 4 to 6, characterized in that, The isolation circuit also includes a collection module, which collects operation requests of the bus, and inputs the collected operation requests into the security identification module. 8. The key management device of claim 2, wherein: The key storage unit includes a static random access register and a one-time storage unit, the static random access register stores a symmetric encryption algorithm key and a certificate, and the one-time storage unit stores an asymmetric encryption algorithm public key. 9. The key management device of claim 8, wherein: The verification circuit does not perform the verification when the one-time memory unit is performing a write operation for the first time. 10. The key management device of claim 8, wherein: The symmetric encryption algorithm key and/or the certificate are updated periodically. 11. The key management device of claim 2, wherein: When the verification circuit receives the write operation, it triggers the encryption and decryption circuit to verify the signature in the write operation, and if the signature verification passes, the AND in the write operation The key corresponding to the signature is written into the key storage unit. 12. The key management device of claim 2, wherein: The processor allocates memory for the write operation or the read operation, and the verification result of the verification circuit is verification failure or the isolation circuit rejects the read operation or the allocation of the memory When the time exceeds a predetermined time, the processor releases the memory. 13. The key management device according to claim 3, further comprising: a memory unit for temporarily storing data processed by the processor; a direct memory access unit for data transfer between different areas of the memory unit or between the memory unit and the encryption and decryption circuit; and A bus, the processor, the encryption and decryption circuit, the memory unit and the direct memory access unit are connected to the bus. 14. A key management method, characterized in that the method is applied to a key management device, and the key management device includes a storage unit for storing keys, and the method comprises: In the case that the operation request from the processor is a read operation for the key, the isolation circuit denies access to the encryption interval address of the key storage unit; If the operation request is a write operation for a key, the isolation circuit transfers the write operation to the key storage unit. 15. A chip, characterized in that the chip comprises the key management device according to any one of claims 1-13. 16. An electronic device, characterized in that the electronic device comprises the key management device according to any one of claims 1-13.

Images