CN115249717B - TFT substrate, display module and electronic equipment - Google Patents

Abstract

Embodiments of the present application provide a TFT substrate, a display module, and electronic equipment. The TFT substrate includes a substrate, a first active layer, a first source-drain layer, a first gate, a plurality of data lines and a wiring layer. Wherein, the wiring layer is disposed on a side of the first source-drain layer away from the substrate. The wiring layer includes a plurality of first metal wires. One ends of the multiple first metal wires are respectively coupled to the multiple data lines, and the other ends of the multiple first metal wires are used for coupling with the display driver chip. The wiring layer can replace the lower fan-out area in the display area AA of the electronic device, and is used to connect the data lines in the TFT substrate and the display driver chip, so as to provide the TFT substrate with image signals required for display. In this way, fan-out in the display area AA can be realized, so that the lower fan-out area of the display module of the electronic device no longer occupies the non-display area, thereby reducing the area of the non-display area and increasing the screen ratio of the electronic device.

Description

TFT substrate, display module and electronic equipment

This application claims the priority of a Chinese patent application filed with the State Intellectual Property Office on August 20, 2021, with application number 202110962861.8 and application name "A TFT Panel", the entire contents of which are incorporated in this application by reference.

technical field

The present application relates to the field of display technology, in particular to a TFT substrate, a display module and electronic equipment.

Background technique

With the continuous development of full-screen technology, electronic devices have higher and higher requirements for screen-to-body ratio. Usually, an electronic device includes a display module for displaying images. The display module may include a display area (active area, AA) and a non-display area located around the display area AA.

Usually, the non-display area includes peripheral driving circuits (such as scanning circuits that provide scanning signals, display driving chips, etc.). In order to increase the screen-to-body ratio, it is necessary to compress the area of the non-display area. Among them, the area of the non-display area can be changed from the horizontal direction to the vertical direction by compressing the scan circuit, or using a waterfall screen or a curved screen to compress the area of the non-display area. However, there is also a lower fanout (fanout) area between the display area AA and the display driver chip, as shown in FIG. 1 . The lower fan-out area couples the display driver chip to the data line (data line, DL) in the display area AA in a fan-out manner, so as to provide image signals to the display area AA. The area of the lower fan-out area cannot be reduced by compressing or bending, so the area of the non-display area at the lower frame of the electronic device is relatively large, which will greatly affect the improvement of the screen-to-body ratio of the electronic device.

Contents of the invention

Embodiments of the present application provide a TFT substrate, a display module, and an electronic device, which are used to solve the problem of a large non-display area of the electronic device, so as to increase the screen-to-body ratio of the electronic device.

In order to achieve the above object, the embodiments of the present application adopt the following technical solutions:

In a first aspect, the present application provides a TFT substrate. The TFT substrate has a plurality of sub-pixels arranged in rows and columns. The TFT substrate includes a substrate, a first active layer, a first source and drain layer, a first gate, a plurality of data lines and a wiring layer. Wherein, the first active layer is disposed on one side of the substrate, and each sub-pixel includes the first active layer. The first source-drain layer is disposed on a side of the first active layer away from the substrate. The first source-drain layer includes a first source electrode and a first drain electrode in each sub-pixel, and the first source electrode and the first drain electrode in each sub-pixel are coupled to the first active electrode in the sub-pixel. source layer. The first gate is arranged corresponding to the first active layer, and is located between the first active layer and the first source-drain layer. A plurality of data lines are located in the first source-drain layer, and the plurality of data lines are respectively coupled to the first source or the first drain in the plurality of rows of sub-pixels. The wiring layer is arranged on the side of the first source-drain layer away from the substrate. The wiring layer includes a plurality of first metal wires. One ends of the multiple first metal wires are respectively coupled to the multiple data lines, and the other ends of the multiple first metal wires are used for coupling with the display driver chip.

Based on this TFT substrate. The TFT substrate is provided with a wiring layer to replace the lower fan-out area in the display area AA of the electronic device, and is used to connect the data lines in the TFT substrate and the display driver chip, so as to provide the TFT substrate with image signals required for display. In this way, fan-out in the display area AA can be realized, so that the lower fan-out area of the display module of the electronic device no longer occupies the non-display area, thereby reducing the area of the non-display area and increasing the screen ratio of the electronic device.

In a possible implementation manner, different first metal traces among the multiple first metal traces are separated from each other. It should be understood that different first metal wires are used to connect different data wires, so as to avoid display quality problems caused by data crosstalk and improve reliability and stability of electronic devices.

In a possible implementation manner, the display driver chip is located at one edge of the TFT substrate, and the first metal wiring extends in an "L" shape. In this way, different first metal traces among the plurality of first metal traces can be separated from each other, and the routing of the first metal traces can be facilitated.

In a possible implementation manner, a plurality of first metal wires form a first region on the TFT substrate. The wiring layer also includes a plurality of second metal wirings located in the second area of the TFT substrate. Wherein, the second area is an area on the TFT substrate other than the first area. The second metal trace is disconnected from the first metal trace. In this way, after the second metal wiring is added to the wiring layer, the problem of uneven display caused by the reflection of the metal wiring (ie, the first metal wiring) in the display area AA can be effectively reduced, and the display quality of the electronic device can be improved. . In addition, the load of the pixel circuit can be uniformed, and the display quality of the display area AA can be improved.

In a possible implementation manner, different second metal traces in the plurality of second metal traces are separated from each other. In this way, the logic function of each pixel circuit in the entire TFT substrate can be guaranteed, display problems caused by crosstalk can be avoided, and the reliability and stability of electronic equipment can be improved.

In a possible implementation manner, the first metal trace extends in an "L" shape. Each second metal trace includes a first sub-trace and a second sub-trace. Wherein, the extension direction of the first sub-trace is consistent with one side of the "L" shape of the first metal trace. The extension direction of the second sub-trace is consistent with the other side of the "L" shape of the first metal trace. In this way, viewed from the display area AA as a whole, the arrangement directions of the first metal wiring and the second metal wiring are consistent (that is, long-range order), so that the first metal wiring and the second metal wiring The line arrangement is uniform, thereby effectively reducing the problem of non-uniform display caused by the reflection of the metal lines (such as the first metal line) in the display area AA, and improving the display quality of the electronic device.

In a possible implementation manner, the TFT substrate further includes a light emitting device. The light-emitting device is arranged on the side of the wiring layer away from the substrate, and the light-emitting device is coupled with the first source-drain layer. It should be understood that the above-mentioned first active layer, first gate, first source, and first drain may form a transistor of a pixel circuit. Different types of pixel circuits may include multiple different transistors, and the sources and drains of the multiple different transistors can be located in the first source-drain layer. The coupling of the light-emitting device to the first source-drain layer means that the light-emitting device is coupled to the source or drain of a certain transistor in the first source-drain layer. Therefore, the light-emitting device can also be arranged in the TFT substrate and coupled with the first source-drain layer to realize the light-emitting device to emit light, so that each sub-pixel in the display module can display according to a preset gray scale, Furthermore, the gray scale displayed by each sub-pixel forms an image.

In a possible implementation manner, the TFT substrate further includes a second source and drain layer. The second source-drain layer is disposed between the first source-drain layer and the wiring layer. The light emitting device is coupled to the first source and drain layer through the second source and drain layer. In this way, the resolution of the display module can be increased, and the display quality can be improved.

In a possible implementation manner, the TFT substrate further includes a light emitting device. The light emitting device is arranged on the side of the wiring layer away from the substrate. The light-emitting device is coupled to the first source-drain layer through the second metal wiring. After the second metal wiring is set in the wiring layer, the light-emitting device can be coupled with the first source-drain layer through the second metal wiring, so as to reduce the load of the power supply wiring and reduce the voltage drop (IR drop) .

In a possible implementation manner, the TFT substrate further includes a second source and drain layer. The second source-drain layer is disposed between the first source-drain layer and the wiring layer. The first source-drain layer is coupled to the second source-drain layer, and the second source-drain layer is coupled to the second metal wiring. Similarly, after the resolution is improved through the second source-drain layer, the second source-drain layer can be coupled with the second metal wiring, so as to realize the coupling of the light-emitting device with the first source-drain layer, so as to reduce the The load of the power trace reduces the voltage drop (IR drop).

In a second aspect, the present application provides a display module. The display module includes a display driver chip and the TFT substrate in any possible implementation manner of the above first aspect. The display driver chip is coupled to the wiring layer in the TFT substrate.

In a third aspect, the present application provides an electronic device. The electronic device includes a printed circuit board, a driver chip, and the TFT substrate in any possible implementation manner of the above first aspect. The printed circuit board includes an application processor. The application processor is coupled with the driver chip. The driving chip includes a display driving chip; the display driving chip is coupled with the wiring layer in the TFT substrate.

It can be understood that the display module provided in the second aspect above and the electronic device described in the third aspect are all associated with the TFT substrate provided in the first aspect above, and the beneficial effects that can be achieved can refer to the above first The beneficial effects of the TFT substrate provided by the aspect will not be repeated here.

Description of drawings

FIG. 1 is a schematic structural diagram of a display module with a lower fan-out area;

FIG. 2 is a schematic structural diagram of an electronic device provided in an embodiment of the present application;

FIG. 3 is a structural schematic diagram 1 of a display module provided by an embodiment of the present application;

FIG. 4 is a schematic structural diagram of another electronic device provided by an embodiment of the present application;

Fig. 5 is a schematic structural diagram II of a display module provided by the embodiment of the present application;

FIG. 6 is a schematic structural diagram III of a display module provided in the embodiment of the present application;

FIG. 7 is a schematic structural diagram of a transistor provided in an embodiment of the present application;

FIG. 8 is a schematic circuit structure diagram of a pixel circuit provided by an embodiment of the present application;

FIG. 9 is a first structural schematic diagram of a TFT substrate provided in an embodiment of the present application;

FIG. 10 is a second structural schematic diagram of a TFT substrate provided in the embodiment of the present application;

Fig. 11 is a structural schematic diagram 4 of a display module provided by the embodiment of the present application;

Fig. 12 is a partial enlarged view of place A in Fig. 11;

Fig. 13 is a schematic structural diagram five of a display module provided in the embodiment of the present application;

Fig. 14 is a partial enlarged view of place A in Fig. 13;

FIG. 15 is a schematic structural diagram III of a TFT substrate provided in the embodiment of the present application;

FIG. 16 is a fourth structural schematic diagram of a TFT substrate provided in an embodiment of the present application.

Detailed ways

The following will describe the technical solutions in the embodiments of the application with reference to the drawings in the embodiments of the application. Apparently, the described embodiments are only some of the embodiments of the application, not all of them.

Hereinafter, the terms "first", "second", etc. are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance or implicitly specifying the quantity of indicated technical features. Thus, a feature defined as "first", "second", etc. may expressly or implicitly include one or more of that feature. In the description of the present application, unless otherwise specified, "plurality" means two or more.

In the description of this application, the terms "center", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", " The orientation or positional relationship indicated by "bottom", "inner", "outer", "vertical", "horizontal", etc. is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the application and simplifying the description. It is not to indicate or imply that the device or element referred to must have a particular orientation, be constructed, or operate in a particular orientation, and thus should not be construed as limiting the application.

In this application, unless otherwise specified and limited, the term "connection" should be understood in a broad sense, for example, "connection" can be a fixed connection, a detachable connection, or an integral body; it can be a direct connection, or It can be connected indirectly through an intermediary. In addition, the term "coupled" or "coupled" may be an electrical connection for signal transmission. Those of ordinary skill in the art can understand the specific meanings of the above terms in this application in specific situations.

An embodiment of the present application provides an electronic device. The electronic device includes a mobile phone (mobile phone), a tablet computer (pad), a computer, a smart wearable product (for example, a smart watch, a smart bracelet), a set-top box, a media player, a portable electronic device, and a virtual reality (virtual reality, VR) Terminal equipment, augmented reality (augmented reality AR) terminal equipment and other electronic products with a display interface. The embodiment of the present application does not specifically limit the specific form of the foregoing electronic device.

For the convenience of description, the electronic device 01 is taken as an example below as a mobile phone as shown in FIG. 2 . The above-mentioned electronic device 01 includes a display module 10 , a middle frame 11 and a rear case 12 . The middle frame 11 is located between the display module 10 and the rear case 12 . The display module 10 and the rear case 12 are respectively connected with the middle frame 11 . Wherein, the accommodating cavity formed between the rear shell 12 and the middle frame 11 is used for accommodating a battery, a camera module (not shown in FIG. 2 ), and a printed circuit board (printed circuit board, PCB) as shown in FIG. 2 , etc. Electronic Component.

It should be understood that the structures in the above-mentioned electronic device 01 are not limited to the above-mentioned structures such as the display module 10, the middle frame 11, and the rear case 12, and may also include other structures, such as a small board, a battery cover, and a subscriber identity module (SIM ) and other structures, which are not specifically limited in the embodiment of the present application.

For any of the above electronic devices 01 , the above display module 10 is mainly used for displaying images, videos and the like. As shown in FIG. 3 , the display module 10 includes a supporting backplane 101 , a pixel circuit 102 , a peripheral driving circuit 103 , a light emitting device 104 and a top packaging layer 105 . Wherein, the supporting backplane 101 is used to support the pixel circuit 102 , the peripheral driving circuit 103 and the light emitting device 104 . The top packaging layer 105 is used to package the pixel circuit 102 , the peripheral driving circuit 103 and the light emitting device 104 . Both the pixel circuit 102 and the peripheral driving circuit 103 are fabricated on the same plane on one side of the supporting backplane, and the peripheral driving circuit is located around the pixel circuit 102 . The light emitting device 104 is located on a side of the pixel circuit 102 away from the supporting backplane 101 . The pixel circuit 102 is used to drive the light emitting device 104 to emit light, so that the display module 10 can display images. The peripheral driving circuit 103 is used in the processor in the electronic device 01 to control the operation of the pixel circuit 102 .

In this case, as shown in FIG. 4 , the display module 10 may include a display area (active area, AA) (also called a pixel area) and a non-display area located around the display area AA. The display area AA includes a plurality of sub-pixels (sub pixel) 30 arranged in rows and columns. Wherein, each sub-pixel 30 is provided with a pixel circuit 102 and a light emitting device 104 as shown in FIG. 2 . The pixel circuit 102 is used to drive the light emitting device 104 to emit light, so that each sub-pixel 30 in the display module 10 can display according to a preset gray scale. The non-display area includes a scanning circuit and a driving chip 20 . Wherein, the scanning circuit provides scanning signals required for image display to the display area AA. The driver chip may include a display driver integrated circuit (DDIC) and a scanning circuit driver chip. In this case, taking an OLED display screen as an example, the pixel circuits in the same row of pixels are coupled to the display driver chip through the same data line (DL), so as to provide image signals for the display area AA. The scanning circuit driver chip is coupled to the scanning circuit through a scan line (scan line, SL), and is used to control the scanning circuit to output a scanning signal to the display area AA. The above-mentioned scanning circuit and the driving chip 20 can constitute a peripheral driving circuit 103 as shown in FIG. 3 .

In some embodiments of the present application, the light-emitting device 104 is a liquid crystal display (liquid crystal display, LCD), an organic light-emitting diode (organic light-emitting diode, OLED), a flexible light-emitting diode (flex light-emitting diode, FLED), Miniled , MicroLed, Micro-oLed, quantum dot light emitting diodes (quantum dot light emitting diodes, QLED) and so on. For the convenience of description, the light emitting device 104 is an OLED as an example for description.

In addition, as shown in FIG. 4 , the above-mentioned electronic device 01 further includes a printed circuit board (printed circuit board, PCB) (or a drive system board), and an application processor (application processor, AP) (such as a CPU) mounted on the PCB. ), power management chip (power IC). The driver chip 20 in FIG. 4 is coupled to the AP through a flexible printed circuit (FPC).

In this way, the AP provides display data for the display driver chip and the display module to display actual image information. The power management chip provides working voltage for the display driver chip and the display module. The FPC provides a signal transmission connection path between the PCB and the display module. The FPC and the PCB are connected through a connector, and the other end of the FPC is bonded to the display module through an anisotropic conductive film. The driver chip is responsible for receiving the signal transmitted by the PCB and sending the signal to the display module according to a specific timing control. For example, the display data output by the AP passes through the driving chip 20 and is converted into a data voltage Vdata, which is then transmitted to the pixel circuits coupled to each data line DL. Next, each pixel circuit generates a driving current I matching the data voltage Vdata through the data voltage Vdata on the data line DL, so as to drive the OLED device in the pixel to emit light.

The pixel circuits, OLED devices, and data lines DL in each pixel of the display module 10 can be fabricated on a base substrate (ie, the supporting backplane 101 ). The base substrate can be made of flexible resin material. In this case, the OLED display can be used as a folding display. Alternatively, the base substrate in the above-mentioned OLED display screen may also be made of a relatively hard material, such as glass. In this case, the aforementioned OLED display is a rigid display.

It should be noted that, as the screen-to-body ratio requirements of electronic devices increase, the display module 10 for electronic devices needs to reduce the non-display area, for example, it can compress the scanning circuit, or use a waterfall screen or a curved screen to compress the non-display area. The area of the non-display area is changed from the horizontal direction to the vertical direction, that is, the non-display area is bent downward. However, as shown in FIG. 5 , there is also a lower fan-out (fanout) area between the display area AA and the driver chip 20 in the display module 10, and the lower fan-out area makes the driver chip 20 and the display The data lines DL in the area AA are coupled to provide image signals to the display area AA. The area of the lower fan-out area cannot be reduced by compressing or bending. Therefore, in general, the area of the non-display area at the lower frame of the electronic device is relatively large, which will greatly affect the improvement of the screen-to-body ratio of the electronic device.

Based on this, some embodiments of the present application provide a TFT substrate. The TFT substrate can adjust the lower fan-out area into the display area AA, which can be called fan-out in AA area (fanout in AA, FIAA). In this way, the lower fan-out area will no longer occupy the non-display area, thereby reducing the area of the non-display area and increasing the screen-to-body ratio of the electronic device.

The TFT substrate provided by some embodiments of the present application will be described in detail below with reference to the accompanying drawings. It should be understood that the TFT substrate includes the supporting backplane 101 , the pixel circuit 102 and the light emitting device 104 shown in FIG. 3 , that is, the display area AA in the display module 10 shown in FIG. 4 .

As shown in FIG. 6 , each sub-pixel 30 in the display area AA of the display module includes a pixel circuit 102 and a light emitting device 104 . Wherein, the pixel circuit 102 is coupled with the scanning circuit through the scanning line SL for receiving the scanning signal of the scanning circuit, and the pixel circuit 102 is also coupled with the display driving chip through the data line DL for receiving the image signal of the display driving chip, The light-emitting device 104 is driven to emit light, so that each sub-pixel 30 in the display area AA can display according to a preset gray scale. The gray scale displayed by each sub-pixel 30 can form an image.

In some embodiments of the present application, the pixel circuit 102 may include a plurality of transistors and at least one capacitor, and the transistor may be a thin film transistor (thin film transistor, TFT).

Any of the above-mentioned transistors may include a gate (gate, g), an active layer (active layer, AL) and a first electrode, such as a source (source, s) and The second pole is, for example, a drain (drain, d). Alternatively, the first pole of the transistor may be the drain d, and the second pole may be the source s. The present application does not limit this, and for the convenience of illustration, the following descriptions are made by taking the first pole of the transistor as the source s and the second pole as the drain d as an example.

The active layer AL is made of semiconductor material. When the voltage applied to the gate g of the transistor can turn on the transistor, the above-mentioned active layer AL is converted from an insulator to a conductor, so that the source s and the drain g of the transistor are coupled. When the voltage applied to the gate g of the transistor cannot turn on the transistor, the above-mentioned active layer AL is in an insulating state, and the source s and drain d of the transistor are disconnected.

Depending on the material constituting the active layer of the above-mentioned transistor, the performance of the transistor also varies. For example, when the material of the active layer of the transistor is polysilicon (for example, low temperature polysilicon, low temperature poly-silicon, LTPS), due to the high electron mobility of the polysilicon transistor, it is generally used in the case of a relatively fast switching frequency (such as electron device 01 is on) to improve switching efficiency. It should be noted that the above-mentioned low-temperature polysilicon is polysilicon deposited in a low-temperature environment (for example, the temperature is lower than 600° C.).

Or, for another example, when the material constituting the active layer of the transistor is a semiconductor oxide (for example, amorphous indium gallium zinc oxide, IGZO), since the electron mobility of the semiconductor oxide transistor is lower than Polysilicon transistors have extremely low off-state current, and are generally used in situations where the switching frequency is slow (for example, the electronic device 01 is in a standby state), and can be used to reduce leakage current, thereby reducing power consumption. Hereinafter, for convenience of description, a transistor whose active layer is polysilicon is called a first transistor, and a transistor whose active layer is a semiconductor oxide is called a second transistor.

Exemplarily, in some embodiments, in order to enable the pixel circuit 102 to be quickly turned on when the high-frequency drive (for example, the electronic device 01 is in the on state), and at the same time, when the low-frequency drive (for example, the electronic device 01 is in the standby state), To reduce power consumption, the pixel circuit 102 includes at least one first transistor and one second transistor.

As shown in FIG. 8 , the pixel circuit 102 may include a driving transistor Td, a switching transistor Tc, and a capacitor Cst. At this time, the pixel circuit 102 has a 2T1C structure. Among them, "2T" refers to two transistors, and "1C" refers to a storage capacitor.

For example, the gate g of the switch transistor Tc is coupled to a gate line (gate line, GL), and the gate line GL is coupled to a scan line SL. The source s of the switching transistor Tc is coupled to a data line (data line, DL) for transmitting the data voltage Vdata to the source s of the switching transistor Tc through the data line D. The drain d of the switching transistor Tc is coupled to one end of the storage capacitor Cst, and the other end of the storage capacitor Cst is coupled to the power supply VDD. The drain d of the switching transistor Tc is also coupled to the gate g of the driving transistor Td, the source s of the driving transistor Td is coupled to the power supply VDD, and the drain d of the driving transistor Td is coupled to the anode (anode) of the light emitting device 104 connected, and the cathode (cathode) of the light emitting device 104 is grounded.

The switching transistor Tc is used to be in a conducting state under the control of a gate line (GL), so as to write the data voltage Vdata into the gate g of the driving transistor Td and the storage capacitor Cst. The storage capacitor Cst can maintain the gate voltage of the driving transistor Td, so that the gate voltage of the driving transistor Td can be stabilized within an image frame. In this case, the driving transistor Td can generate a driving current according to the data voltage Vdata, so that the light emitting device 104 can emit light according to the driving current.

In some embodiments of the present application, the drive transistor Td in FIG. 8 may be the above-mentioned first transistor, for example, the active layer of the drive transistor Td is LTPS, in addition, the switch transistor Tc may be the above-mentioned second transistor, for example, the switch The active layer of the transistor is IGZO. In this case, due to the high electron mobility of the drive transistor Td (that is, the first transistor), when the first transistor is connected to the light-emitting device 104, the light-emitting device 104 can be turned on quickly. The off-state current of the second transistor is extremely low, and when the second transistor is used as the switching transistor Tc to control the switching of the circuit, the leakage current can be reduced, thereby reducing power consumption and increasing the standby time of the device.

Alternatively, in other embodiments of the present application, the driving transistor Td in FIG. 8 may be the above-mentioned second transistor, for example, the active layer of the driving transistor Td is IGZO, and in addition, the switching transistor Tc may be the above-mentioned first transistor, That is, for example, the active layer of the switching transistor Tc is LTPS.

It should be understood that the above-mentioned pixel circuit 102 is only for illustration. In some embodiments, the number of switching transistors can be increased to eliminate the influence of the threshold voltage (Vth) of the driving transistor Td on the luminous brightness of the light emitting device 104 and improve the brightness of the light emitting device. Uniformity, for example, the pixel circuit 102 can be a 7T1C or 8T1C structure. Of course, in some embodiments, the above pixel circuit 102 may also include only one transistor, such as the above first transistor or the above second transistor. Therefore, the embodiment of the present application does not specifically limit the structure of the pixel circuit 102 .

In the following, for the convenience of description, the structure of the pixel circuit 102 is 2T1C as an example, and the driving transistor Td in the pixel circuit 102 is the above-mentioned first transistor (for example, the active layer is LTPS), and the switching transistor Tc is the second transistor. (for example, the active layer is IGZO), the TFT substrate provided in the embodiment of the present application will be described.

As shown in FIG. 9 or FIG. 10 (the cross-sectional view obtained by cutting along the dotted line O-O in FIG. 6), the TFT substrate provided by the embodiment of the present application includes a substrate 201, and the first transistor ( For example, the active layer is LTPS) 202 and the second transistor (for example, the active layer is IGZO) 203, and a pixel definition layer (pixel definition layer) disposed on the side away from the substrate 201 of the first transistor 202 and the second transistor 203 , PDL) 204. The pixel defining layer 204 has a plurality of hollow structures. One of the aforementioned light emitting devices 104 may be disposed in one of the hollow structures in the pixel defining layer 204 . The above-mentioned light emitting device 104 may include an anode (anode) 205 , a light emitting layer 206 and a cathode 207 stacked in order from bottom to top.

In the embodiment of the present application, the material constituting the substrate 201 may include hard materials, such as at least one of glass, sapphire or metal materials. Alternatively, the material constituting the substrate 201 may also include a flexible material, such as a polymer material. Exemplarily, when the material of the substrate 201 includes a flexible material, as shown in FIG. 9 or FIG. layer 2012 (for example, silicon oxide, SiOx), a second substrate layer 2013 (for example: PI) and a second barrier layer 2014 (for example, silicon oxide, SiOx). The first substrate layer 2011, the first barrier layer 2012, the second The substrate layer 2013 and the second barrier layer 2014 are stacked in sequence.

It can be known from the above description that the first transistor 202 may include a gate 211 , a first electrode (eg, source s), a second electrode (eg, drain d) 209 and an active layer 212 . As shown in FIG. 9 or FIG. 10, there is a first gate insulating layer 213 (for example, a silicon oxide SiOx layer) between the gate 211 of the first transistor 202 and the active layer 212, and the gate 211 of the first transistor 202 Compared with the active layer 212 , it is further away from the substrate 201 . Therefore, the first transistor 202 is a top-gate transistor.

Similarly, the second transistor 203 may also include a gate 214 (ie, the first gate), a first pole (eg, the source s) (ie, the first source), a second pole (eg, the drain d) (ie the first drain) and the active layer 215 (ie the first active layer). Between the gate 214 of the second transistor 203 and the active layer 215, there is a second gate insulating layer 216 (for example, a silicon oxide SiOx layer), and the gate 214 of the second transistor 203 is more dense than the active layer 215. away from the substrate 201 . Therefore, the second transistor 202 is a top-gate transistor.

The material constituting the gate 211 of the first transistor 202 and the gate 214 of the second transistor 203 can be molybdenum (Mo), titanium/aluminum/titanium alloy (Ti/Al/Ti), (molybdenum/aluminum/molybdenum alloy) Mo /Al/Mo, titanium (Ti) and other metal materials.

Since the active layer 212 of the first transistor 202 is polysilicon, the active layer 215 of the second transistor 203 is a semiconductor oxide. In order to prevent the ion diffusion in the active layer 212 of the first transistor 202 and the active layer 215 of the second transistor 203 from affecting the function of the transistor, usually between the first gate insulating layer 213 and the second gate insulating layer 216 There is also a barrier layer 217 between them.

In addition, the TFT substrate also includes a storage capacitor Cst. The storage capacitor Cst may also include a first electrode 223 and a second electrode 224 . The first electrode 223 is located on the surface of the first gate insulating layer 213 away from the substrate 201 , and the first electrode 223 and the gate 211 of the first transistor 202 have the same layer and the same material. A third gate insulating layer 225 is further disposed between the first gate insulating layer 213 and the blocking layer 217 . The second electrode 224 is located on the surface of the third gate insulating layer 225 away from the substrate 201, the second electrode 224 is coupled to the first transistor 202, and the second electrode 224 is made of the same material as the gate 211 of the second transistor 203. . In this case, the second electrode 224 is the upper plate of the storage capacitor Cst, and the first electrode 223 is the lower plate of the storage capacitor.

An interlayer dielectric layer 218 is disposed on the side of the second gate insulating layer 216 and the gate 214 of the second transistor 203 away from the substrate 201 for isolation. The side of the interlayer dielectric layer 218 away from the substrate 201 is covered with an organic film as a first planarization layer (Planarization, PLN) 219 .

Usually, the source s and drain d of the first transistor 202 and the source s and drain d of the second transistor 203 are arranged in the same hierarchical structure. For convenience of description, the layered structure where the source s and drain d of the first transistor 202 and the source s and drain d of the second transistor 203 are located is referred to as a first source-drain layer. A first source and drain layer can be formed on the side of the first flat layer 219 away from the substrate 201 . The source s and the drain d in the first source-drain layer can be coupled to the active layer of the corresponding transistor (such as the first transistor or the second transistor) through via holes.

According to FIG. 8 , the above-mentioned first transistor 202 can be used as the driving transistor Td as shown in FIG. 8 . Therefore, in some embodiments of the present application, as shown in FIG. 9 , the second pole 209 of the first transistor 202 may be directly coupled to the anode 205 of the light emitting device 104 . Alternatively, as shown in FIG. 10 , the TFT substrate may further include a second source and drain layer 208 . The second source-drain layer 208 is located on a side of the first source-drain layer away from the substrate 201 . The second pole 209 of the first transistor 202 can be coupled to the anode 205 of the light emitting device 104 through the second source-drain layer 208 . Compared with the second pole 209 of the first transistor 202 being directly coupled to the anode 205 of the light emitting device 104 , the second pole 209 of the first transistor 202 is connected to the anode 205 of the light emitting device 104 through the second source and drain layer 208 Coupled with each other, the resolution of the display module composed of the TFT substrate can be improved.

According to FIG. 8 , the above-mentioned second transistor 203 can be used as the switching transistor Tc shown in FIG. 8 , and the source s of the switching transistor Tc needs to be coupled to the data line DL. Usually, the data line DL can be arranged on the first source-drain layer (not shown in the figure) of the TFT substrate. The chips are coupled so that the image signal (ie, the data voltage Vdata) provided by the driving chip can be transmitted to the switching transistor Tc, and then transmitted to the driving transistor Td to drive the light emitting device 104 to emit light.

However, in some embodiments of the present application, as shown in FIG. 9 or FIG. 10 , the TFT substrate further includes a wiring layer 210 . When the second electrode 209 of the first transistor 202 is directly coupled to the anode 205 of the light emitting device 104 , as shown in FIG. 9 , the wiring layer 210 is located between the first source-drain layer and the pixel defining layer 204 . For example, the side of the first source-drain layer away from the substrate 201 may be covered with an organic film as the second planar layer 220 . A wiring layer 210 can be formed on the side of the second planar layer 220 away from the substrate 201 . A side of the wiring layer 210 away from the substrate 201 may be covered with an organic film as the third planar layer 221 . The aforementioned pixel defining layer may be located on a side of the third flat layer 221 away from the substrate 201 .

When the second electrode 209 of the first transistor 202 is coupled to the anode 205 of the light emitting device 104 through the second source and drain layer 208, as shown in FIG. 10, the wiring layer 210 is located between the second source and drain layer 208 and the pixel Defined between layers 204 . For example, the side of the first source-drain layer away from the substrate 201 may be covered with an organic film as the second planar layer 220 . On the side of the second planar layer 220 far away from the substrate 201, a second source-drain layer 208 can be fabricated for coupling to the first source-drain layer (such as being coupled to the second electrode of the first transistor 202) through a via hole. 209). The side of the second source-drain layer 208 away from the substrate 201 may be covered with an organic film as the third planar layer 221 . The above-mentioned wiring layer 210 can be fabricated on the side of the above-mentioned third flat layer 221 away from the substrate 201 . A side of the wiring layer 210 away from the substrate 201 may be covered with an organic film as the fourth planar layer 222 . The above-mentioned pixel defining layer 204 can be disposed on the side of the fourth planar layer 222 away from the substrate 201, and the anode 205 of the light emitting device 104 inside the hollow structure of the pixel defining layer 204 can communicate with the second source and drain layer through the via hole. 208 , so that the second pole 209 of the first transistor 202 is coupled to the anode 205 of the light emitting device 104 .

The wiring layer 210 includes a plurality of first metal wires 2101, the plurality of first metal wires 2101 respectively correspond to a plurality of data lines (data lines, DL) in the TFT substrate, and the plurality of first metal wires 2101 is used to connect multiple data lines DL in the TFT substrate. For example, the multiple data lines DL of the TFT substrate are usually located at the first source-drain layer of the first transistor 202, and may be coupled to the source or drain of the second transistor 203, so each line in the wiring layer 210 The first metal trace 2101 can be coupled to the corresponding data line DL in the TFT substrate through a via hole (not shown in the figure, and the via hole is filled with a conductive material, such as a metal material). The plurality of first metal traces 2101 of the wiring layer 210 can also be coupled to the driver chip through a wire (wirebond), so as to realize fan-out in the display area AA, so as to realize the coupling between the driver chip and the data line DL in the TFT substrate , thereby reducing the area of the non-display area and increasing the screen-to-body ratio of the electronic device.

It should be noted that, in the TFT substrate shown in FIG. 9 or FIG. 10 , the wiring layer 210 only includes the first metal wiring 2101 for connecting the data line DL of the TFT substrate to the driving chip. Usually, the driving chip is located at the lower edge of the display area AA, so the first metal wires 2101 in the wiring layer 210 are distributed in the lower area of the display AA area, as shown in FIG. 11 . Here, the lower area showing the AA area also includes both sides of the AA area, that is, the lower area showing the AA area is all areas where the lower edge of the AA area extends along the two sides of the AA area toward the middle of the AA area). In addition, to facilitate wiring arrangement in the wiring layer 210 , different first metal wirings 2101 do not intersect each other and are isolated from each other (that is, separated from each other). For example, as shown in FIG. 12 (the partial enlarged view at A in FIG. 11 ), the via holes 230 connected to the first metal traces 2101 on different data lines DL are staggered in the extending direction of the data lines DL. After each first metal wire 2101 is connected to the via hole 230 of the corresponding data line DL, it extends in an "L" shape in the second source-drain layer 210, so that all the first metal wires 2101 are arranged Afterwards, all the first metal traces 2101 form a first area similar to a "house" shape. It should be understood that, according to the arrangement of different via holes 230 , the area formed by the first metal trace 2101 may be in other arbitrary shapes, such as inverted triangle, trapezoid, and the like.

After adding the wiring layer 210 formed by the first metal wiring 2101, there will be pixel circuits between the sub-pixels 30 covered with the first metal wiring 2101 and the sub-pixels 30 not covered with the first metal wiring 2101 The problem of inconsistency in load may cause the problem of inconsistency in brightness among different sub-pixels 30 , thereby reducing the display quality of the electronic device. In addition, the first area formed by the first metal wiring 2101 will form a reflective area compared with the area without the first metal wiring 2101 , thus causing the problem of uneven display of different sub-pixels 30 in the display area AA.

In some embodiments of the present application, in order to solve the problem of inconsistent loads of the above-mentioned pixel circuits and the problem of uneven display in different regions, as shown in FIG. (that is, the second area) (also called the Dummy area) covers the second metal wire 2102 . That is to say, in the TFT substrate, the wiring layer 210 includes a first metal wiring 2101 and a second metal wiring 2102 . For the connection relationship of the first metal wiring 2101 , please refer to the above description, which will not be repeated here. The second metal wiring 2102 is not connected to the first metal wiring 2101 and does not have any electrical connection relationship (that is, the second metal wiring 2102 is separated from the first metal wiring 2101 ). The arrangement of the second metal traces 2102 can be similar to the arrangement of the first metal traces 2101, for example, as shown in FIG. 14 (the partial enlarged view at A in FIG. The second metal wires 2102 and each group of second metal wires 2102 are not connected to each other and do not have any electrical connection relationship (that is, they are separated from each other). Each group of second metal wires 2102 may be formed by coupling metal wires A (ie, first sub-wires) and metal wires B (ie, second sub-wires) arranged alternately. Wherein, the metal trace A may be in the same direction as one side of the "L" shape in the first metal trace 2101, and the metal trace B may be in the same direction as the other side of the "L" shape in the first metal trace 2101. unanimous. In this way, viewed from the display area AA as a whole, the arrangement directions of the first metal wiring 2101 and the second metal wiring 2102 are consistent (that is, long-range order), so that the first metal wiring 2101 and the second metal wiring 2101 The two metal wires 2102 are uniformly arranged, thereby effectively reducing the problem of non-uniform display caused by the reflection of the metal wires (such as the first metal wire 2101 ) in the display area AA, and improving the display quality of the electronic device. In addition, through the arrangement of the above-mentioned second metal wiring 2102, in the local micro-nano circuit (ie pixel circuit), the pixel circuits in different sub-pixels 30 are separated from each other (ie, short-range disorder), thereby ensuring that the entire TFT substrate The logic function of each pixel circuit in the device can avoid display problems caused by crosstalk, and improve the reliability and stability of electronic equipment.

After the second metal wire 2102 is provided in the wiring layer 210, as shown in FIG. The second metal wire 2102 is coupled to the first source-drain layer (that is, to the second pole 209 of the first transistor 202 ) through the via hole, so as to realize the connection between the second pole 209 of the first transistor 202 and the light emitting device 104 The anode 205 is coupled. Alternatively, as shown in FIG. 16, the anode 205 of the light emitting device 104 may be coupled to the second metal wiring 2102 in the wiring layer 210 through a via hole, and the second metal wiring 2102 in the wiring layer 210 is coupled through a via hole to the second source-drain layer 208 , so that the second pole 209 of the first transistor 202 is coupled to the anode 205 of the light emitting device 104 .

It should be understood that when the electronic device is provided with an under-screen camera (that is, a camera arranged under the display screen), or the electronic device has other special-shaped design areas (such as a circular arc-shaped corner (conner) on the edge of the electronic device), the wiring After the second metal wire 2102 is provided on the layer 210, the anode 205 of the area light emitting device 104 can also be coupled to the second pole 209 of the first transistor 202 through the second metal wire 2102 and the via hole.

When the TFT substrate is applied to a large-sized AM-OLED panel or an AM-OLED panel with high power consumption, when the second metal wiring 2102 in the wiring layer 210 passes through the via hole and the second source-drain layer 208 or the first After the second electrode 209 of a transistor 202 is coupled, the wiring layer 210 can be used to reduce the load of the power supply wiring in the AM-OLED panel and reduce the voltage drop (IR drop). When the TFT substrate is applied to an LCD panel, the second metal wiring 2102 in the wiring layer 210 can be coupled with the common electrode in the LCD panel to optimize ghost (Ghost), uneven brightness (mura) and Bad loading problem.

In summary, the wiring layer 210 is provided in the TFT substrate, and the wiring layer 210 includes the first metal wiring 2101 and the second metal wiring 2102, which can effectively reduce the Line 2101) The problem of uneven display caused by reflections can improve the display quality of electronic equipment. In addition, the load of the pixel circuit can be uniformed, and the display quality of the display area AA can be improved.

The embodiment of the present application also provides a display module. The display module includes any one of the above-mentioned TFT substrates and a driver chip. Wherein, the driving chip may include a display driving chip. The display driving chip is coupled with the data line of the TFT substrate. The display module has the same technical effect as the TFT substrate provided in the foregoing embodiments, which will not be repeated here.

The embodiment of the present application also provides an electronic device. The electronic device includes a printed circuit board, a driver chip and any TFT substrate as described above, and the printed circuit board includes an application processor. The application processor is coupled with the driver chip. The driving chip includes a display driving chip; the display driving chip is coupled with the wiring layer in the TFT substrate. The electronic device has the same technical effect as that of the TFT substrate provided in the foregoing embodiments, which will not be repeated here.

The above is only a specific implementation of the application, but the scope of protection of the application is not limited thereto. Anyone familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the application. Should be covered within the protection scope of this application. Therefore, the protection scope of the present application should be determined by the protection scope of the claims.

Claims (8)

1. A TFT substrate having a plurality of subpixels arranged in rows and columns, the TFT substrate comprising:

a substrate;

the first active layer is arranged on one side of the substrate; each subpixel includes the first active layer therein;

the first source-drain electrode layer is arranged on one side of the first active layer, which is far away from the substrate; the first source/drain electrode layer comprises a first source electrode and a first drain electrode in each sub-pixel; the first source and the first drain within each of the subpixels are coupled to the first active layer within the subpixel;

The first grid electrode is arranged corresponding to the first active layer and is positioned between the first active layer and the first source drain electrode layer;

the data lines are positioned on the first source-drain electrode layer, and each data line is respectively coupled with the first source electrode or the first drain electrode in a row of sub-pixels;

the wiring layer is arranged on one side of the first source-drain electrode layer, which is far away from the substrate; the wiring layer comprises a plurality of first metal wires; one end of each first metal wire is coupled with one data wire, and the other end of each first metal wire is used for being coupled with a display driving chip;

the wiring layer further comprises a plurality of second metal wires, the second metal wires and the first metal wires are arranged in the wiring layer in a non-overlapping mode, and the second metal wires are disconnected with the first metal wires;

the second metal wire in the wiring layer is coupled to the first source-drain electrode layer through a via hole;

the TFT substrate further includes:

a light emitting device disposed on a side of the wiring layer away from the substrate; the light emitting device is coupled with the first source drain electrode layer through the second metal wire.

2. The TFT substrate of claim 1, wherein different ones of the first metal traces are spaced apart from one another.

3. The TFT substrate of claim 1 or 2, wherein the display driver chip is located at a side edge of the TFT substrate, and the first metal trace extends in an "L" shape.

4. The TFT substrate of claim 3, wherein different ones of the second metal traces are spaced apart from each other.

5. The TFT substrate of claim 1, wherein the first metal trace extends in an "L" shape; each second metal wire comprises a first sub-wire and a second sub-wire; the extending direction of one side of the L-shaped first metal wire is consistent with the extending direction of one side of the L-shaped first metal wire; the second sub-wiring is consistent with the extending direction of the other side of the L-shaped first metal wiring.

6. The TFT substrate of claim 1, wherein the TFT substrate further comprises:

the second source-drain electrode layer is arranged between the first source-drain electrode layer and the wiring layer; the second source-drain electrode layer is coupled with the second metal wiring.

7. A display module comprising a display driver chip and the TFT substrate as set forth in any one of claims 1 to 6; the display driving chip is coupled with the wiring layer in the TFT substrate.

8. An electronic device comprising a printed circuit board, a driver chip, and the TFT substrate as set forth in any one of claims 1 to 6;

the printed circuit board includes an application processor; the application processor is coupled with the driving chip;

the driving chip comprises a display driving chip; the display driving chip is coupled with the wiring layer in the TFT substrate.

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