CN115099146A - Circuit generation method, circuit generation device, electronic equipment and storage medium - Google Patents

Abstract

The present application provides a method, device, electronic device and storage medium for generating a circuit, including: acquiring circuit design parameters, where the circuit design parameters include expected circuit characteristics, an upper limit of the number of devices, and the number of device ports; according to the expected circuit characteristics, establishing Data set; build multiple candidate circuits based on the neural network model; for each candidate circuit, based on fixed device design parameters and data set, obtain the device port parameters of the candidate circuit through feasible analysis and training; according to the data set and the actual output of the candidate circuit , perform an increase or decrease analysis on the candidate circuit until the actual output of the candidate circuit matches the data set; according to the data set and the simulation output of the candidate circuit, the device design parameters of the candidate circuit are obtained through quantitative analysis and training; the final circuit is obtained. In the above scheme, a circuit is constructed through a neural network model, and the final circuit is obtained through analysis and screening, thereby automatically generating a circuit, reducing manual operations and improving efficiency.

Description

Circuit generation method, device, electronic device, and storage medium

technical field

The present application relates to the field of integrated circuits, and in particular, to a circuit generation method, apparatus, electronic device, and storage medium.

Background technique

At present, for complex circuit functions and various types of circuit devices, the circuit design mainly relies on the experience of R&D personnel, and the feasibility of the circuit is verified by simulation.

However, as analog circuits enter the nanoscale, the complexity and integration of integrated circuits are getting higher and higher. The method of designing the circuit that relies on the experience of the developer faces the problem of inefficiency. Therefore, how to generate circuits efficiently is a current problem.

SUMMARY OF THE INVENTION

The present application provides a circuit generation method, device, electronic device, and storage medium for generating circuits with high efficiency.

In a first aspect, the present application provides a circuit generation method comprising: acquiring circuit design parameters, the circuit design parameters including desired circuit characteristics, an upper limit of the number of devices, and the number of device ports; establishing a data set according to the desired circuit characteristics; According to the number of device ports, the upper limit of the number of devices, and the types of candidate devices, multiple candidate circuits are constructed based on the neural network model; for each candidate circuit, based on fixed device design parameters and data sets, obtained through feasible analysis and training The device port parameters of the candidate circuit; if the feasibility analysis is passed, the increase or decrease analysis is performed on the candidate circuit according to the data set and the actual output of the candidate circuit, until the actual output of the candidate circuit matches the data set; if the increase or decrease analysis is passed, the device design parameters of the candidate circuit are obtained through quantitative analysis and training according to the data set and the simulation output of the candidate circuit; wherein, the device port parameters include a device The electrical signal parameters of each port, the data set includes multiple sets of standard inputs and corresponding standard outputs; the final circuit is obtained according to the candidate circuits through quantitative analysis.

In a possible implementation manner, for each candidate circuit, based on fixed device design parameters, the device port parameters of the candidate circuit are obtained by performing feasible analysis and training, including: using a first objective function as an optimizer's Optimize the objective, and perform iterative training of feasibility analysis until the first objective function is satisfied, wherein the first objective function represents that the voltages of the input ports and the output ports are equal and the current sum is equal to 0; if the feasibility analysis If the number of iterations of the feasibility analysis exceeds the preset first threshold, the candidate circuit is screened; if the number of iterations of the feasibility analysis does not exceed the first threshold, it is determined that the candidate circuit passes the feasibility analysis.

In a possible implementation manner, if the feasibility analysis is passed, according to the data set and the actual output of the candidate circuit, an increase or decrease analysis is performed on the candidate circuit until the actual output of the candidate circuit is reached. The output matches the data set, including: if the feasibility analysis is passed, using each standard input in the data set as the actual input of the candidate circuit, and performing iterative training of the increase or decrease analysis until the second Objective function, wherein the second objective function represents that the error between the current actual output and the standard output does not exceed a preset second threshold; Threshold, the current training will be recorded as 0; if the number of iterations of this incremental analysis does not exceed the preset third threshold, the current actual output of the candidate circuit will be recorded; all records of the incremental analysis training will be recorded Correlation analysis is performed with the standard output in the data set, and if the correlation analysis result is greater than a preset fourth threshold, it is determined that the candidate circuit passes the increase or decrease analysis.

In a possible implementation manner, if the increase/decrease analysis is passed, the device design parameters of the candidate circuit are obtained through quantitative analysis and training according to the data set and the simulation output of the candidate circuit, including: The standard input in the data set is used as the simulation input of the candidate circuit, and based on the circuit simulator, the candidate circuit is simulated to obtain the simulation output of the candidate circuit; and, according to the initial value of the device design parameter and With a predetermined standard deviation range, the current training design parameters are randomly generated; according to the current training design parameters and the corresponding simulation output, based on a probability class algorithm, a prediction model for predicting the device design parameters based on the simulation output is trained; The simulation output is used as input, and the device design parameters output by the prediction model and the standard deviation range of the output are obtained; according to the output device design parameters and the standard deviation range of the output, the current training design parameters are randomly generated; According to the current training design parameters and the corresponding simulation output, the step of training the prediction model for predicting the device design parameters based on the simulation output based on the probability class algorithm, until the number of model training times exceeds the preset fifth threshold, then the prediction model is used. The currently output device design parameters are used as the device design parameters of the candidate circuit, and it is determined that the candidate circuit has passed the quantitative analysis.

In a possible implementation manner, obtaining the final circuit according to the candidate circuits that have passed the quantitative analysis includes: screening the candidate circuits that have passed the quantitative analysis, and pushing the screened candidate circuits to the user; candidate circuit as the final circuit.

In a second aspect, the present application provides a circuit generation device, comprising: an acquisition module for acquiring circuit design parameters, where the circuit design parameters include expected circuit characteristics, an upper limit value of the number of devices, and the number of device ports; characteristics, to establish a data set; a building module, for constructing multiple candidate circuits based on the neural network model according to the number of device ports, the upper limit of the number of devices, and the type of candidate devices; a training module for each candidate circuit , based on the fixed device design parameters and data set, obtain the device port parameters of the candidate circuit through feasible analysis training; if the feasibility analysis is passed, according to the data set and the actual output of the candidate circuit, the candidate circuit The circuit performs an increase/decrease analysis until the actual output of the candidate circuit matches the data set; if the increase/decrease analysis is passed, then according to the data set and the simulation output of the candidate circuit, the quantitative analysis training is performed to obtain the Device design parameters of candidate circuits; wherein, the device port parameters include electrical signal parameters of each port of the device, and the data set includes multiple sets of standard inputs and corresponding standard outputs; a screening module is used to analyze the candidate circuits according to the quantitative analysis. , to obtain the final circuit.

In a possible implementation manner, the training module is specifically configured to perform iterative training of feasibility analysis based on the first objective function as the optimization objective of the optimizer until the first objective function is satisfied, wherein the The first objective function represents that the input voltage of each port and the output port are equal and the current sum is equal to 0; the training module is specifically also used to filter out all the data if the number of iterations of the feasibility analysis exceeds a preset first threshold. The candidate circuit is determined; if the number of iterations of the feasibility analysis does not exceed the first threshold, it is determined that the candidate circuit passes the feasibility analysis.

In a possible implementation manner, the training module is specifically configured to, if the feasibility analysis passes, use each standard input in the data set as the actual input of the candidate circuit, and perform the iteration of the increase-decrease analysis Training until the second objective function is satisfied, wherein the second objective function represents that the error between the current actual output and the standard output does not exceed a preset second threshold; If the number of iterations exceeds the preset third threshold, the current training will be recorded as 0; if the number of iterations of this increase/decrease analysis does not exceed the preset third threshold, the current actual output of the candidate circuit will be recorded; The training module is specifically also used to perform correlation analysis on the records of all the increase/decrease analysis training and the standard output in the data set. If the correlation analysis result is greater than the preset fourth threshold, it is determined that the candidate circuit has passed the Incremental analysis.

In a possible implementation manner, if the increase/decrease analysis is passed, the device design parameters of the candidate circuit are obtained through quantitative analysis and training according to the data set and the simulation output of the candidate circuit, including: The training module is specifically configured to use the standard input in the data set as the simulation input of the candidate circuit, simulate the candidate circuit based on the circuit simulator, and obtain the simulation output of the candidate circuit; According to the initial value of the device design parameters and the predetermined standard deviation range, the current training design parameters are randomly generated; the training module is specifically also used for, according to the current training design parameters and the corresponding simulation output, based on probabilistic algorithms, training with A prediction model for predicting device design parameters based on the simulation output; the simulation output of the candidate circuit is used as input to obtain the device design parameters output by the prediction model and the standard deviation range of the output; The outputted device design parameters and the output standard deviation range randomly generate the current training design parameters; and, re-executing the described according to the current training design parameters and the corresponding simulation output, based on the probability class algorithm training for predicting the device based on the simulation output The step of designing the prediction model of the parameters, until the number of model training times exceeds the preset fifth threshold, the device design parameters currently output by the prediction model are used as the device design parameters of the candidate circuit, and it is determined that the candidate circuit has passed the quantitative analyze.

In a possible implementation manner, the screening module is specifically configured to screen candidate circuits that have passed quantitative analysis, and push the screened candidate circuits to the user; the screening module is also specifically configured to screen the user The selected candidate circuit is used as the final circuit.

In a third aspect, the present application provides an electronic device, comprising: a processor, and a memory communicatively connected to the processor; the memory stores computer-executed instructions; the processor executes the computer-executed instructions stored in the memory, to implement the method of any one of the first aspects.

In a fourth aspect, the present application provides a computer-readable storage medium, where computer-executable instructions are stored in the computer-readable storage medium, and the computer-executable instructions are executed by a processor to execute the method according to any one of the first aspects. .

The circuit generation method, device, electronic device and storage medium provided by the present application obtain circuit design parameters, the circuit design parameters include expected circuit characteristics, upper limit of the number of devices, and number of device ports; according to the expected circuit characteristics, establish data According to the number of device ports, the upper limit of the number of devices, and the types of candidate devices, multiple candidate circuits are constructed based on the neural network model; for each candidate circuit, based on fixed device design parameters and data sets, through feasible analysis The device port parameters of the candidate circuit are obtained by training; if the feasibility analysis is passed, the increase or decrease analysis is performed on the candidate circuit according to the data set and the actual output of the candidate circuit until the actual output of the candidate circuit is reached. The output matches the data set; if the increase or decrease analysis is passed, the device design parameters of the candidate circuit are obtained through quantitative analysis and training according to the data set and the simulation output of the candidate circuit; wherein, the device port parameters Including the electrical signal parameters of each port of the device, the data set includes multiple sets of standard inputs and corresponding standard outputs; the final circuit is obtained according to the candidate circuit through quantitative analysis. In the above scheme, a circuit is constructed through a neural network model, and the final circuit is obtained through analysis and screening, thereby automatically generating a circuit, reducing manual operations and improving efficiency.

Description of drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the application and together with the description serve to explain the principles of the application.

FIG. 1 is a schematic diagram of an application scenario of a circuit generation method provided by an embodiment of the present application;

FIG. 2 is a schematic flowchart of a circuit generation method provided in Embodiment 1 of the present application;

FIG. 3 provides an example of circuit feasibility analysis provided by an embodiment of the present application;

FIG. 4 is a schematic structural diagram of a circuit generation apparatus provided in Embodiment 2 of the present application;

FIG. 5 is an apparatus block diagram of a circuit generation apparatus provided in Embodiment 3 of the present application;

FIG. 6 is a schematic structural diagram of an electronic device provided in Embodiment 4 of the present application.

Specific embodiments of the present application have been shown by the above-mentioned drawings, and will be described in more detail hereinafter. These drawings and written descriptions are not intended to limit the scope of the concepts of the present application in any way, but to illustrate the concepts of the present application to those skilled in the art by referring to specific embodiments.

Detailed ways

Exemplary embodiments will be described in detail herein, examples of which are illustrated in the accompanying drawings. Where the following description refers to the drawings, the same numerals in different drawings refer to the same or similar elements unless otherwise indicated. The implementations described in the illustrative examples below are not intended to represent all implementations consistent with this application. Rather, they are merely examples of apparatus and methods consistent with some aspects of the present application as recited in the appended claims.

First, the terms involved are explained:

Spice model (Simulation program with integrated circuit emphasis, referred to as Spice): an analog circuit simulator for circuit analysis of integrated circuits.

FIG. 1 is a schematic diagram of an application scenario of a circuit generation method provided by an embodiment of the present application. Take the scenario shown as an example: the neural network model obtains the user's circuit design parameters and constructs multiple candidate circuits. The candidate circuits are subjected to qualitative analysis and quantitative analysis in turn, and the circuits that fail the analysis are screened out to obtain the final circuit. Push the final circuit to the user for selection.

The solutions of the embodiments of the present application will be exemplified and introduced below with reference to the following embodiments.

Example 1

2 is a schematic flowchart of a circuit generation method provided in Embodiment 1 of the present application, and the method includes the following steps:

S101. Acquire circuit design parameters, where the circuit design parameters include expected circuit characteristics, an upper limit of the number of devices, and the number of device ports; establish a data set according to the expected circuit characteristics;

S102. According to the number of device ports, the upper limit of the number of devices, and the type of candidate devices, construct a plurality of candidate circuits based on a neural network model;

S103. For each candidate circuit, based on the fixed device design parameters and the data set, obtain the device port parameters of the candidate circuit through feasible analysis and training; if the feasibility analysis is passed, then according to the data set and the candidate circuit Actual output, perform an increase or decrease analysis on the candidate circuit until the actual output of the candidate circuit matches the data set; if the increase or decrease analysis passes, then according to the data set and the simulation output of the candidate circuit, The device design parameters of the candidate circuit are obtained through quantitative analysis and training; wherein, the device port parameters include electrical signal parameters of each port of the device, and the data set includes multiple sets of standard inputs and corresponding standard outputs;

S104: Obtain a final circuit according to the candidate circuit through quantitative analysis.

As an example, the execution body of this embodiment may be a circuit generating apparatus, and the circuit generating apparatus may be implemented in multiple ways. For example, it can be program software, or a medium storing relevant computer programs, such as a USB flash drive; , server, etc.

In one example, S101 includes: obtaining the upper limit of the number of devices in the device library; obtaining the user-defined number of device ports; obtaining the circuit characteristics expected by the user;

As an implementation manner, a data set is established by constructing a series of input and output voltage or current results according to the circuit characteristics designed by the user. For example, if the characteristic of the circuit designed by the user is voltage amplification, a series of voltages are constructed as input, and a series of voltages are respectively multiplied by the amplification factor as an output data set.

Combined with the scene example, the upper limit of the number of devices is obtained directly from the device library. The number of device ports can be set according to user needs. Normalizes all devices to a user-set number of device ports. For example, the user sets the number of device ports to 3, normalizing all devices to 3-port devices. Each port of each device contains two variables, current and voltage. For the extra ports with resistances smaller than 3-port devices, they can be equivalent to ports whose current is always 0 and voltage is always 0. Similarly, open circuit, short circuit, and power supply can also be equivalent to 3-port devices. Similarly, the combination of multiple devices can also be equivalent to a 3-port device.

Optionally, port design is performed based on the neural network simulation Spice model.

Based on the above embodiments, circuit design parameters are obtained, so that a circuit that meets the conditions is automatically generated according to the circuit design parameters next.

Next, according to the obtained circuit design parameters, the circuit is automatically generated and analyzed.

In an example, S102 includes: calculating the generated maximum number of circuits; and sequentially constructing a plurality of candidate circuits according to the maximum number of circuits.

Optionally, the maximum number of generated circuits is calculated based on the calculation formula of the maximum number of circuits:

((M*N)^N)*C)^M

Among them, M is the upper limit of the number of devices, N is the number of device ports, and C is the type of candidate devices.

According to the maximum number of circuits, a plurality of candidate circuits are constructed based on the neural network model.

Based on the above implementation manner, all circuits that conform to the circuit design parameters are generated through enumeration to avoid circuit omission.

In the above scheme, to generate multiple circuits that meet the circuit design parameters, it is necessary to verify the reliability of the circuit through circuit analysis and verification. The circuit analysis includes qualitative analysis and quantitative analysis, the qualitative analysis includes feasibility analysis and increase or decrease analysis, and the quantitative analysis is used to obtain device design parameters of the circuit. The following is an example of the circuit analysis flow.

In an example, S103 includes: based on the first objective function as the optimization objective of the optimizer, performing iterative training of feasibility analysis until the first objective function is satisfied, wherein the first objective function represents the input of each port and output the voltage of the port is equal and the current sum is equal to 0; if the number of iterations of the feasibility analysis exceeds the preset first threshold, the candidate circuit is screened; if the number of iterations of the feasibility analysis does not exceed the first threshold , it is determined that the candidate circuit passes the feasibility analysis.

Combined with scenario examples, qualitative analysis includes feasibility analysis and increase or decrease analysis. Feasibility analysis is represented by a first objective function. If the first objective function is satisfied, that is, the input voltage of each port of the circuit and the output voltage of the port are equal and the current sum is equal to 0, it means that each port of the circuit can flow normally. If there is an open circuit of the port and the current cannot pass through the port, it is not satisfied that the voltage input to the port and the output port are equal and the sum of the current is equal to 0. Iterative optimization is performed with the first objective function as the optimization target of the optimizer. If the number of iterations exceeds the preset first threshold and the first objective function is not reached, it is determined that the circuit fails the feasibility analysis. The number of iterations is limited by the first threshold to prevent infinite loop iterations.

For ease of understanding, Figure 3 is an example of a circuit feasibility analysis. As shown in Figure 3, the ports of multiple devices in the circuit are connected. If the circuit can flow normally, the voltages flowing through the ports are equal and the sum of the currents is equal to 0. Among them, the current meter of the input port is positive, the current meter of the output port is negative, and the sum of the current of the input port is equal to the absolute value of the sum of the current of the output port.

Based on the above embodiments, the candidate circuit is iteratively optimized through the first objective function to obtain the device port parameters of the circuit, so as to ensure the normal circulation of the circuit. The number of iterations is constrained by the first threshold to prevent infinite loop iterations.

In an example, S103 further includes: if the feasibility analysis is passed, using each standard input in the data set as the actual input of the candidate circuit, and performing iterative training of the increase/decrease analysis until the second Objective function, wherein the second objective function represents that the error between the current actual output and the standard output does not exceed a preset second threshold; Threshold, the current training will be recorded as 0; if the number of iterations of this incremental analysis does not exceed the preset third threshold, the current actual output of the candidate circuit will be recorded; all records of the incremental analysis training will be recorded Correlation analysis is performed with the standard output in the data set, and if the correlation analysis result is greater than a preset fourth threshold, it is determined that the candidate circuit passes the increase or decrease analysis.

Combined with the scenario example, the increase or decrease analysis is used to analyze whether the function of the circuit can meet the user's needs. The data of the dataset is constructed according to user requirements. The input of the data set is sequentially obtained and the second objective function is used to train the candidate circuit. If the output of the candidate circuit and the output of the data set are within the error range, it means that the function of the candidate circuit meets the needs of the user.

Based on the above embodiments, whether the candidate circuit can achieve the circuit characteristics designed by the user is verified through the second objective function.

In the above scheme, the candidate circuits are qualitatively analyzed, and the candidate circuits that can circulate normally and meet the circuit characteristics designed by the user are screened out. Next, the quantitative analysis process is exemplified.

In an example, S103 further includes: using the standard input in the data set as a simulation input of the candidate circuit, simulating the candidate circuit based on a circuit simulator, and obtaining a simulation output of the candidate circuit; and, According to the initial value of the device design parameters and the predetermined standard deviation range, the current training design parameters are randomly generated; according to the current training design parameters and the corresponding simulation output, based on the probability class algorithm, the training is used to predict the device design based on the simulation output. parameter prediction model; take the simulation output of the candidate circuit as input, obtain the device design parameters output by the prediction model and the standard deviation range of the output; according to the output device design parameters and the output standard deviation range, randomly generate the current training the design parameters; and, performing the step of training the prediction model for predicting the device design parameters based on the simulation output based on the probabilistic algorithm based on the current training design parameters and the corresponding simulation output again, until the number of times of model training exceeds a preset number of times. For the fifth threshold, the device design parameters currently output by the prediction model are used as the device design parameters of the candidate circuit, and it is determined that the candidate circuit has passed the quantitative analysis.

Combining the scene example, quantitative analysis is used to obtain the device design parameters of the circuit. The device design parameters are the property parameters of the device itself, such as the device design parameters of the resistor, that is, the resistance value of the resistor. According to the initial values of device design parameters set by the user, a series of device design parameters are generated within a predetermined standard deviation range. The simulation output is obtained by simulating the input data in the candidate circuit input data set. Iterative training optimizes device design parameters by simulating a model that outputs a model that predicts a range of device design parameters.

Optionally, a hash table is constructed using the simulation output as the key and the corresponding circuit as the value.

Based on the above embodiments, the final device design parameters are obtained by optimization by training the simulation output prediction device design parameter model.

In the above scheme, the candidate circuit is analyzed to obtain the optimized circuit, and then the selection stage of the optimized circuit is performed to obtain the final circuit.

In one example, S104 includes: screening candidate circuits that have passed the quantitative analysis, and pushing the screened candidate circuits to the user; and taking the candidate circuits selected by the user as the final circuit.

Optionally, draw each key of the hash table into a radar chart, and if there is a radar chart a included in the radar chart b, screen out the radar chart a.

Combined with the scene example, the candidate circuits through quantitative analysis are filtered and pushed to the user, and the user can select a suitable circuit according to their needs.

Based on the above embodiments, the final circuit is determined through user selection, so that the final circuit meets user requirements.

In the circuit generation method provided in this embodiment, circuit design parameters are obtained, where the circuit design parameters include expected circuit characteristics, an upper limit of the number of devices, and the number of device ports; a data set is established according to the expected circuit characteristics; The number of ports, the upper limit of the number of devices, and the types of candidate devices, and multiple candidate circuits are constructed based on the neural network model; for each candidate circuit, the candidate circuit is obtained through feasible analysis and training based on fixed device design parameters and data sets If the feasibility analysis is passed, then according to the data set and the actual output of the candidate circuit, the candidate circuit is analyzed for increase or decrease, until the actual output of the candidate circuit matches the data set ; If the increase/decrease analysis is passed, then according to the data set and the simulation output of the candidate circuit, the device design parameters of the candidate circuit are obtained through quantitative analysis and training; wherein, the device port parameters include the electrical power of each port of the device. Signal parameters, the data set includes multiple sets of standard inputs and corresponding standard outputs; according to the candidate circuits through quantitative analysis, the final circuit is obtained. In the above scheme, a circuit is constructed through a neural network model, and the final circuit is obtained through analysis and screening, thereby automatically generating a circuit, reducing manual operations and improving efficiency.

Embodiment 2

FIG. 4 is a schematic structural diagram of a circuit generation device according to Embodiment 2 of the present application. As shown in FIG. 4 , the device includes:

an acquisition module 61, configured to acquire circuit design parameters, where the circuit design parameters include expected circuit characteristics, an upper limit of the number of devices, and the number of device ports; establish a data set according to the expected circuit characteristics;

A building module 62, configured to build a plurality of candidate circuits based on the neural network model according to the number of device ports, the upper limit value of the number of devices, and the type of candidate devices;

The training module 63 is configured to, for each candidate circuit, obtain the device port parameters of the candidate circuit through feasible analysis training based on fixed device design parameters and data sets; The actual output of the candidate circuit is analyzed, and the candidate circuit is subjected to an increase or decrease analysis until the actual output of the candidate circuit matches the data set; if the increase or decrease analysis passes, the data set and the candidate circuit The device design parameters of the candidate circuit are obtained through quantitative analysis and training; wherein, the device port parameters include electrical signal parameters of each port of the device, and the data set includes multiple sets of standard inputs and corresponding standard outputs;

The screening module 64 is used for obtaining the final circuit according to the candidate circuits through quantitative analysis.

In one example, the acquisition module 61 is specifically used to acquire the upper limit of the number of devices in the device library; the acquisition module 61 is specifically used to acquire the user-defined number of device ports; the acquisition module 61 is specifically used to acquire the circuit characteristics expected by the user .

As an embodiment, the acquisition module 61 constructs a series of input and output voltage or current results according to the circuit characteristics designed by the user, and establishes a data set. For example, if the characteristic of the circuit designed by the user is voltage amplification, a series of voltages are constructed as input, and a series of voltages are respectively multiplied by the amplification factor as an output data set.

Combined with the scene example, the upper limit of the number of devices is obtained directly from the device library. The number of device ports can be set according to user needs. Normalizes all devices to a user-set number of device ports. For example, the user sets the number of device ports to 3, normalizing all devices to 3-port devices. Each port of each device contains two variables, current and voltage. For the extra ports with resistances smaller than 3-port devices, they can be equivalent to ports whose current is always 0 and voltage is always 0. Similarly, open circuit, short circuit, and power supply can also be equivalent to 3-port devices. Similarly, the combination of multiple devices can also be equivalent to a 3-port device.

Optionally, port design is performed based on the neural network simulation Spice model.

Based on the above embodiments, circuit design parameters are obtained, so that a circuit that meets the conditions is automatically generated according to the circuit design parameters next.

Next, according to the obtained circuit design parameters, the circuit is automatically generated and analyzed.

In one example, the building module 62 is specifically configured to calculate and obtain the maximum number of circuits generated; the building module 62 is further configured to sequentially build a plurality of candidate circuits according to the maximum number of circuits.

Optionally, the maximum number of generated circuits is calculated based on the calculation formula of the maximum number of circuits:

((M*N)^N)*C)^M

Among them, M is the upper limit of the number of devices, N is the number of device ports, and C is the type of candidate devices.

According to the maximum number of circuits, a plurality of candidate circuits are constructed based on the neural network model.

Based on the above implementation manner, all circuits that conform to the circuit design parameters are generated through enumeration to avoid circuit omission.

In the above scheme, to generate multiple circuits that meet the circuit design parameters, it is necessary to verify the reliability of the circuit through circuit analysis and verification. The circuit analysis includes qualitative analysis and quantitative analysis, the quantitative analysis includes feasibility analysis and increase/decrease analysis, and the quantitative analysis of the device design parameters of the circuit obtained by the user. The following is an example of the circuit analysis flow.

In one example, the training module 63 is specifically configured to perform iterative training of feasibility analysis based on the first objective function as the optimization objective of the optimizer until the first objective function is satisfied, wherein the first objective function represents The input voltage of each port and the output voltage of the port are equal and the current sum is equal to 0; the training module 63 is also specifically configured to filter out the candidate circuit if the number of iterations of the feasibility analysis exceeds the preset first threshold; if feasible If the number of iterations of the feasibility analysis does not exceed the first threshold, it is determined that the candidate circuit passes the feasibility analysis.

As an embodiment, the training module 63 constructs a series of input and output voltage or current results according to the circuit characteristics designed by the user, and establishes a data set. For example, if the characteristic of the circuit designed by the user is voltage amplification, a series of voltages are constructed as input, and a series of voltages are respectively multiplied by the amplification factor as an output data set.

Combined with scenario examples, qualitative analysis includes feasibility analysis and increase or decrease analysis. Feasibility analysis is represented by a first objective function. If the first objective function is satisfied, that is, the voltage of each port of the circuit and the output port are equal and the sum of the current is equal to 0, it means that each port of the circuit can flow normally. If there is a port open circuit, and the current cannot pass through the port, it is not satisfied that the voltages of the input port and the output port are equal and the sum of the currents is equal to 0. The training module 63 performs iterative optimization with the first objective function as the optimization target of the optimizer. If the number of iterations exceeds the preset first threshold and does not reach the first objective function, it is determined that the circuit fails the feasibility analysis. The number of iterations is limited by the first threshold to prevent infinite loop iterations.

Based on the above embodiments, the training module 63 iteratively optimizes the candidate circuit through the first objective function, and obtains the device port parameters of the circuit to ensure that the circuit can circulate normally. The number of iterations is constrained by the first threshold to prevent infinite loop iterations.

In one example, the training module 63 is specifically configured to, if the feasibility analysis passes, use each standard input in the data set as the actual input of the candidate circuit, and perform iterative training of the increase/decrease analysis until the required The second objective function, wherein the second objective function indicates that the error between the current actual output and the standard output does not exceed a preset second threshold; If the number of iterations of the increase/decrease analysis does not exceed the preset third threshold, the current actual output of the candidate circuit will be recorded; the training module 63, specifically also It is used to perform correlation analysis between all the records of the increase-decrease analysis training and the standard output in the data set. If the correlation analysis result is greater than a preset fourth threshold, it is determined that the candidate circuit passes the increase-decrease analysis.

Combined with the scenario example, the increase or decrease analysis is used to analyze whether the function of the circuit can meet the user's needs. The data of the dataset is constructed according to user requirements. The training module 63 sequentially obtains the input of the data set and uses the second objective function to train the candidate circuit. If the output of the candidate circuit and the output of the data set are within the error range, it means that the function of the candidate circuit meets the needs of the user.

Based on the above embodiments, whether the candidate circuit can achieve the circuit characteristics designed by the user is verified through the second objective function.

In the above scheme, the candidate circuits are qualitatively analyzed, and the candidate circuits that can circulate normally and meet the circuit characteristics designed by the user are screened out. Next, the quantitative analysis process is exemplified.

In an example, the training module 63 is specifically configured to use the standard input in the data set as the simulation input of the candidate circuit, simulate the candidate circuit based on a circuit simulator, and obtain the simulation output of the candidate circuit And, according to the initial value of the device design parameter and the predetermined standard deviation range, the current training design parameter is randomly generated; the training module 63 is specifically also used for according to the current training design parameter and the corresponding simulation output, based on the probability class algorithm, training a prediction model for predicting device design parameters based on the simulation output; using the simulation output of the candidate circuit as an input, obtaining the device design parameters output by the prediction model and the standard deviation range of the output; the training module 63, specifically also For randomly generating the current training design parameters according to the output device design parameters and the standard deviation range of the output; The step of outputting a prediction model for predicting device design parameters, until the number of model training times exceeds a preset fifth threshold, the device design parameters currently output by the prediction model are used as the device design parameters of the candidate circuit, and the candidate circuit is determined. circuit by quantitative analysis.

Combining the scene example, quantitative analysis is used to obtain the device design parameters of the circuit. The device design parameters are the property parameters of the device itself, such as the device design parameters of the resistor, that is, the resistance value of the resistor. The training module 63 generates a series of device design parameters within a predetermined standard deviation range according to the initial values of the device design parameters set by the user. The simulation output is obtained by simulating the input data in the candidate circuit input data set. Iterative training optimizes device design parameters by simulating a model that outputs a model that predicts a range of device design parameters.

Optionally, a hash table is constructed using the simulation output as the key and the corresponding circuit as the value.

Based on the above embodiments, the training module 63 optimizes and obtains the final device design parameters by training the simulation output prediction device design parameter model.

In the above scheme, the candidate circuit is analyzed to obtain the optimized circuit, and then the selection stage of the optimized circuit is performed to obtain the final circuit.

In one example, the screening module 64 is specifically configured to perform screening processing on the candidate circuits that have passed the quantitative analysis, and push the screened candidate circuits to the user; the screening module 64 is also specifically configured to use the candidate circuits selected by the user as final circuit.

Optionally, draw each key of the hash table into a radar chart, and if there is a radar chart a included in the radar chart b, screen out the radar chart a.

Taking the example of the scene as an example, the screening module 64 pushes the candidate circuits through the quantitative analysis to the user through a screening process, and the user can select a suitable circuit according to requirements.

Based on the above embodiments, the final circuit is determined through user selection, so that the final circuit meets user requirements.

In the circuit generation apparatus provided in this embodiment, an acquisition module is configured to acquire circuit design parameters, where the circuit design parameters include expected circuit characteristics, an upper limit of the number of devices, and the number of device ports; a data set is established according to the expected circuit characteristics ; a building module for constructing multiple candidate circuits based on the neural network model according to the number of device ports, the upper limit value of the number of devices and the type of candidate devices; a training module for each candidate circuit, based on a fixed device Design parameters and data sets, and obtain the device port parameters of the candidate circuit through feasible analysis training; if the feasibility analysis is passed, increase or decrease the candidate circuit according to the data set and the actual output of the candidate circuit until the actual output of the candidate circuit matches the data set; if the increase/decrease analysis is passed, then according to the data set and the simulation output of the candidate circuit, the device of the candidate circuit is obtained through quantitative analysis and training Design parameters; wherein, the device port parameters include electrical signal parameters of each port of the device, and the data set includes multiple sets of standard inputs and corresponding standard outputs; a screening module is used to obtain the final circuit according to the candidate circuits that have passed quantitative analysis. . In the above scheme, a circuit is constructed through a neural network model, and the final circuit is obtained through analysis and screening, thereby generating a circuit, reducing manual operations and improving efficiency.

Embodiment 3

Fig. 5 is an apparatus block diagram of a circuit generating apparatus according to an exemplary embodiment, the apparatus may be a mobile phone, a computer, a digital broadcasting terminal, a message sending and receiving device, a game console, a tablet device, a medical device, a fitness device, Personal digital assistants, etc.

Apparatus 800 may include one or more of the following components: processing component 802 , memory 804 , power supply component 806 , multimedia component 808 , audio component 810 , input/output interface 812 , sensor component 814 , and communication component 816 .

The processing component 802 generally controls the overall operation of the device 800, such as operations associated with display, phone calls, data communications, camera operations, and recording operations. The processing component 802 can include one or more processors 820 to execute instructions to perform all or some of the steps of the methods described above. Additionally, processing component 802 may include one or more modules that facilitate interaction between processing component 802 and other components. For example, processing component 802 may include a multimedia module to facilitate interaction between multimedia component 808 and processing component 802.

Memory 804 is configured to store various types of data to support operations at device 800 . Examples of such data include instructions for any application or method operating on device 800, contact data, phonebook data, messages, pictures, videos, and the like. Memory 804 may be implemented by any type of volatile or nonvolatile storage device or combination thereof, such as static random access memory (SRAM), electrically erasable programmable read only memory (EEPROM), erasable Programmable Read Only Memory (EPROM), Programmable Read Only Memory (PROM), Read Only Memory (ROM), Magnetic Memory, Flash Memory, Magnetic or Optical Disk.

Power supply assembly 806 provides power to the various components of device 800 . Power components 806 may include a power management system, one or more power supplies, and other components associated with generating, managing, and distributing power to device 800 .

Multimedia component 808 includes a screen that provides an output interface between the device 800 and the user. In some embodiments, the screen may include a liquid crystal display (LCD) and a touch panel (TP). If the screen includes a touch panel, the screen may be implemented as a touch screen to receive input signals from a user. The touch panel includes one or more touch sensors to sense touch, swipe, and gestures on the touch panel. The touch sensor may not only sense the boundaries of a touch or swipe action, but also detect the duration and pressure associated with the touch or swipe action. In some embodiments, multimedia component 808 includes a front-facing camera and/or a rear-facing camera. When the apparatus 800 is in an operation mode, such as a shooting mode or a video mode, the front camera and/or the rear camera may receive external multimedia data. Each of the front and rear cameras can be a fixed optical lens system or have focal length and optical zoom capability.

Audio component 810 is configured to output and/or input audio signals. For example, audio component 810 includes a microphone (MIC) that is configured to receive external audio signals when device 800 is in operating modes, such as call mode, recording mode, and voice recognition mode. The received audio signal may be further stored in memory 804 or transmitted via communication component 816 . In some embodiments, audio component 810 also includes a speaker for outputting audio signals.

The I/O interface 812 provides an interface between the processing component 802 and a peripheral interface module, which may be a keyboard, a click wheel, a button, or the like. These buttons may include, but are not limited to: home button, volume buttons, start button, and lock button.

Sensor assembly 814 includes one or more sensors for providing status assessment of various aspects of device 800 . For example, the sensor assembly 814 can detect the open/closed state of the device 800, the relative positioning of components, such as the display and keypad of the device 800, and the sensor assembly 814 can also detect a change in the position of the device 800 or a component of the device 800 , the presence or absence of user contact with the device 800 , the orientation or acceleration/deceleration of the device 800 and the temperature change of the device 800 . Sensor assembly 814 may include a proximity sensor configured to detect the presence of nearby objects in the absence of any physical contact. Sensor assembly 814 may also include a light sensor, such as a CMOS or CCD image sensor, for use in imaging applications. In some embodiments, the sensor assembly 814 may also include an acceleration sensor, a gyroscope sensor, a magnetic sensor, a pressure sensor, or a temperature sensor.

Communication component 816 is configured to facilitate wired or wireless communication between apparatus 800 and other devices. Device 800 may access wireless networks based on communication standards, such as WiFi, 2G or 3G, or a combination thereof. In one exemplary embodiment, the communication component 816 receives broadcast signals or broadcast related information from an external broadcast management system via a broadcast channel. In an exemplary embodiment, the communication component 816 also includes a near field communication (NFC) module to facilitate short-range communication. For example, the NFC module may be implemented based on radio frequency identification (RFID) technology, infrared data association (IrDA) technology, ultra-wideband (UWB) technology, Bluetooth (BT) technology and other technologies.

In an exemplary embodiment, apparatus 800 may be implemented by one or more application specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field programmable A gate array (FPGA), controller, microcontroller, microprocessor or other electronic component implementation is used to perform the above method.

In an exemplary embodiment, there is also provided a non-transitory computer-readable storage medium including instructions, such as a memory 804 including instructions, executable by the processor 820 of the apparatus 800 to perform the method described above. For example, the non-transitory computer-readable storage medium may be ROM, random access memory (RAM), CD-ROM, magnetic tape, floppy disk, optical data storage device, and the like.

Embodiment 4

FIG. 6 is a schematic structural diagram of an electronic device provided in an embodiment of the application. As shown in FIG. 6 , the electronic device includes:

A processor (processor) 291, and the electronic device further includes a memory (memory) 292; and may also include a communication interface (Communication Interface) 293 and a bus 294. The processor 291 , the memory 292 , and the communication interface 293 can communicate with each other through the bus 294 . The communication interface 293 may be used for information transfer. The processor 291 may invoke logic instructions in the memory 292 to perform the methods of the above-described embodiments.

In addition, the above-mentioned logic instructions in the memory 292 may be implemented in the form of software functional units and may be stored in a computer-readable storage medium when sold or used as an independent product.

As a computer-readable storage medium, the memory 292 may be used to store software programs and computer-executable programs, such as program instructions/modules corresponding to the methods in the embodiments of the present application. The processor 291 executes functional applications and data processing by running the software programs, instructions and modules stored in the memory 292, that is, to implement the methods in the above method embodiments.

The memory 292 may include a storage program area and a storage data area, wherein the storage program area may store an operating system, an application program required for at least one function; the storage data area may store data created according to the use of the terminal device, and the like. Additionally, memory 292 may include high-speed random access memory, and may also include non-volatile memory.

Embodiments of the present application provide a non-transitory computer-readable storage medium, where computer-executable instructions are stored in the computer-readable storage medium, and when the computer-executable instructions are executed by a processor, are used to implement the methods described in the foregoing embodiments. method.

Other embodiments of the present application will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses or adaptations of this application that follow the general principles of this application and include common knowledge or conventional techniques in the technical field not disclosed in this application . The specification and examples are to be regarded as exemplary only, with the true scope and spirit of the application being indicated by the following claims.

It is to be understood that the present application is not limited to the precise structures described above and illustrated in the accompanying drawings and that various modifications and changes may be made without departing from the scope thereof. The scope of the application is limited only by the appended claims.

Claims (12)

1. A circuit generation method, comprising:

obtaining circuit design parameters, wherein the circuit design parameters comprise expected circuit characteristics, upper limit values of the number of devices and the number of ports of the devices; establishing a data set based on the desired circuit characteristic;

constructing a plurality of candidate circuits based on a neural network model according to the number of the device ports, the upper limit value of the number of the devices and the types of the candidate devices;

for each candidate circuit, obtaining device port parameters of the candidate circuit through feasible analysis training based on fixed device design parameters and a data set; if the feasibility analysis passes, performing additive-subtractive analysis on the candidate circuit according to the data set and the actual output of the candidate circuit until the actual output of the candidate circuit matches the data set; if the additive and subtractive analysis passes, obtaining device design parameters of the candidate circuit through quantitative analysis training according to the data set and the simulation output of the candidate circuit; the device port parameters comprise electric signal parameters of each port of the device, and the data set comprises multiple groups of standard inputs and corresponding standard outputs;

and obtaining a final circuit according to the candidate circuit through quantitative analysis.

2. The method of claim 1, wherein obtaining, for each candidate circuit, device port parameters for the candidate circuit by performing feasible analysis training based on fixed device design parameters comprises:

performing iterative training of feasibility analysis based on a first objective function as an optimization target of an optimizer until the first objective function is met, wherein the first objective function represents that the voltage input to each port and the voltage output to the port are equal and the current sum is equal to 0;

if the iteration number of the feasibility analysis exceeds a preset first threshold value, screening out the candidate circuit; if the number of iterations of the feasibility analysis does not exceed the first threshold, determining that the candidate circuit passes the feasibility analysis.

3. The method of claim 1, wherein the incrementally and decreasingly analyzing the candidate circuit based on the data set and the actual output of the candidate circuit until the actual output of the candidate circuit matches the data set if the feasibility analysis passes comprises:

if the feasibility analysis is passed, taking each standard input in the data set as an actual input of the candidate circuit, and performing iterative training of additive-subtractive analysis until a second objective function is met, wherein the second objective function represents that the error between the current actual output and the standard output does not exceed a preset second threshold;

if the iteration times of the incremental analysis exceed a preset third threshold, recording that the training is 0; if the iteration times of the current increasing and decreasing analysis do not exceed a preset third threshold, recording the current actual output of the candidate circuit;

and performing correlation analysis on all records of the additive and subtractive analysis training and the standard output in the data set, and if the correlation analysis result is greater than a preset fourth threshold, judging that the candidate circuit passes the additive and subtractive analysis.

4. The method of claim 1, wherein obtaining device design parameters of the candidate circuit by quantitative analysis training based on the data set and simulation output of the candidate circuit if the additive/subtractive analysis passes comprises:

taking the standard input in the data set as the simulation input of the candidate circuit, and simulating the candidate circuit based on a circuit simulator to obtain the simulation output of the candidate circuit; randomly generating current training design parameters according to the initial values of the device design parameters and a preset standard deviation range;

training a prediction model for predicting device design parameters based on simulation output based on a probability algorithm according to current training design parameters and corresponding simulation output; taking the simulation output of the candidate circuit as input, and obtaining device design parameters output by the prediction model and the output standard deviation range;

randomly generating current training design parameters according to the output device design parameters and the output standard deviation range; and executing the step of training a prediction model for predicting the device design parameters based on the simulation output based on the probability algorithm again according to the current training design parameters and the corresponding simulation output until the model training times exceed a preset fifth threshold, taking the device design parameters currently output by the prediction model as the device design parameters of the candidate circuit, and judging that the candidate circuit passes the quantitative analysis.

5. The method according to any one of claims 1-4, wherein obtaining a final circuit from the candidate circuits by quantitative analysis comprises:

screening the candidate circuits which pass the quantitative analysis, and pushing the screened candidate circuits to a user;

and taking the candidate circuit selected by the user as a final circuit.

6. A circuit generation apparatus, comprising:

the circuit design method comprises the steps of obtaining circuit design parameters, wherein the circuit design parameters comprise expected circuit characteristics, upper limit values of the number of devices and the number of ports of the devices; establishing a data set according to the desired circuit characteristics;

the building module is used for building a plurality of candidate circuits based on a neural network model according to the number of the device ports, the upper limit value of the number of the devices and the types of the candidate devices;

the training module is used for obtaining device port parameters of the candidate circuit through feasible analysis training based on fixed device design parameters and a data set aiming at each candidate circuit; if the feasibility analysis passes, performing additive-subtractive analysis on the candidate circuit according to the data set and the actual output of the candidate circuit until the actual output of the candidate circuit matches the data set; if the additive and subtractive analysis passes, obtaining device design parameters of the candidate circuit through quantitative analysis training according to the data set and the simulation output of the candidate circuit; the device port parameters comprise electric signal parameters of each port of the device, and the data set comprises multiple groups of standard inputs and corresponding standard outputs;

and the screening module is used for obtaining a final circuit according to the candidate circuit which passes the quantitative analysis.

7. The apparatus of claim 6,

the training module is specifically configured to perform iterative training of feasibility analysis based on a first objective function as an optimization target of the optimizer until the first objective function is satisfied, where the first objective function represents that voltages input to each port and output to the port are equal and a sum of currents is equal to 0;

the training module is specifically further configured to screen out the candidate circuit if the number of iterations of the feasibility analysis exceeds a preset first threshold; if the number of iterations of the feasibility analysis does not exceed the first threshold, determining that the candidate circuit passes the feasibility analysis.

8. The apparatus of claim 6,

the training module is specifically configured to perform iterative training of additive-subtractive analysis by using each standard input in the data set as an actual input of the candidate circuit if the feasibility analysis passes until a second objective function is satisfied, where an error between a current actual output and a standard output, which is characterized by the second objective function, does not exceed a preset second threshold;

if the iteration number of the incremental analysis exceeds a preset third threshold, recording the training as 0; if the iteration times of the current increasing and decreasing analysis do not exceed a preset third threshold, recording the current actual output of the candidate circuit;

the training module is specifically configured to perform correlation analysis on all records of the incremental and incremental analysis training and the standard output in the data set, and if a correlation analysis result is greater than a preset fourth threshold, determine that the candidate circuit passes the incremental and incremental analysis.

9. The apparatus of claim 6, wherein obtaining device design parameters of the candidate circuit by quantitative analysis training based on the data set and simulation output of the candidate circuit if the additive/subtractive analysis passes comprises:

the training module is specifically configured to use a standard input in the data set as a simulation input of the candidate circuit, and simulate the candidate circuit based on a circuit simulator to obtain a simulation output of the candidate circuit; randomly generating current training design parameters according to the initial values of the device design parameters and a preset standard deviation range;

the training module is specifically used for training a prediction model for predicting device design parameters based on simulation output based on a probability algorithm according to current training design parameters and corresponding simulation output; taking the simulation output of the candidate circuit as input, and obtaining device design parameters output by the prediction model and the output standard deviation range;

the training module is specifically used for randomly generating current training design parameters according to the output device design parameters and the output standard deviation range; and executing the step of training a prediction model for predicting the device design parameters based on the simulation output based on the probability algorithm again according to the current training design parameters and the corresponding simulation output until the model training times exceed a preset fifth threshold, taking the device design parameters currently output by the prediction model as the device design parameters of the candidate circuit, and judging that the candidate circuit passes the quantitative analysis.

10. The apparatus according to any one of claims 6-9, wherein:

the screening module is specifically used for screening the candidate circuits which pass the quantitative analysis and pushing the screened candidate circuits to a user;

the screening module is specifically further configured to use the candidate circuit selected by the user as the final circuit.

11. An electronic device, comprising: a processor, and a memory communicatively coupled to the processor;

the memory stores computer-executable instructions;

the processor executes computer-executable instructions stored by the memory to implement the method of any of claims 1-5.

12. A computer-readable storage medium having computer-executable instructions stored therein, which when executed by a processor, are configured to implement the method of any one of claims 1-5.

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