CN114979522A - An adaptive pixel-level high dynamic CMOS image sensor and its realization method - Google Patents

Abstract

The invention discloses a self-adaptive pixel-level high-dynamic CMOS image sensor and a realization method thereof.A pixel array outputs photoelectric signals which are respectively input to a column-level ADC reading circuit and a pixel-level ADC circuit; a comparator in the column ADC readout circuit receives the photoelectric signal and the ramp signal respectively, and the comparison result is transmitted to a data synthesizer through a counter; the comparison unit in the pixel ADC circuit receives the photoelectric signal and the reference signal respectively, the comparison result is processed by the register unit and then is transmitted to the control unit and the data synthesizer respectively, the control unit generates control duration data and feeds the control duration data back to the pixel array, and the final result is generated in the data synthesizer and is output. The high real-time characteristic of the pixel level ADC circuit and the high-precision characteristic of the column level ADC reading circuit are organically combined, the final result is output by the data synthesizer, and the high dynamic imaging requirement is met when the light ray changes rapidly.

Description

An adaptive pixel-level high dynamic CMOS image sensor and its realization method

technical field

The invention belongs to the technical field of image sensors, and relates to an adaptive pixel-level high dynamic CMOS image sensor and a realization method thereof.

Background technique

CMOS image sensors are widely used in space exploration, earth observation, industrial monitoring and consumer electronics. Through various types of complex light collection, application requirements such as target acquisition, detection perception and imaging shooting are realized. The dynamic range of the CMOS image sensor is the range that can monitor the light intensity. Due to the limited well capacity of the device, when the incident light is too strong, the pixels are quickly saturated, resulting in the loss of strong light information. In nature, from direct sunlight to dark night, the dynamic range reaches 180dB. A sensor with a wider dynamic range can detect a wider range of scene illumination, which can produce more detailed images. Improving the dynamic range of the device is conducive to good scientific detection, industrial application and imaging quality, and is of great value to improving scientific and technological strength and national life.

The currently adopted high dynamic range implementation schemes include: potential well capacity adjustment technology, multiple sampling technology, and logarithmic response technology. Potential well capacity adjustment technology, adding lateral overflow gates, and increasing the potential well capacity by one or several times during exposure, which can compress the transfer curve of the CMOS image sensor charge as a function of light intensity. Multi-sampling technology, the same scene is sampled multiple times at different exposure times, and then the output of the multiple samples is combined into an image with a large dynamic range. The logarithmic response technology utilizes the characteristics of diode-connected MOS transistors operating in the subthreshold region to obtain the photodiode logarithmic response transfer curve.

The high dynamic implementation method in the prior art mainly adopts a planar 2D structure, and adopts a single pixel-level ADC or column-level ADC. 8 is an overall structural diagram of a high-dynamic image sensor in the prior art. The pixel array and the column-level ADC readout circuit are in the same plane, and photoelectric conversion and analog-to-digital conversion are completed respectively. The high-dynamic configuration signal is input through the external SPI interface through light judgment. To achieve dynamic range improvement. See Figure 9 for the specific structure diagram. The pixel array includes a global exposure control tube, a transfer tube, a high dynamic reset tube, a source follower tube and a readout control tube. The column-level ADC readout circuit includes a comparator and a counter, and the high dynamic range is adjusted by external configuration. The voltage and control time of the tube can achieve the high dynamic target, but the high dynamic mode is judged by the shooting scene, and the feedback cycle is long, which cannot adapt to the shooting scene with high-speed change of light and dark, can not meet the high dynamic imaging requirements, and does not make full use of the vertical space, There is also room for improvement in space utilization.

SUMMARY OF THE INVENTION

The purpose of the present invention is to solve the problem in the prior art that only a single ADC is used for high dynamic calibration, the real-time performance is poor, and the requirements for high dynamic imaging cannot be met under the condition of rapid light change, and an adaptive pixel-level high dynamic CMOS image sensor is provided. and its implementation method.

To achieve the above object, the present invention adopts the following technical solutions to realize:

An adaptive pixel-level high dynamic CMOS image sensor includes a pixel array, a column-level ADC readout circuit and a pixel-level ADC circuit;

The pixel array and the column-level ADC readout circuit are arranged on the upper-layer chip, the pixel-level ADC circuit is arranged on the lower-layer chip, and a 3D stacking structure is used between the upper-layer chip and the lower-layer chip;

The pixel array outputs photoelectric signals, and the photoelectric signals are respectively input to the column-level ADC readout circuit and the pixel-level ADC circuit;

The column-level ADC readout circuit includes a comparator, a counter and a data synthesizer, the negative terminal of the comparator receives the photoelectric signal, the positive terminal inputs the ramp signal, and the comparison result is transmitted to the data synthesizer through the counter;

The pixel-level ADC circuit includes a comparison unit, a control unit, and a register unit. The positive end of the comparison unit receives the photoelectric signal, and the negative end receives the reference signal. After the comparison result is processed by the register unit, it is respectively sent to the control unit and the data synthesizer. The unit generates control duration data and feeds it back to the pixel array, where the final result output is produced in the data synthesizer.

A further improvement of the present invention is:

The pixel array includes a global exposure control tube, a transfer tube, a high dynamic reset tube, a source follower tube, a readout control tube, a diode and a capacitor, and the drains of the global exposure control tube, the high dynamic reset tube and the source follower tube are all connected to VDD , the source of the global exposure control tube is connected to the source of the transfer tube and then grounded through a diode. The drain of the transfer tube and the source of the high dynamic reset tube are connected to the FD point, and the FD point is connected to the gate of the source follower tube and through the capacitor. Grounding, the source of the source follower tube is connected to the drain of the readout control tube, and the source of the readout control tube outputs a photoelectric signal.

The comparison unit includes a first comparator, a second comparator and a third comparator. The positive input terminals of the first comparator, the second comparator and the third comparator are all photoelectric signals, and the negative input terminals are respectively the reference voltage. Level high VREFH, reference level VREF, and reference level low VREFL.

The reference level high VREFH, the reference level VREF and the reference level low VREFL are specifically expressed as:

Among them, V0 is the output voltage value under the pixel reset condition, and V_fullscale is the difference between the voltage value output when the pixel is saturated and the voltage value output when the pixel is reset.

The register unit is a truth table register, and compares the output result of the comparison unit with the value in the truth table register to judge the light intensity.

A copper-copper interconnect structure is used between the upper-layer chip and the lower-layer chip.

A method for implementing an adaptive pixel-level high dynamic CMOS image sensor, comprising the following steps:

The pixel array outputs photoelectric signals, and the comparison unit of the pixel-level ADC circuit receives the photoelectric signals for comparison, and inputs them to the positive input terminals of the first comparator, the second comparator and the third comparator respectively, and the negative input terminals are respectively the reference level High VREFH, reference level VREF and reference level low VREFL, output digital signal after the comparison is completed;

Compare the digital signal in the truth table register to judge the light intensity, the truth table register outputs the corresponding high-order digital signal to the data synthesizer, and determines the time controller to output the corresponding control duration data, the time controller will control the The duration data is fed back to the pixel array, and the high dynamic reset tube is adjusted in real time;

The photoelectric signal is input to the negative input terminal of the comparator and compared with the ramp signal. When the photoelectric signal is greater than the ramp signal, the comparator turns over, the counter counts once, and the counting result is sent to the data synthesizer;

The data synthesizer synthesizes the received data and outputs the final result.

When the photoelectric signal is smaller than VREFL, the comparison unit outputs 000; when the photoelectric signal is smaller than VREF, the comparison unit outputs 001; when the photoelectric signal is smaller than VREFH, the comparison unit outputs 011; when the photoelectric signal is larger than VREFH, the comparison unit outputs 111.

Compared with the prior art, the present invention has the following beneficial effects:

By using the photoelectric signal output by the pixel array, the real-time detection and processing of light and the comparative calculation of the control time are realized in the pixel-level ADC circuit to achieve the goal of high dynamic control, and the high real-time characteristics of the pixel-level ADC circuit are realized. It is organically combined with the high-precision characteristics of the column-level ADC readout circuit, and the final result is output by the data synthesizer. When the light changes rapidly, high dynamic imaging requirements are achieved, and the vertical space is fully utilized by using a 3D stacking structure.

Description of drawings

In order to describe the technical solutions of the embodiments of the present invention more clearly, the following briefly introduces the accompanying drawings that need to be used in the embodiments. It should be understood that the following drawings only show some embodiments of the present invention, and therefore do not It should be regarded as a limitation of the scope, and for those of ordinary skill in the art, other related drawings can also be obtained according to these drawings without any creative effort.

1 is an overall structural diagram of an adaptive pixel-level high dynamic CMOS image sensor of the present invention;

2 is a specific structural diagram of an adaptive pixel-level high dynamic CMOS image sensor of the present invention;

Fig. 3 is the sensor pre-exposure timing chart of the present invention;

4 is a high dynamic timing diagram of the sensor of the present invention;

Figure 5 is a high dynamic reset tube voltage diagram;

Fig. 6 is the high dynamic voltage curve of the sensor of the present invention;

Fig. 7 is the sensor working flow chart of the present invention;

8 is an overall structural diagram of a high dynamic image sensor in the prior art;

FIG. 9 is a specific structural diagram of a high dynamic image sensor in the prior art.

Among them: 101-pixel array, 102-column-level ADC readout circuit, 103-pixel-level ADC circuit, 10-global exposure control tube; 11-transmission tube; 12-high dynamic reset tube; 13-source follower tube; 14- Readout control tube; 15-first comparator; 16-second comparator; 17-third comparator; 18-time controller; 19-truth table register; 20-comparator; 21-counter; 22- data synthesizer.

Detailed ways

In order to make the purposes, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments These are some embodiments of the present invention, but not all embodiments. The components of the embodiments of the invention generally described and illustrated in the drawings herein may be arranged and designed in a variety of different configurations.

Thus, the following detailed description of the embodiments of the invention provided in the accompanying drawings is not intended to limit the scope of the invention as claimed, but is merely representative of selected embodiments of the invention. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

It should be noted that like numerals and letters refer to like items in the following figures, so once an item is defined in one figure, it does not require further definition and explanation in subsequent figures.

In the description of the embodiments of the present invention, it should be noted that if the terms "upper", "lower", "horizontal", "inside", etc. appear, the orientation or positional relationship indicated is based on the orientation or positional relationship shown in the accompanying drawings , or the orientation or positional relationship that the product of the invention is usually placed in use, it is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed in a specific orientation and operation, and therefore should not be construed as limiting the present invention. Furthermore, the terms "first", "second", etc. are only used to differentiate the description and should not be construed to indicate or imply relative importance.

Furthermore, the presence of the term "horizontal" does not imply that the component is required to be absolutely horizontal, but rather may be tilted slightly. For example, "horizontal" only means that its direction is more horizontal than "vertical", it does not mean that the structure must be completely horizontal, but can be slightly inclined.

In the description of the embodiments of the present invention, it should also be noted that, unless otherwise expressly specified and limited, the terms "set", "installed", "connected" and "connected" should be understood in a broad sense. It can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate medium, and it can be internal communication between two components. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific situations.

Below in conjunction with accompanying drawing, the present invention is described in further detail:

Referring to FIG. 1, it is an overall structural diagram of an adaptive pixel-level high dynamic CMOS image sensor of the present invention, including a pixel array 101, a column-level ADC readout circuit 102 and a pixel-level ADC circuit, and the pixel array 101 and the column-level ADC circuit 102 are provided in On the upper-layer chip, the pixel-level ADC circuit 103 is arranged on the lower-layer chip, and the nodes of the upper-layer chip and the lower-layer chip are connected by metal connecting posts.

Referring to FIG. 2, it is a specific structural diagram of the adaptive pixel-level high dynamic CMOS image sensor of the present invention, including a global exposure control tube 10, a transfer tube 11, a high dynamic reset tube 12, a source follower tube 13, a readout tube in the pixel array 101 Control tube 14, diodes and capacitors, comparator 20, counter 21 and data synthesizer 22 in column-level ADC readout circuit 102, first comparator 15, second comparator 16, third comparator in pixel-level ADC circuit 103 The comparator 17, the time controller 18 and the truth table register 19, the drains of the global exposure control tube 10, the high dynamic reset tube 12 and the source follower tube 13 are all connected to VDD, and the source of the global exposure control tube 10 is connected to the transmission tube 11 The source of the MOSFET is connected to ground through a diode, the drain of the transfer transistor 11 and the source of the high dynamic reset transistor 12 are connected to the FD point, the FD point is connected to the gate of the source follower transistor 13 and grounded through a capacitor, and the source follows the source of the transistor 13. The pole is connected to the drain of the readout control tube 14, and the source of the readout control tube 14 outputs the photoelectric signal; the negative end of the comparator 20 receives the photoelectric signal, the positive end inputs the ramp signal, and the comparison result is transmitted to the data synthesizer 22 through the counter 21 ; The comparison unit includes a first comparator 15, a second comparator 16 and a third comparator 17, the positive input terminals of the first comparator 15, the second comparator 16 and the third comparator 17 are all photoelectric signals, and the negative input The terminals are the reference level high VREFH, the reference level VREF and the reference level VREFL respectively. The photoelectric signal is compared with the reference signal and then outputs the thermometer code, which is compared in the truth table register 19 to determine the light intensity and the true value. The table register 19 outputs the corresponding high-order digital signal to the data synthesizer 22, and determines that the time controller 18 outputs the corresponding control duration data. The time controller 18 feeds back the control duration data to the pixel array 101, and the high dynamic reset tube 12 performs Real-time adjustment; the photoelectric signal is input to the negative input end of the comparator 20 and compared with the ramp signal, when the photoelectric signal is greater than the ramp signal, the comparator 20 is turned over, the counter 21 counts once, and the counting result is sent to the data synthesizer 22; The data synthesizer 22 synthesizes the received data and outputs the final result.

Referring to FIG. 3 is the sensor pre-exposure timing diagram of the present invention, the global exposure control tube 10 is used as a global reset control switch, and is turned on once at the beginning of each frame to reset the photodiodes of the entire pixel array; Before the image signal is transferred from PD to FD, the high dynamic reset tube 12 is turned on to reset the FD; after the reset of the FD point is completed, the transmission tube 11 of the entire pixel array is turned on at the same time, and the image signal is transferred from the PD to the FD point. In the pixel-level ADC structure, all pixels are executed in parallel, the row selection switch source follower tube 13 is turned on, the light intensity electrical signal is read out, and enters the column-level ADC readout circuit 102 . The photoelectric signal is compared with the reference level high VREFH, the reference level VREF, and the reference level low VREFL through the comparators 15-17. The output voltage value is Vf when the pixel is saturated, and the output voltage value is V0 under the pixel reset condition. The difference between the two is the pixel output swing V_fullscale, where the voltage values of VREFL, VREF, and VREFH are:

As shown in Table 1, the output of the comparator is a thermometer code, and the values of t1 to t3 are determined by comparing the truth table. Among them, A, B, and C are the outputs of comparators 15 to 17 respectively. Since the stronger the light intensity, the lower the pixel output voltage value, so when the light intensity is very strong, the output voltage of PIXEL_OUT is less than VREFL, and ABC outputs 000; When the light intensity is strong, the output voltage of PIXEL_OUT is less than VREF, and ABC outputs 001; when the light intensity is weak, the output voltage of PIXEL_OUT is less than VREFH, and ABC outputs 011; when the light intensity is weak, the output voltage of PIXEL_OUT is greater than VREFH, and ABC outputs 111. The corresponding t1~t3 settings are shown in Table 1 to meet different high dynamic requirements. As shown in Figure 4, the total duration of t1~t3 is the exposure duration t, which is configured by the user according to the device usage requirements. The truth table Listed in is the constant proportional relationship between t1 and t3. If the light intensity is weak light, t1 to t3 are all 0, and the high dynamic reset tube 12 is connected to the power supply voltage during exposure t.

Table 1 Corresponding truth table of light intensity and high dynamic timing

PIXEL-OUT A B C t1 t2 t3 light intensity MSB<0> MSB<1> ≤VREFL 0 0 0 2 4 6 powerful 0 0 ≤VREF 0 0 1 4 4 4 strong 0 1 ≤VREFH 0 1 1 6 4 2 weaker 1 0 ≥VREFH 1 1 1 0 0 0 weak 1 1

In the pixel reset stage, as shown in FIG. 5, the voltage on the high dynamic reset transistor 12 is 3.3V. At this time, the potential barrier of the transistor is low, and the photocurrent is discharged through the transistor; then, the high dynamic reset transistor 12 is powered by 3.3V is reduced to the voltage value of V1 and lasts for t1 time. V1 is 1.4V by default. Because the voltage of the high dynamic reset tube 12 is lowered, the potential barrier of the tube is raised. Since the voltage on the photodiode at this time is Vpd>V1-Vth, the photocurrent Integrate, Vpd decreases accordingly. When Vpd<V1-Vth, the high dynamic reset tube 12 is turned on, and the photocurrent integration stops. At this time, the charge accumulated by the PD is Qh(t), and Qh(t) reflects when the high dynamic reset When the gate voltage of the transistor 12 is lowered, the maximum amount of charge that the photodiode can accumulate. When the accumulated charge is greater than Qh(t), the excess charge will force the high dynamic reset transistor 12 to conduct, and transmit through VDD, high dynamic reset transistor 12, and transmission. The loop formed by tube 11, photodiode 10, and GND is discharged; then the gate voltage of the high dynamic reset tube 12 is reduced to the V2 voltage value again and lasts for t2 time. V2 is 1.2V by default. Decrease, Vpd>V2-Vth, so the M2 tube is turned off again, and the photocurrent continues to integrate until Vpd<V2-Vth; then reduce to the V3 voltage value and continue for t3 time, V3 defaults to 1.0V, and will continue to repeat the above process; finally Decrease to V4 voltage and keep it at this voltage level until the end of exposure, V4 defaults to 0.8V, this voltage is very low to prevent the photodiode from being overexposed.

FIG. 6 is the result of the piecewise linear response of the sensor pixel brought about by the change of the gate voltage of the high dynamic reset transistor 12 . As can be seen from the figure, when the brightness is high, the output slope becomes slower, and the dynamic range is extended.

Figure 7 shows the overall execution process. Through pre-integration, the photoelectric signal is output, and the photoelectric signal is compared with the reference. The 3D stacked chip-level ADC is used to judge the light intensity, and the segment integration time length is controlled according to the strong and weak light results. Then low-bit conversion and high-low-bit ADC data synthesis are performed by column-level ADC to realize adaptive high-dynamic image sensor.

An embodiment of the present invention provides a method for implementing an adaptive pixel-level high dynamic CMOS image sensor, including the following steps:

The pixel array 101 outputs a photoelectric signal, and the photoelectric signal and the reference signal are compared in the comparison unit of the pixel-level ADC circuit 103 to output a digital signal;

According to the digital signal, the truth table register 19 is compared to determine the light intensity. The truth table register 19 outputs the corresponding high-order digital signal to the data synthesizer 22, and determines that the time controller 18 outputs the corresponding control duration data, time The controller 18 feeds back the control duration data to the pixel array 101 to adjust the high dynamic reset tube 12 in real time;

The photoelectric signal is input to the negative input terminal of the comparator 20 for comparison with the ramp signal, when the photoelectric signal is greater than the ramp signal, the comparator 20 is turned over, the counter 21 counts once, and the counting result is sent to the data synthesizer 22;

The data synthesizer 22 synthesizes the received data and outputs the final result.

The above are only preferred embodiments of the present invention, and are not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and changes. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims (8)

1. An adaptive pixel-level high dynamic CMOS image sensor, characterized in that it comprises a pixel array (101), a column-level ADC readout circuit (102) and a pixel-level ADC circuit (103); The pixel array (101) and the column-level ADC readout circuit (102) are arranged on the upper-layer chip, the pixel-level ADC circuit (103) is arranged on the lower-layer chip, and a 3D stacking structure is used between the upper-layer chip and the lower-layer chip; The pixel array (101) outputs photoelectric signals, and the photoelectric signals are respectively input to the column-level ADC readout circuit (102) and the pixel-level ADC circuit (103); The column-level ADC readout circuit (102) includes a comparator (20), a counter (21) and a data synthesizer (22). The negative terminal of the comparator (20) receives the photoelectric signal, the positive terminal inputs the ramp signal, and the comparison result Through the counter (21) to the data synthesizer (22); The pixel-level ADC circuit (103) includes a comparison unit, a control unit, and a register unit. The positive end of the comparison unit receives the photoelectric signal, and the negative end receives the reference signal. After the comparison result is processed by the register unit, it is respectively sent to the control unit and data synthesis. The control unit (22) generates control duration data and feeds it back to the pixel array (101), and the data synthesizer (22) produces the final result output. 2. The adaptive pixel-level high dynamic CMOS image sensor according to claim 1, wherein the pixel array (101) comprises a global exposure control tube (10), a transfer tube (11), a high dynamic reset Tube (12), source follower tube (13), readout control tube (14), diodes and capacitors, the drains of the global exposure control tube (10), the high dynamic reset tube (12) and the source follower tube (13) are all Connect to VDD, the source of the global exposure control tube (10) is connected to the source of the transfer tube (11) and then grounded through a diode, the drain of the transfer tube (11) and the source of the high dynamic reset tube (12) are connected to FD point, the FD point is connected to the gate of the source follower transistor (13) and grounded through a capacitor, the source of the source follower transistor (13) is connected to the drain of the readout control transistor (14), and the source of the readout control transistor (14) Output photoelectric signal. 3. The adaptive pixel-level high dynamic CMOS image sensor according to claim 1, wherein the comparison unit comprises a first comparator (15), a second comparator (16) and a third comparator (17), the positive input terminals of the first comparator (15), the second comparator (16) and the third comparator (17) are all photoelectric signals, and the negative input terminals are respectively the reference level high VREFH, the reference level VREF and reference level low VREFL. 4. An adaptive pixel-level high dynamic CMOS image sensor according to claim 3, wherein the reference level high VREFH, the reference level VREF and the reference level low VREFL are specifically expressed as:

Among them, V0 is the output voltage value under the pixel reset condition, and V_fullscale is the difference between the voltage value output when the pixel is saturated and the voltage value output when the pixel is reset. 5. a kind of adaptive pixel level high dynamic CMOS image sensor as claimed in claim 1, is characterized in that, described register unit is truth table register (19), the output result of contrast comparison unit and truth table register ( 19) to judge the light intensity. 6 . The adaptive pixel-level high dynamic CMOS image sensor according to claim 1 , wherein a copper-copper interconnect structure is used between the upper-layer chip and the lower-layer chip. 7 . 7. A realization method of an adaptive pixel-level high dynamic CMOS image sensor, characterized in that, comprising the following steps: The pixel array (101) outputs the photoelectric signal, and the comparison unit of the pixel-level ADC circuit (103) receives the photoelectric signal for comparison, and respectively inputs the photoelectric signal to the first comparator (15), the second comparator (16) and the third comparator ( 17) The positive input terminal and the negative input terminal are respectively the reference level high VREFH, the reference level VREF and the reference level low VREFL, and the digital signal is output after the comparison is completed; According to the digital signal, the truth table register (19) is compared to judge the light intensity. The truth table register (19) outputs the corresponding high-order digital signal to the data synthesizer (22), and determines the time controller (18). Outputting corresponding control duration data, the time controller (18) feeds back the control duration data to the pixel array (101), and adjusts the high dynamic reset tube (12) in real time; The photoelectric signal is input to the negative input terminal of the comparator (20) for comparison with the ramp signal. When the photoelectric signal is greater than the ramp signal, the comparator (20) is turned over, the counter (21) counts once, and the counting result is sent to the data synthesizer (22) in; The data synthesizer (22) synthesizes the received data and outputs the final result. 8. The method for implementing an adaptive pixel-level high dynamic CMOS image sensor according to claim 7, wherein when the photoelectric signal is less than VREFL, the comparison unit outputs 000; when the photoelectric signal is less than VREF, the comparison unit outputs 000. The unit outputs 001; when the photoelectric signal is less than VREFH, the comparison unit outputs 011; when the photoelectric signal is greater than VREFH, the comparison unit outputs 111.

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