CN114974369A - Non-volatile multi-time programmable memory - Google Patents

Abstract

The present invention relates to a non-volatile multiple-time programmable memory, which comprises: at least one memory cell constructed on a substrate, the memory cell comprising: two adjacent different types of memory cells located in the substrate wells, MOS transistors and MOS capacitors respectively located in the different types of wells, wherein there is a gap with a distance d between the two wells; the MOS transistor includes a floating gate and a floating gate oxide below it, The MOS capacitor includes gate oxide and a coupling region located in the well where the capacitor is located. In the non-volatile memory cell and the memory thereof, two adjacent wells of different types can resist a high voltage higher than the voltage that their PN junctions can usually withstand without breakdown. For example, it can withstand the higher voltages required by the memory during an erase operation, ensuring that the electrons on the floating gate are completely erased.

Description

nonvolatile multiple times programmable memory

technical field

The present invention generally relates to the technical field of memory, and more particularly, to a nonvolatile multi-time programmable memory.

Background technique

In recent years, the application of multi-time programmable non-volatile memory has been rapidly expanded, so multi-time programmable non-volatile memory of various structures has emerged as the times require. One of these structures consists of a MOS floating gate transistor and a MOS capacitor located in two adjacent wells of different types (eg P-well and N-well), where the MOS capacitor acts as a control gate. During programming, electrons migrate from the channel region of the MOS floating gate transistor to the floating gate, and during erasing, the electrons in the floating gate tunnel into the channel below.

In order to simplify the process and reduce wafer cost, multiple-time programmable non-volatile memories are usually parasitic devices, that is, using established process steps and mask levels to build or generate new structures. The tunnel oxide layer corresponding to the floating gate transistor generally uses the gate oxide layer corresponding to the input and output devices (I/O devices) of the chip.

For example, when the memory is generated based on a 5v input-output device (I/O device), during the erase operation, a high voltage of 16-18v needs to be applied between the N-well and the P-well of the memory cell. But the PN junction between the traditional N well and P well can only withstand the voltage of 15-16v. This results in breakdown between the N-well and P-well before the desired erase voltage is reached. After the breakdown, the voltage between the N-well and the P-well is clamped at 15-16v and cannot be raised to the required higher voltage. As a result, electrons in the floating gate cannot be completely erased, that is, incomplete erasing.

Therefore, it is necessary to provide a new multiple-time programmable non-volatile memory cell, which can resist higher high voltages between two adjacent wells of different types, higher than the voltage that its PN junction can usually withstand, and will not break down. For example, it can withstand the higher voltages required in the erase operation of the memory device, ensuring that the electrons on the floating gate are completely erased.

SUMMARY OF THE INVENTION

A first aspect of the present invention relates to a non-volatile multiple-time programmable memory, comprising: at least one memory cell constructed on a substrate, the memory cell comprising: two adjacent memory cells located in the substrate two different types of wells, MOS transistors and MOS capacitors respectively located in the different types of wells, wherein there is a gap with a distance d between the two wells; the MOS transistor includes a floating gate and a floating gate below it Gate oxide, the MOS capacitor includes the gate oxide and a coupling region located in the well where the capacitor is located.

In a preferred embodiment, wherein the gap distance d≤6µm, more preferably the gap distance is 0.2µm≤d≤2.0µm.

In another preferred embodiment, the thickness of the floating gate oxide layer of the MOS transistor is 90-180 Å.

In another preferred embodiment, the floating gate of the MOS transistor extends to cover the capacitor in the adjacent well, forming the upper plate of the capacitor. More preferably, the capacitance value of the MOS capacitor is greater than the gate capacitance of the MOS transistor. More preferably, the coupling region is a heavily doped coupling region.

In yet another preferred embodiment, wherein the substrate is a P-type substrate, and a deep N-well is also constructed thereon, and the two different types of wells are an N-well and a P-well, both located in the deep N well.

In yet another preferred embodiment, the substrates of all memory cells are merged into one body; the memory cells are arranged in multiple rows and columns, the MOS transistors of all memory cells are located in the same type of merged well, and all memory cells are arranged in multiple rows and columns. The MOS capacitance of the cell is also located within the same type of merged well.

In yet another preferred embodiment, the memory according to the present invention further comprises: a bit line connected to the drain of each MOS transistor of a column of memory cells; a common line connected to each of a column of memory cells a source of a MOS transistor; and a word line connected to the heavily doped coupling region of each MOS capacitor of a row of memory cells.

Description of drawings

The specific embodiments of the present invention will be described below with reference to the accompanying drawings. These specific embodiments are only used to illustrate the present invention, and not to limit the scope of the present invention.

Figure 1 shows a top view of a non-volatile memory cell in one embodiment of the present invention.

FIG. 2 shows a cross-sectional view of the memory cell shown in FIG. 1 along section line A-A.

FIG. 3 shows a cross-sectional view of the memory cell shown in FIG. 1 along section line B-B.

FIG. 4 shows the relationship between the breakdown voltage between the P well and the N well and the gap between the two wells in the substrate of the memory cell shown in FIG. 1 .

Fig. 5 shows the I-V graphs of the memory cell shown in Fig. 1 in a read operation after erasing at different erase voltages, where ■ is the curve of the structure with no gap between the P-well and the N-well, ● and ▲ are the curves of the structure with a gap d of 0.8 µm between the P-well and the N-well, respectively.

Figure 6 shows a portion of a 2x2 array of memory cells in one embodiment of the present invention.

The same numbers in the figures indicate the same or similar elements.

Detailed ways

The invention discloses a novel multi-time programmable non-volatile memory cell, the substrate of which includes two adjacent wells of different types and MOS transistors and MOS capacitors respectively located in the two wells. There is a gap d between two adjacent wells of different types, so that the two adjacent wells can resist a higher high voltage, which is much higher than the voltage that the PN junction in the gapless structure can usually withstand, while Breakdown will not occur.

For example, when the memory cell is generated based on a 5v input-output device (I/O device), two adjacent wells of different types in the memory cell can resist the 16-18v erase high voltage required for the erase operation , to ensure complete and complete erasure.

The memory cell and its memory of the present invention can also be used in other operations or occasions that require higher voltages between adjacent wells of different types.

Hereinafter, the present invention will be described and illustrated in detail through specific embodiments. However, it is apparent that various adjustments and changes can be made to these specific embodiments without departing from the spirit and broader scope of the present invention, which are all within the scope of the present invention.

In a preferred embodiment, the non-volatile storage unit includes:

a P-type substrate, a deep N well is located in the P-type substrate, a P well and an N well are adjacently located in the deep N well, and there is a gap d between the P well and the N well;

a PMOS transistor constructed in the N-well, comprising a PMOS gate oxide and a polysilicon gate overlying it;

An NMOS capacitor is built into the P-well, including an N+ coupling region in the P-well, gate oxide, and polysilicon gate overlying it.

The gap d is preferably ≤6.0µm. When the concentration of doping ions in the N-well and P-well is high, the breakdown voltage between the N-well and the P-well is low, and the gap d can be selected to be a relatively large value to improve the compatibility between the N-well and the P-well. withstand voltage. vice versa. When the concentration of doping ions in the N-well and the P-well is low, the breakdown voltage between the N-well and the P-well is high, and the gap d can be selected to be a relatively small value.

For a common non-volatile memory cell, the doping ion concentration in the N-well and the P-well is a conventional value of 10 ¹² /cm ² , and the voltage between the adjacent N-well and P-well can only withstand a voltage of 15-16v. For such a memory cell, in order to improve the withstand voltage value between the N well and the P well, the gap d is preferably ≤2µm, more preferably 0.1-1.2µm, more preferably 0.2-1.0µm, more preferably 0.3-0.9µm, and most preferably Preferably 0.4-0.8 µm.

The existence of this gap can make the voltage between the adjacent N-well and P-well significantly higher than that of the structure without gap. In a structure with a gap, the voltage that can be withstood between adjacent N wells and P wells initially increases significantly with the increase of the gap. When the gap increases to a certain extent, the rising trend of the withstand voltage becomes slower. For a common non-volatile memory cell (the dopant ion concentration in the N-well and P-well is a conventional value of 10 ¹² /cm ² ), when the gap d increases to more than 0.8µm, the rising trend of the withstand voltage becomes slower .

The voltage that the above-mentioned gapped structure of the present invention can withstand can be raised to 20-25v. When the multiple-time programmable memory cell and its memory are generated based on 5v input and output devices (I/O devices), the required erase voltage is generally about 16-18v, and the memory cell and its memory of the present invention can guarantee such a The erase operation is completely thorough and smooth. The memory cell and the memory thereof of the present invention can also be used in other operations or occasions, which require the withstand voltage between adjacent N wells and P wells to reach 18-25v.

The N+ coupling region of the NMOS capacitor is formed by N+ source/drain ion implantation. The polysilicon gate of the NMOS capacitor extends and merges with the gate of the PMOS transistor to form the floating gate of the memory cell. The floating gate is preferably a single layer of polysilicon. The N+ coupling region connects the control word line (WL) to the control gate of the memory cell. The control gate is formed by the channel region of the NMOS capacitor. Thus, the structure of the coupling capacitor consists of the floating gate in the P-well partially overlapping the active region, the underlying gate oxide and the NMOS channel. In order to improve the efficiency of the coupling gate, the coupling capacitance is made much larger than the capacitance of the PMOS gate.

A PMOS transistor, built into the N-well, has a P+ source and drain separated by a P-channel. The gate oxide layer of the PMOS transistor covers the channel to form a tunnel oxide layer.

The memory cells are programmed by channel hot electron tunneling to the floating gate. The erase operation is based on the Fowler-Nordheim tunneling mechanism, which tunnels electrons in the PMOS floating gate into the channel below. The tunnel oxide used for both program and erase operations is the gate oxide over the channel region of the PMOS transistor.

The above-mentioned multiple memory cells can be arranged in multiple rows and columns to form an array or memory. The NMOS capacitors of the memory cells are located in a combined P-well, the PMOS transistors of the memory cells are located in a combined N-well, and all memory cells are located in a combined N-deep well. Each of the non-volatile memory cells in the array can be configured to be programmed and erased independently.

In another preferred embodiment, the MOS transistor may be an NMOS transistor, located in the P-well; the MOS capacitor may be a PMOS capacitor, located in the N-well. In this case, the source and drain of the NMOS transistor are doped with N-type ions, and the coupling region of the PMOS capacitor is doped with P-type ions.

The memory cells of the present invention can be fabricated using processes common in silicon chip fabs with deep sub-micron technology having a feature size of 0.25 μm or less (250 nm). For example, it can be fabricated using a 180nm logic process.

The steps of forming two different types of wells and their gaps d are as follows. On the substrate or deep N well (in the case of a deep N well), a layer of photoresist is applied, and then the area where the second well (eg P well) and gap d are to be formed is masked with a mask, and then Expose and develop to expose the region where the first well (eg, N well) is to be formed. Subsequently, desired dopant atoms (eg, phosphorus atoms to form N-type dopant ions) are implanted into the exposed regions to form a first well (eg, an N-well). Then, deposit another layer of photoresist, and then use a mask to cover the formed first well and the area where the gap d is to be formed, and then perform exposure and development to expose the area where the second well (eg, P well) is to be formed. area. Subsequently, desired dopant atoms (eg, boron atoms to form P-type dopant ions) are implanted into the exposed regions to form a second well (eg, P-well).

The above-mentioned N-type dopant atoms include heteroatoms such as phosphorus, arsenic, or antimony of group V. P-type dopant atoms include group III heteroatoms such as boron, gallium or indium.

The steps of preparing the other components of the above-mentioned memory cells are all conventional steps in the 180nm logic process, and are known to those of ordinary skill in the art.

Hereinafter, a specific preferred embodiment of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 shows a top view of a non-volatile memory cell 100 of the present invention. FIG. 2 is a cross-sectional view thereof along section line A-A, and FIG. 3 is a cross-sectional view thereof along section line B-B.

In this embodiment, as shown in FIGS. 1-3 , the non-volatile memory cell 100 is constructed in a P-type silicon substrate 101 . A deep N well (DNW) 104 is disposed in the P substrate 101 to electrically isolate the memory cells from the substrate. An N-well (NW) 102 and a P-well (PW) 103 are disposed in the deep N-well 104 next to each other. A PMOS transistor 110 is provided in the N well 102 . The PMOS transistor 110 includes a P-type drain 112 and a source 111 . The drain 112 includes a lightly doped region 112A and a heavily doped P+ contact region 112B. The source electrode 111 includes a lightly doped region 111A and a heavily doped P+ contact region 111B.

The source electrode 111 is connected to the common line (COM), and the drain electrode 112 is connected to the bit line (BL). Transistor 110 is surrounded by a shallow trench filled with thick field oxide 114 . Between the source electrode 111 and the drain electrode 112 is a channel region 113 . Overlying the channel 113 is a gate oxide layer 115 . A conductively doped polysilicon gate is placed on top of the gate oxide 115, forming the floating gate 116 of the PMOS transistor.

The floating gate 116 and the gate oxide 115 extend to the P-well 103 and partially overlap with the active region 125 to constitute the upper plate and the dielectric of the NMOS capacitor 120, respectively. The floating gate 116 also partially overlaps the charge injection element 122, which consists of a lightly doped N region 122A and a heavily doped N+ region 122B. The floating gate 116 is surrounded by sidewall spacers 117, and the sidewall spacers 117 are generally formed of silicon nitride or silicon oxide.

When forming the N+ or P+ regions, the sidewall isolation layer 117 prevents N+ or P+ implants from entering the lightly doped N or P regions. The charge injector 122 is connected to a word line (WL), which is also connected to the P well through a P+ contact region (not shown). During operation, when the potential of the floating gate 116 is greater than that of WL, and its voltage difference is greater than the threshold voltage of the NMOS capacitor, the P-well region 121 under the floating gate is inverted, and electrons emitted by the injector 122 form an electron in the region 121 layer, thereby forming the lower plate of the NMOS capacitor 120 . The lower plate 121 is connected to the WL through the injection member 122 .

The gate capacitance value of the NMOS capacitor 120 is larger than the gate capacitance value of the PMOS transistor 110 . According to a preferred embodiment, the gate capacitance value of the NMOS capacitor 120 is almost 2.5 times the gate capacitance value of the PMOS transistor 110 .

In the programming operation, set the potential value of BL and COM so that a large enough potential difference is formed between the two, so that a strong lateral electric field is formed from the source to the drain; set the WL potential value, so that the N-well potential and the floating gate self-NMOS capacitor The difference between the potentials coupled to is greater than the threshold of the PMOS, thereby forming the channel 113 . In the strong lateral electric field from source to drain, holes are accelerated from side to side of channel 113, resulting in impact ionization at the drain depletion region. Hot electrons generated by impact ionization are attracted by the forward biased gate and injected into the floating gate.

In the erasing operation, set WL to a negative potential value and N well to a positive potential value, and at the same time, the potential values of BL and COM are equal to that of the N well, so that the channel 113 is turned on and receives BL and COM (drain-source). The potential difference between the negative potential coupled from the NMOS capacitor to the floating gate and the channel reaches the tunneling voltage of the floating gate oxide layer, resulting in tunneling of the floating gate oxide layer, so that the floating gate electrons tunnel into the channel below.

In the readout operation after erasing, set the potential of WL to be less than the N-well, the BL potential to be less than COM, and the potential values of the N-well and COM to be greater than 0v, so that the difference between the N-well potential and the potential coupled to the floating gate self-capacitance is greater than that of the PMOS threshold, and thus the channel 113 is turned on. Under the action of the transverse electric field formed by the potential difference between BL and COM, the readout current is generated.

The specific potential values of the BL, COM, WL, and N wells set in the above programming, erasing and reading operations can be set according to the needs of the actual application. Sure.

In an erase operation, since WL is connected to the P-well, the P-well potential is equal to WL. Then, the voltage between the N well and the P well needs to be subjected to a voltage higher than the tunneling voltage. Therefore, the withstand voltage between the N-well and the P-well needs to be slightly higher than the tunneling voltage during erasing.

When the above-mentioned memory cell of the present invention and its memory are formed based on a 5V input-output device (I/O device), the thickness of the floating gate oxide layer in the memory cell is about 90-150 Å, preferably 110-130 Å, and the required thickness The erase tunneling voltage is generally about 16-18v.

FIG. 4 shows the relationship between the withstand voltage and the breakdown voltage between the P well and the N well of the memory cell shown in FIG. 1 of the present invention and the gap d between the two wells. In the memory cell shown in FIG. 1 , the dopant ion concentration in the P well and the N well is a conventional value of about 10 ¹² /cm ² .

It can be seen from the figure that the leakage current between the P well and the N well is initially 0 and does not change with the increase of the bias voltage between the two wells. Subsequently, the leakage current slightly increases as the bias voltage further increases. Then, when the voltage increases to a certain value, the leakage current increases suddenly, indicating that a breakdown occurs between the P well and the N well. The voltage value at this time is the breakdown voltage between the two wells. The voltage that can be withstood between the P-well and the N-well is the voltage below the breakdown voltage.

As can be seen from the figure, in the memory cell with the gap structure of the present invention, the withstand voltage between the P well and the N well and its breakdown voltage are significantly higher than those of the gapless structure. Moreover, the withstand voltage and its breakdown voltage between the P well and the N well initially increased significantly with the increase of the gap, and then the increase trend became slower. The two memory cell structures with a gap of 0.8µm and a gap of 1.2µm are very close in withstand voltage and breakdown voltage.

It can also be seen from FIG. 4 that the memory cell structure with a gap of 0.4µm shown in FIG. 1 of the present invention can withstand voltages above 18v, which is higher than the erasing high voltage required for memory cells formed based on 5V devices. Memory cell structures with gaps ≥ 0.4 µm can withstand voltages up to 18-22v. Appropriately reducing the concentration of doping ions in the P well and N well can make the possible withstand voltage higher than 25V.

5 shows the memory cell shown in FIG. 1 of the present invention, when the thickness of the floating gate oxide layer is 120 Å, after erasing under different erasing voltages, the difference between the reading current and the control gate potential in the reading operation I-V graph. where ■ is the curve of the gapless structural unit between the P well and N well, ● and ▲ are the memory cells with a gap d of 0.8µm between the P well and the N well after erasing at 17v and 18v erasing voltage, respectively Read the curve.

The floating gate oxide layer in the memory cell shown in Figure 5 is 120Å thick and is formed based on a 5V device, and the required erase voltage is about 18V.

As can be seen from Figure 5, the read current of the memory cell decreases as the potential value of the control gate increases, because the N-well and COM potentials are greater than 0, and the floating gate is coupled to the potential from the control gate (WL) value, increases with the increase of the control gate potential value, and the potential difference with the N-well and COM decreases.

As shown in Figure 5, the erase voltage of the gapless cell is 16v. This is because in the gapless structure, when the potential difference between the control gate (WL) and the N-well reaches 15-16v, the voltage between the N-well and the P-well has not yet reached the 18v voltage required for tunneling of the floating gate oxide layer. Breakdown occurs first (as shown by curve a in Figure 4). Then the erase voltage is clamped at 16v, and the required tunneling voltage of 18v cannot be achieved. Therefore, electrons in the floating gate cannot tunnel into the channel, and electrons that are not erased remain in the floating gate.

In the subsequent readout operation, when the control gate (WL) is driven to a potential less than the N-well, the large number of electrons remaining in the floating gate of the gapless structure makes the potential value of the floating gate self-coupling from the control gate more negative, resulting in The readout current is large. The readout current is large, indicating that the erasing effect is not good.

In a cell with a 0.8µm gap between the P-well and the N-well, the voltage between the two wells can be up to more than 20v (as shown by curve c in Figure 4), so the voltage can rise to the required level for tunneling. 18v. When the difference between the potential to which the floating gate self-capacitively couples and the potential between the channel reaches 18v, the electrons in the floating gate tunnel through the floating gate oxide layer to the channel.

In the subsequent readout operation, the control gate (WL) is driven to a potential less than the N-well, no electrons are retained in the floating gate of the cell with a gap of 0.8 µm, and the floating gate is coupled from the control gate to a potential value higher than that of the gapless structure , and the potential difference with the N-well and COM is smaller than that of the gapless structure, resulting in a small readout current. The readout current is small, indicating that the erasing effect is good.

It can also be seen from Figure 5 that for a cell with a gap of 0.8µm between the P well and the N well, when the erase voltage is set to 17v, the readout current is between the gapless cell and the erase voltage of 18v with gaps between units. This is because the set erasing voltage is not high enough, resulting in incomplete erasing and a small amount of electrons remaining in the floating gate.

The memory cells of the present invention can be arranged in multiple rows and columns to form an array and a memory. For example, multiple non-volatile cells 100 can be put together to form a memory array.

For illustrative purposes, a circuit diagram of a 2x2 memory array 250 is depicted and shown in FIG. 6 . The array contains 4 memory cells arranged in 2 rows and 2 columns. By increasing and/or decreasing the number of rows and/or columns, arrays of different sizes can be formed. The memory array 250 includes memory cells 200 , 210 , 220 and 230 . Memory array 250 also includes NMOS capacitors 201 , 211 , 221 and 231 , and PMOS transistors 202 , 212 , 222 and 232 .

In one embodiment, the WLs of memory cells 200 and 210 are connected to WLO to form one memory row, and the WLs of memory cells 220 and 230 are connected to WL1 to form another memory row. The common line (COM) and the bit line (BL) of cells 200 and 220 are connected to COM0 and BL0, respectively, forming a memory column. Similarly, the common line (COM) and bit line (BL) of cells 210 and 230 are connected to COM1 and BL1, respectively, forming another memory column. The memory array is built in a P-type substrate. The deep N wells of these memory cells are combined to form a single deep N well (DNW) (eg, deep N well 254). The N-well and the P-well of the memory cells in one memory row are merged respectively. Thus, each memory row contains one N-well (eg NW252A, NW252B) and one P-well (eg PW253A, PW253B).

Each N-well is connected to a deep N-well, which in turn is connected to a DNW. The P-well of the 'm'th memory row is connected to the word line WLm, where 'm' represents the row number. By combining wells within a row, memory cells in the array can be packed more tightly because most of the well-to-well space is eliminated. The memory array is built on the same substrate as other on-chip logic circuits, which require the substrate to be grounded or 0v.

The array and memory formed by the storage unit of the present invention have the same good performance and effect as the above-mentioned storage unit.

It is to be recognized that this specification and its drawings are to be regarded as illustrative only and not restrictive.

Claims (9)

1. A non-volatile, multi-time programmable memory, comprising: at least one memory cell constructed on a substrate, the memory cell comprising: the device comprises two adjacent traps of different types in the substrate, and an MOS transistor and an MOS capacitor which are respectively arranged in the traps of different types, wherein a gap with a distance d is arranged between the two traps; the MOS transistor comprises a floating gate and a floating gate oxide below the floating gate, the MOS capacitor comprises a gate oxide and a coupling region, and the coupling region is positioned in a well where the capacitor is positioned; wherein the gap distance d is less than or equal to 6 mu m.

2. The multi-time programmable memory of claim 1, wherein the gap distance is 0.2 μm ≦ d ≦ 2.0 μm.

3. The multiple-time programmable memory of claim 1 or 2, wherein a floating gate oxide layer thickness of the MOS transistor is 90-180 a.

4. The multiple-time programmable memory of any one of claims 1-3, wherein the floating gate of the MOS transistor extends over the capacitor in the adjacent well to form an upper plate of the capacitor.

5. The multi-time programming memory of any of claims 1-3, wherein the MOS capacitor has a capacitance value greater than a gate capacitance of the MOS transistor.

6. The multi-time programming memory of any of claims 1-3, wherein the coupling region is a heavily doped coupling region.

7. The multi-time programming memory of any of claims 1-3, wherein the substrate is a P-type substrate, and further having a deep N-well formed thereon, the two different types of wells being an N-well and a P-well, both located in the deep N-well.

8. The reprogrammable memory of any of claims 1-3, wherein the substrates of all memory cells are consolidated, said memory cells are arranged in rows and columns, the MOS transistors of all memory cells are located in consolidated wells of the same type, and the MOS capacitors of all memory cells are also located in consolidated wells of the same type.

9. The non-volatile, multi-time programmable memory of claim 8, further comprising:

a bit line connected to a drain of each MOS transistor of a column of memory cells;

a common line connected to a source of each MOS transistor of a column of memory cells; and

and the word line is connected to the heavily doped coupling region of each MOS capacitor of one row of memory cells.

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