CN114883391A - Fully-isolated N-type LDMOS device and preparation method thereof - Google Patents

Abstract

The invention discloses a fully isolated N-type LDMOS device and a preparation method thereof. The device is provided with a double-layer deep trench isolation structure (DTI) with different depths: the deep trench structure is located on the outside and is used to isolate the buried layer NBL ; The deep trench structure is located on the inner side and is used for lateral isolation of LDMOS devices to form fully isolated LDMOS devices. During the preparation process, deep trench structures with different depths of two layers are formed by a two-step etching process. Compared with the traditional fully isolated LDMOS device composed of junction isolation, under the condition of high voltage, the fully isolated LDMOS device with the double-layer DTI structure of the present invention can greatly reduce the area of the device and improve the integration under the condition of ensuring the lateral breakdown voltage. and avoid the leakage problem caused by the parasitic transistors existing in the junction isolation being turned on.

Description

A fully isolated N-type LDMOS device and preparation method thereof

technical field

The invention belongs to semiconductor technology, and relates to the field of semiconductor integrated circuit manufacturing, in particular to a fully isolated N-type LDMOS device (Fully Isolated Lateral Double-diffusion Metal Oxide Semiconductor field effect transistor, fully isolated lateral double diffused metal-oxide-semiconductor field effect transistor). ) and its preparation method.

Background technique

With the development of power integrated circuits, the BCD process has become the mainstream power device fabrication technology. LDMOS has also become the core device of the BCD process due to its advantages of strong voltage resistance, large driving current, good switching performance, and objective cost.

LDMOS devices are usually used in high-voltage applications. With the increase in demand for high voltage levels, LDMOS needs to meet high-voltage isolation between circuit systems to prevent the internal source voltage from being higher than the drain. Lateral leakage. In the traditional technology, lateral triodes are usually used to form junction isolation. This method of junction isolation often has the risk of junction breakdown. In order to avoid the problem of lateral junction breakdown, it can only be solved by increasing the area.

SUMMARY OF THE INVENTION

The purpose of the present invention is to propose a fully isolated N-type LDMOS with a double-layer deep trench (DTI) structure in view of the problems of large area and lateral isolation leakage in the existing junction-isolated fully-isolated N-type LDMOS isolation method. The device and its preparation method can increase the lateral BV while reducing the area and leakage current by changing the lateral isolation mode.

To achieve the above object, the present invention adopts the following technical solutions:

A fully isolated N-type LDMOS device is characterized in that the structure of the device is distributed laterally symmetrically at the geometric center, and specifically includes:

P-type substrate;

The P-type epitaxial layer P-EPI that is epitaxial upward along the P-type substrate;

a heavily doped N-type buried layer NBL disposed at the junction of the P-type substrate and the P-type epitaxial layer P-EPI;

A P-type region HVPW is located at the center of the top surface of the P-type epitaxial layer P-EPI, and the middle of the top surface of the P-type region HVPW is provided with a P-type epitaxial layer Substrate electrode terminal and symmetrically distributed on both sides of the electrode terminal. N-type source terminals ;

The N-type drift region N-Drift is symmetrically distributed on both sides of the P-type region HVPW;

The P-type region P-Type located at the bottom of the P-type region HVPW and the N-type drift region N-Drift;

The N-type drain terminal located on the surface of the N-Drift of the N-type drift region;

a gate arranged on the top of the P-type epitaxial layer P-EPI, a gate oxide is arranged between the gate and the P-type epitaxial layer P-EPI, and spacers are arranged on both sides of the gate;

an N-type region DNW located outside the N-type drift region N-Drift and connected to the heavily doped N-type buried layer NBL;

a deep concentration N-type region N-Well arranged on the surface of the N-type region DNW, and an N-type NBL electrode terminal arranged on the surface of the N-type region N-Well;

an inner deep trench structure arranged between the N-type region DNW and the N-type drift region N-Drift and connected to the heavily doped N-type buried layer NBL;

a deep trench structure disposed outside the N-type region DNW and the heavily doped N-type buried layer NBL and a P-region implanted at the bottom of the deep trench structure;

The P-type region P-Well located on the outside of the deep trench structure has a P-type substrate Substrate electrode end on the top of the surface of the P-type region P-Well; on the top surface of the P-type epitaxial layer P-EPI, there is a symmetrical Shallow trench isolation structure of P-type region HVPW.

The P-type substrate is intrinsic, lightly doped silicon or epitaxial silicon; the P-type region HVPW is P-type doped silicon; the P-type region P-Well is P-type doped silicon; The P-type region P-Type is silicon with a concentration higher than the P-EPI doping concentration of the P-type epitaxial layer; the P-type epitaxial layer Substrate electrode end and the P-type substrate Substrate electrode end are heavily doped silicon; The P-region is lightly doped P-type silicon;

The gate is heavily doped polysilicon or metal; the gate oxide is silicon dioxide or hafnium dioxide; the sidewall is silicon dioxide or SiO ₂ -Nitride-SiO ₂ structure; the shallow trench isolation The structure is silicon dioxide; the outer deep trench structure and the inner deep trench structure are insulating structures composed of silicon dioxide or other materials wrapped by silicon dioxide, wherein the depth of the outer deep trench structure is higher than that of the inner deep trench groove structure depth;

The N-type drift region N-Drift is an N-type doped region used as a drift region; the N-type source terminal and the N-type drain terminal are N-type heavily doped regions; the heavily doped N-type buried layer NBL is a heavily doped N-type region;

The N-type region DNW is an N-type doped region; the N-type region N-Well is an N-type doped region; the N-type NBL electrode terminal is a heavily doped N-type region, wherein the N-type regions DNW, N The type region N-Well and the N-type NBL electrode terminal together constitute the lead of the heavily doped N-type buried layer NBL, and the doping concentration is such that the N-type NBL electrode terminal is larger than the N-type region N-Well is larger than the N-type region DNW;

The P-type epitaxial layer Substrate electrode end, the P-type region HVPW and the P-type region P-Type together constitute the lead-out of the P-type epitaxial layer P-EPI inside the deep trench structure; the P-type substrate Substrate electrode end and The P-type regions P-Well together constitute the lead-out of the P-type substrate outside the deep trench structure.

The outer deep trench structure is used to isolate the heavily doped N-type buried layer NBL, the inner deep trench structure is used to isolate the N-type drift region N-Drift and the N-type region DNW of the structure shown, wherein the outer deep trench is The depth of the trench structure should be guaranteed to be greater than the final depth of the N-type buried layer NBL, and the inner deep trench structure should be guaranteed to extend into 1/5~3/5 of the final area of the N-type buried layer NBL, namely the N-type drift region N-Drift and the N-type region. The DNW is isolated in the lateral direction, while ensuring that the connection between the N-type region DNW and the heavily doped N-type buried layer NBL is not blocked by the inner deep trench structure.

In the present invention, lateral isolation is formed by the inner deep trench structure, and vertical isolation is formed by a high-concentration P-Type region, thereby forming a fully isolated N-type LDMOS device.

A preparation method of the above-mentioned fully isolated N-type LDMOS device, the method comprises the following specific steps:

The first step: prepare a semiconductor material, the semiconductor material is a P-type substrate, and the P-type substrate is a P-type semiconductor;

The second step: use the photolithography process to expose and develop the mask of the NBL layer, and leave the patterned photoresist PR on the surface as a barrier layer; use the ion implantation process to implant N-type semiconductor impurities on the surface of the P-type substrate , to remove glue;

The third step: using the epitaxial process to form a P-type epitaxial layer P-EPI on the surface of the P-type substrate, and through the thermal process accompanying the epitaxial process, the N-type impurities injected in the second step diffuse upward into the epitaxial layer and diffuse downward. into the substrate to form an N-type buried layer NBL;

Step 4: Using a photolithography process, the mask of the DNW layer is used for exposure and development, leaving a patterned photoresist PR on the surface as a barrier layer; using an ion implantation process, the surface of the P-type epitaxial layer P-EPI is implanted with N-type Semiconductor impurities, the N-type impurities are diffused to form the N-type region DNW through the push-well process; the glue is removed;

The fifth step: using an etching process to etch a shallow trench on the P-type epitaxial layer P-EPI, and fill the oxide insulating layer SiO ₂ to form a shallow trench isolation (STI) structure;

The sixth step: using a photolithography process, the mask plate of the inner deep trench layer is used for exposure and development, the formation area of the inner deep trench structure is opened, and an etching process is used to etch the inner deep trench; The inner deep trench area is filled with an insulating structure composed of silicon dioxide or other materials clad with silicon dioxide to form an inner deep trench structure;

Step 7: Using a photolithography process, the mask of the inner deep trench layer is used for exposure and development, the formation area of the outer deep trench structure is opened, and an etching process is used to etch the outer deep trench; The formed outer deep trench region adopts a thermal oxidation process to form an oxide layer on the surface of the trench, and uses an ion implantation process to implant P-type impurities to form a P-region under the outer trench; the outer depth formed by etching is deep The trench area is filled with an insulating structure composed of silicon dioxide or other materials clad with silicon dioxide to form a deep trench structure;

The eighth step: using the photolithography process, the mask of the P-type layer is used for exposure and development, and the patterned photoresist PR is left on the surface as a barrier layer, and the ion implantation process is used. Implant P-type semiconductor impurities to form a P-type region P-Type, and remove the glue;

The ninth step: using the photolithography process, the mask of the N-well layer is used for exposure and development, and the patterned photoresist PR is left on the surface as a barrier layer, and the ion implantation process is used. Implant N-type semiconductor impurities to form N-type region N-Well, and remove glue;

The tenth step: using the photolithography process, the mask of the N-Drift layer is used for exposure and development, and the patterned photoresist PR is left on the surface as a barrier layer, and the ion implantation process is used. Implant N-type semiconductor impurities to form N-type drift region N-Drift, remove glue;

The eleventh step: using the photolithography process, the mask of the P-well layer is used for exposure and development, and the patterned photoresist PR is left on the surface as a barrier layer, and the ion implantation process is used. The surface is implanted with P-type semiconductor impurities to form a P-type region P-Well, and the glue is removed;

The twelfth step: use the photolithography process to expose and develop the mask of the HVPW layer, leave the patterned photoresist PR on the surface as a barrier layer, and use the ion implantation process to implant the P-EPI surface of the P-type epitaxial layer. P-type semiconductor impurities form P-type region HVPW, and remove glue;

The thirteenth step: using the thermal oxidation furnace tube process, grow the gate oxide layer on the surface of the P-type epitaxial layer P-EPI, and the gate oxide layer is made of SiO ₂ or HfO ₂ ; using the CVD process, deposit on the gate oxide layer. Accumulate polysilicon as gate;

The fourteenth step: using CVD process, deposit an insulating layer on the surface of the P-type epitaxial layer P-EPI, the insulating layer material is SiO ₂ or SiO ₂ -Nitride-SiO ₂ , and form sidewalls on both sides of the gate through an etching process ;

The fifteenth step: using the photolithography process, the mask of the N+ layer is used for exposure and development, and the patterned photoresist PR is left on the surface as a blocking layer. N-type impurities are injected into the shallow concentration layer to form N-type source terminal, N-type drain terminal, and N-type NBL electrode terminal, and the glue is removed; the photolithography process is used to expose and develop with the mask of the P+ layer, leaving a patterned surface on the surface. The photoresist PR is used as a barrier layer, and an ion implantation process is used to implant P-type impurities in a high-concentration shallow layer on the surface of the P-type epitaxial layer P-EPI to form the P-type epitaxial layer Substrate electrode end and the P-type substrate Substrate electrode end, and remove the glue. ; Obtain a new type of fully isolated N-type LDMOS device with a double-layer DTI structure.

A novel fully isolated N-type LDMOS device with a double-layer DTI structure of the present invention, the inner deep trench structure replaces the P-Drift region used to form the lateral triode, and the outer deep trench structure is used to isolate the buried layer NBL area.

The lateral breakdown voltage of this fully isolated N-type LDMOS is related to the width of the inner deep trench to a certain extent. Compared with the LDMOS structure of the traditional junction isolation structure, it has a smaller area and a higher breakdown voltage. Under high voltage conditions, a fully isolated LDMOS device with a double-layer DTI structure can greatly reduce the area of the device under the condition of ensuring the lateral breakdown voltage, improve the integration level, and avoid the leakage problem caused by the parasitic transistors existing in the junction isolation.

Description of drawings

Fig. 1 is the structural representation of the present invention;

2 is a schematic structural diagram of a traditional fully isolated N-type LDMOS device with a junction isolation structure;

Figure 3 is a line graph showing the variation of the breakdown voltage of the junction isolation structure with the width of the P-Drift region in a traditional fully isolated N-type LDMOS device;

4 is a breakdown curve diagram of the DTI isolation structure when the width of the inner deep trench structure 6 is 1um in the present invention;

Fig. 5 is the preparation flow chart of the present invention.

Detailed ways

The specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings and examples. The following examples and accompanying drawings are used to illustrate the present invention, but are not intended to limit the scope of the present invention.

Referring to FIG. 1, the fully isolated N-type LDMOS device according to the present invention has a structure that is laterally symmetrically distributed at the geometric center of the device, including a P-type substrate 1; an epitaxial P-type epitaxial layer P extending upward along the P-type substrate 1 -EPI 2; a heavily doped N-type buried layer NBL 3 located at the junction of the P-type substrate 1 and the P-type epitaxial layer P-EPI 2; a P-type region HVPW 13 located at the top surface of the epitaxial layer P-EPI 2 , a P-type epitaxial layer Substrate electrode terminal 20 and an N-type source terminal 17 symmetrically distributed on both sides of the electrode terminal 20 are arranged on the top middle surface of the P-type region HVPW 13; Drift region N-Drift11 and P-type region P-Type 9 arranged at the bottom of P-type region HVPW 13 and N-type drift region N-Drift 11; N-type drain terminal 18 arranged on the surface of N-type drift region N-Drift 11; A gate 15 is arranged on the top of the P-type epitaxial layer P-EPI 2, a gate oxide 14 is arranged between the gate 15 and the P-type epitaxial layer P-EPI 2, and sidewalls 16 are arranged on both sides of the gate 15; An N-type region DNW4 connected to the heavily doped N-type buried layer NBL 3 outside the N-type drift region N-Drift 11 ; an N-type region N-Well 10 with a deep concentration on the surface of the N-type region DNW4, and an N-type region N-Well 10 located in the N-type region DNW4. The N-type NBL electrode terminal 19 on the surface of the N-type region N-Well 10; the inner deep trench is arranged between the N-type region DNW 4 and the N-type drift region N-Drift 11 and is connected to the heavily doped N-type buried layer NBL 3 Structure 6, a deep trench structure 8 disposed on the outside of the N-type region DNW 4 and the heavily doped N-type buried layer NBL 3 and a P-region 7 implanted at the bottom of the deep deep trench structure 8; disposed in the deep deep trench The P-type region P-Well 12 on the outside of the structure 8 is arranged on the P-type substrate Substrate electrode end 21 on the top of the surface of the P-type region P-Well 12; Shallow trench isolation structure 5 of region HVPW 13 .

The invention is a fully isolated N-type LDMOS device with a double-layer DTI structure, and the whole device is two N-type LDMOS splicing structures that are laterally symmetrical about the geometric center of the device. A heavily doped N-type buried layer NBL 3 is formed in the P-type substrate 1 , and a deep n-well DNW4 and a shallow n-well N-Well 10 are formed in the P-type substrate to serve as the heavily doped N-type buried layer NBL 3 's elicitation. The N-type drift region N-Drift 11 is mainly responsible for the withstand voltage as a drift region, and a heavily doped N-type region is formed in the N-type drift region N-Drift 11 to form the drain terminal 18 . A P-well HVPW 13 is formed in the center of the device, the HVPW 13 provides the channel region of the N-type LDMOS, the heavily-doped N-type region is formed on the P-type region HVPW13 to form the source terminal 17, and the heavily-doped P-type region is formed to form the Substrate electrode drawn from the epitaxial layer. Extreme 20.

A layer of P-Type region 9 with a higher concentration than the epitaxial layer P-EPI 2 is implanted at the lower end of the drift region N-Drift 11 and the P-well HVPW 13 to form the vertical isolation of the fully isolated N-type LDMOS, preventing the longitudinal isolation of the epitaxial layer P-EPI The low concentration of 2 causes the drift region N-Drift 11 to penetrate through the buried layer NBL 3 .

The active region on the surface of the device is isolated by a shallow trench isolation (STI) structure 5 formed of an insulating material SiO ₂ . The surface gate 15 straddles the STI structure 5, the N-type drift region N-Drift 11 and the P-type region HVPW 13, the gate 15 is made of metal material or heavily doped polysilicon, and the gate oxide 4 is made of _SiO2 or HfO ₂ . The portion of the gate 15 straddling the STI structure 5 acts as a field plate for assisting depletion.

The present invention provides a double layer deep trench isolation (DTI) structure. The inner deep trench structure 6 is located between the N-type drift region N-Drift 11 and the N-type region DNW 4, and the inner deep trench structure 6 is used for the lateral isolation of the N-type LDMOS, wherein the lateral breakdown voltage (BV) is related to the inner deep trench. The width of the trench structure 6 is related. The outer deep trench structure 8 is used to isolate the heavily doped N-type buried layer NBL 3 from the outer silicon substrate. The deep trench structure 6 and the deep deep trench structure 8 are both composed of insulating materials, which are SiO ₂ or SiO ₂ Including other materials, the outer deep trench structure 8 is deeper than the buried layer NBL 3 , and the inner deep trench structure 6 is guaranteed to extend into 1/5~3/5 of the final area of the buried layer NBL 3 . There is a lightly doped P-region 7 under the outer deep trench structure 8, and the P-region 7 can prevent the turn-on of the parasitic transistor at the bottom of the DTI.

Example

Referring to FIG. 1 , the novel fully isolated N-type LDMOS device with the double-layer deep trench (DTI) structure of the present embodiment is characterized in that the inner deep trench structure 6 and the outer deep trench structure 8 are composed of SiO ₂ insulating structure. In this embodiment, the distance between the longitudinal middle position of the heavily doped N-type buried layer NBL 3 and the surface of the epitaxial layer is about 15um, and the depth of the outer deep trench structure 8 is deeper than that of the heavily doped N-type buried layer NBL 3, and the depth is about 25um , with a width of 2um, used for the isolation of different NBLs on the same silicon wafer; the inner deep trench structure 6 is used to provide lateral isolation of fully isolated devices, isolating the drift region N-Drift 11 and the N-type region DNW 4, and it is necessary to ensure that the extension The final area of the heavily doped N-type buried layer NBL 3 is 1/5~3/5, which not only ensures the lateral isolation of the drift region N-Drift 11 and the N-type region DNW 4, but also ensures that the N-type region DNW 4 and the heavy doping The communication of the hetero-N-type buried layer NBL 3 is not blocked by the inner deep trench. In this embodiment, the inner deep trench structure 6 has a width of 1 um and a depth of about 15 um.

Referring to FIG. 2, the traditional fully isolated N-type LDMOS device adds a P-Drift region 22 to the traditional LDMOS structure, so that the N-Drift region 11, the P-Drift region 22 and the DNW4 together form a lateral NPN structure, thereby LDMOS device. horizontal isolation. Compared with the traditional fully isolated N-type LDMOS device provided with the junction isolation structure in FIG. 2, the new fully isolated N-type LDMOS device provided with the double-layer DTI structure of the present invention is characterized in that the inner deep trench structure 6 is used to perform the lateral direction of the device. Isolation can save area while ensuring the pressure resistance of the isolation structure.

Referring to FIG. 3 , in a conventional fully isolated LDMOS device with junction isolation, a simulation test is performed on the withstand voltage performance of the NPN structure used for lateral isolation. The test method is as follows: the drain terminal 18 is scanned for a voltage of 0~200V, and the P-drift electrode terminal 23 and the NBL electrode terminal 19 are connected to 0 potential. The results show that the lateral withstand voltage of the NPN structure is related to the width of the P-Drift region 22 . When the width of the P-Drift region 22 is reduced to 5um, the breakdown voltage of the lateral NPN structure formed by the N-Drift region 11 , the P-Drift region 22 and the DNW4 is reduced to 84V. Since the width of the P-Drift region is reduced, the NPN structure used for lateral isolation will have a punch-through phenomenon between the N-Drift region 11 and the DNW region 4 before the junction breakdown between the P-Drift region 22 and the N-Drift region 11 occurs. , thereby limiting the withstand voltage characteristics of the NPN structure for lateral isolation.

FIG. 4 shows the withstand voltage IV curve of the inner deep trench structure 6 used for lateral isolation when the width of the inner deep trench structure 6 is 1 um according to the present invention, that is, a novel fully isolated N-type LDMOS device with double DTI structure. The test method is: connect the NBL electrode terminal 19 to 0 potential, and scan the drain terminal 18 to a voltage of 0~200V. When the width of the inner deep trench structure 6 is 1um, the breakdown voltage of the withstand voltage structure can reach 93V. Compared with the traditional N-type fully isolated LDMOS device with junction isolation, it can meet the breakdown voltage. Save design area.

Referring to Fig. 5, in order to realize the above-mentioned device, the preparation method adopted in the present invention includes the following steps:

Step a: preparing lightly doped P-type semiconductor material, the semiconductor material being the substrate layer 1;

Step b: Using a photolithography process, the mask of the NBL layer is used for exposure and development, and a patterned PR (photoresist) is left on the surface as a barrier layer; an ion implantation process is used to implant N-type semiconductor impurities on the surface of the substrate layer 1 , to remove the glue.

Step c: Using an epitaxial process, a P-type epitaxial layer 2 (P-EPI) is formed on the surface of the P-type substrate layer 1. At the same time, through the thermal process accompanying the epitaxial process, the N-type impurities are diffused to form a buried layer 3 (NBL). This embodiment In the example, the distance between the longitudinal middle position of the NBL layer 3 and the surface of the epitaxial layer is about 15um;

Step d: using a photolithography process to expose and develop a mask of the DNW layer, leaving a patterned PR (photoresist) on the surface as a barrier layer; using an ion implantation process, the surface of the epitaxial layer 2 is implanted with N-type semiconductor impurities, The N-type impurity is diffused to form a deep n-well 4 (DNW) through the push-well process, and the glue is removed;

Step e: using an etching process to etch a shallow trench on the epitaxial layer 2 and fill the oxide insulating layer SiO ₂ to form a shallow trench isolation (STI) structure 5 ;

Step f: using an etching process, etch an inner deep trench in the epitaxial layer 2 with a depth of about 15um and a width of 1um, and fill the oxide insulating layer SiO ₂ material to form a deep trench isolation structure 6 . Using an etching process, the outer deep trench is etched on the epitaxial layer 2 and the substrate layer 1, with a depth of about 25um and a width of 2um. P-type impurities are implanted into the bottom of the outer deep trench by an ion implantation process, and the impurity concentration is 3×10 Between ¹⁵ cm ^-3 and 7×10 ¹⁵ cm ^-3 , a P-region 7 is formed, and the oxide insulating layer SiO ₂ is filled to form a deep trench isolation structure 8;

Step g: use a photolithography process to expose and develop a mask of the P-type layer, leave a patterned PR (photoresist) on the surface as a blocking layer, and use an ion implantation process to implant P-type on the surface of the epitaxial layer 2 The semiconductor impurities form P-Type region 9 and remove glue; through repeated photolithography and ion implantation processes, finally form P-type region 9, N-Well region 10, N-Drift region 11, P-Well region 12, HVPW region 13 ;

Step h: using a thermal oxidation furnace tube process, a gate oxide layer 14 is grown on the surface of the epitaxial layer 2 , and the gate oxide layer is made of SiO ₂ . Using a CVD process, polysilicon is deposited on the gate oxide layer 14 as the gate electrode 15;

Step i: using a CVD process, depositing an insulating layer on the surface of the epitaxial layer 2, the insulating layer material is SiO ₂ -Nitride-SiO ₂ , and forming sidewall structures 16 on both sides of the gate by an etching process;

Step j: Using a photolithography process, the mask of the N+ layer is used for exposure and development, and a patterned PR (photoresist) is left on the surface as a barrier layer, and an ion implantation process is used to implant a high concentration shallow layer on the surface of the epitaxial layer 2 N-type impurities are formed to form the source region 17, the drain region 18, and the NBL terminal 19, and the gate polysilicon is heavily doped, and the glue is removed; the photolithography process is used, and the mask of the P+ layer is used for exposure and development, leaving on the surface. The patterned PR (photoresist) is used as a barrier layer, and an ion implantation process is used to implant high-concentration shallow layers into the surface of the epitaxial layer 2 to implant P-type impurities to form the epitaxial layer 2 body electrode Substrate20 and the substrate layer 1 body electrode Substrate21, remove the glue , a new type of fully isolated N-type LDMOS device with double-layer DTI structure is obtained.

Claims (5)

1. The utility model provides a full isolation N type LDMOS device, characterized in that, the structure of device is with the horizontal symmetrical distribution of geometric center, specifically includes:

a P-type substrate (1);

a P-type epitaxial layer P-EPI (2) extending upwards along the P-type substrate (1);

the heavily doped N-type buried layer NBL (3) is arranged at the junction of the P-type substrate (1) and the P-EPI (2) of the P-type epitaxial layer;

the device comprises a P-type region HVPW (13) arranged at the center of the top surface of a P-type epitaxial layer P-EPI (2), wherein a P-type epitaxial layer Substrate electrode end (20) and N-type source ends (17) symmetrically distributed on two sides of the electrode end (20) are arranged in the middle of the top surface of the P-type region HVPW (13);

N-Drift regions N-Drift (11) symmetrically distributed on two sides of the P-type region HVPW (13);

a P-Type region P-Type (9) arranged at the bottom of the P-Type region HVPW (13) and the N-Type Drift region N-Drift (11);

an N-type drain terminal (18) arranged on the surface of the N-type Drift region N-Drift (11);

the grid electrode (15) is arranged on the top of the P-type epitaxial layer P-EPI (2), a grid electrode oxide (14) is arranged between the grid electrode (15) and the P-type epitaxial layer P-EPI (2), and side walls (16) are arranged on two sides of the grid electrode (15);

an N-type region DNW (4) which is arranged at the outer side of the N-type Drift region N-Drift (11) and connected with the heavily doped N-type buried layer NBL (3);

a deep concentration N-Well (10) arranged on the surface of the N-type region DNW (4), and an N-type NBL electrode terminal (19) arranged on the surface of the N-Well (10);

the inner deep groove structure (6) is arranged between the N-type region DNW (4) and the N-type Drift region N-Drift (11) and is connected with the heavily doped N-type buried layer NBL (3);

a deep trench structure (8) arranged on the outer side of the N-type region DNW (4) and the heavily doped N-type buried layer NBL (3) and a P-region (7) injected into the bottom of the deep trench structure (8);

a P-type region P-Well (12) arranged at the outer side of the deep trench structure (8), wherein a P-type Substrate electrode end (21) is arranged at the top of the surface of the P-type region P-Well (12); a shallow trench isolation structure (5) symmetrical to a P-type region HVPW (13) is arranged on the top surface of the P-type epitaxial layer P-EPI (2).

2. The fully isolated N-type LDMOS device of claim 1, wherein the P-type substrate (1) is intrinsic, lightly doped silicon or epitaxial silicon; the P-type region HVPW (13) is P-type doped silicon; the P-Well (12) is P-type doped silicon; the P-Type region P-Type (9) is silicon with doping concentration higher than that of a P-EPI (2) of a P-Type epitaxial layer; the P-type epitaxial layer Substrate electrode end (20) and the P-type Substrate electrode end (21) are heavily doped silicon; the P-region (7) is lightly doped P-type silicon;

the grid (15) is heavily doped polysilicon or metal; the gate oxide (14) is silicon dioxide or hafnium oxide; the side wall (16) is silicon dioxide or SiO ₂ -Nitride-SiO ₂ Structure; the shallow trench isolation structure (5) is silicon dioxide; the outer deep groove structure (8) and the inner deep groove structure (6) are insulation structures formed by silicon dioxide or other materials wrapped outside the silicon dioxide, wherein the depth of the outer deep groove structure (8) is higher than that of the inner deep groove structure (6);

the N-Drift region N-Drift (11) is an N-type doped region used as a Drift region; the N-type source end (17) and the N-type drain end (18) are N-type heavily doped regions; the heavily doped N-type buried layer NBL (3) is a heavily doped N-type region;

the N-type region DNW (4) is an N-type doped region; the N-Well (10) of the N-type region is an N-type doped region; the N-type NBL electrode end (19) is a heavily doped N-type region, wherein the N-type region DNW (4), the N-Well (10) and the N-type NBL electrode end (19) form the extraction of a heavily doped N-type buried layer NBL (3), and the doping concentration of the N-type NBL electrode end (19) is greater than that of the N-Well (10) of the N-type region DNW (4);

the P-Type epitaxial layer substructure electrode end (20), the P-Type region HVPW (13) and the P-Type region P-Type (9) form the extraction of a P-Type epitaxial layer P-EPI (2) at the inner side of the deep trench structure (8); the P-type Substrate electrode end (21) and the P-type region P-Well (12) form the extraction of the P-type Substrate (1) at the outer side of the deep trench structure (8).

3. The fully-isolated N-type LDMOS device of claim 1, wherein the outer deep trench structure (8) is used for isolating the heavily doped N-type buried layer NBL (3), and the inner deep trench structure (6) is used for isolating the N-Drift region N-Drift (11) and the N-type region DNW (4), wherein the depth of the outer deep trench structure (8) is greater than that of the N-type buried layer NBL (3), and the inner deep trench structure (6) is extended into the N-type buried layer NBL (3) regions 1/5-3/5, so that the N-Drift region N-Drift (11) and the N-type region DNW (4) are laterally isolated, and the communication between the N-type region DNW (4) and the N-type NBL (3) is not interrupted by the inner deep trench structure (6).

4. The fully isolated N-Type LDMOS device of claim 1, wherein a lateral isolation is formed by the inner deep trench structure (6) and a longitudinal isolation is formed by a high concentration P-Type region (9) to form a fully isolated N-Type LDMOS device.

5. The preparation method of the full-isolation N-type LDMOS device in claim 1, comprising the following specific steps:

the first step is as follows: preparing a semiconductor material, wherein the semiconductor material is a P-type substrate (1), and the P-type substrate (1) is a P-type semiconductor;

the second step is that: carrying out exposure and development by using a mask with an NBL layer by adopting a photoetching process, and leaving a patterned photoresist PR on the surface as a barrier layer; injecting N-type semiconductor impurities into the surface of the P-type substrate (1) by adopting an ion injection process, and removing the photoresist;

the third step: forming a P-type epitaxial layer P-EPI (2) on the surface of a P-type substrate (1) by adopting an epitaxial process, and simultaneously, injecting N-type impurities in the second step to upwards diffuse into the epitaxial layer and downwards diffuse into the substrate through a thermal process accompanied by the epitaxial process to form an N-type buried layer NBL (3);

the fourth step: carrying out exposure and development on a mask plate of the DNW layer by adopting a photoetching process, and leaving a patterned photoresist PR on the surface as a barrier layer; injecting N-type semiconductor impurities into the surface of a P-EPI (2) of a P-type epitaxial layer by adopting an ion injection process, and diffusing the N-type impurities by a well pushing process to form an N-type region DNW (4); removing the photoresist;

the fifth step: etching shallow trench in P-EPI (2) of P-type epitaxial layer by etching process, and filling oxide insulating layer SiO ₂ Forming a shallow trench isolation structure (5);

and a sixth step: exposing and developing the mask plate of the inner deep groove layer by adopting a photoetching process, opening a forming area of the inner deep groove structure (6), and etching the inner deep groove by adopting an etching process; filling an insulation structure formed by silicon dioxide or silicon dioxide-wrapped other materials in the etched inner deep groove region to form an inner deep groove structure (6);

the seventh step: exposing and developing the mask plate of the inner deep groove layer by adopting a photoetching process, opening a forming area of the outer deep groove structure (8), and etching the outer deep groove by adopting an etching process; forming an oxide layer on the surface of the groove by adopting a thermal oxidation process in the deep groove region with the outer depth formed by etching, and injecting P-type impurities to form a P-region below the outer groove by adopting an ion injection process; filling an insulation structure formed by silicon dioxide or silicon dioxide-wrapped other materials in the deep groove region on the outer side formed by etching to form a deep groove structure (8);

eighth step: carrying out exposure and development on a mask plate of a P-Type layer by adopting a photoetching process, leaving a patterned photoresist PR on the surface as a barrier layer, injecting P-Type semiconductor impurities on the surface of a P-Type epitaxial layer P-EPI (2) by adopting an ion injection process to form a P-Type region P-Type (9), and removing the photoresist;

the ninth step: carrying out exposure and development on a mask plate of the N-Well layer by adopting a photoetching process, leaving a patterned photoresist PR on the surface as a barrier layer, injecting N-type semiconductor impurities on the surface of a P-EPI (2) of a P-type epitaxial layer by adopting an ion injection process to form an N-Well (10) of an N-type region, and removing the photoresist;

the tenth step: carrying out exposure and development on a mask of the N-Drift layer by adopting a photoetching process, leaving a patterned photoresist PR on the surface as a barrier layer, injecting N-type semiconductor impurities on the surface of a P-EPI (2) of a P-type epitaxial layer by adopting an ion injection process to form an N-Drift region N-Drift (11), and removing the photoresist;

the eleventh step: carrying out exposure and development on a mask plate of the P-Well layer by adopting a photoetching process, leaving a patterned photoresist PR on the surface as a barrier layer, injecting P-type semiconductor impurities on the surface of a P-EPI (2) of a P-type epitaxial layer by adopting an ion injection process to form a P-Well (12) of a P-type region, and removing the photoresist;

the twelfth step: adopting a photoetching process, carrying out exposure and development on a mask plate of the HVPW layer, leaving a patterned photoresist PR on the surface as a barrier layer, adopting an ion implantation process, implanting P-type semiconductor impurities on the surface of a P-type epitaxial layer P-EPI (2) to form a P-type region HVPW (13), and removing the photoresist;

the thirteenth step: adopting a thermal oxidation furnace tube process to grow a grid oxide layer (14) on the surface of the P-EPI (2) of the P-type epitaxial layer, wherein the material of the grid oxide layer is SiO ₂ Or HfO ₂ (ii) a Depositing polysilicon over the gate oxide layer (14) as a gate (15) using a CVD process;

the fourteenth step is that: depositing an insulating layer on the surface of the P-EPI (2) of the P-type epitaxial layer by adopting a CVD (chemical vapor deposition) process, wherein the insulating layer is made of SiO (silicon oxide) ₂ Or SiO ₂ -Nitride-SiO ₂ Forming side walls (16) on two sides of the grid electrode through an etching process;

the fifteenth step: carrying out exposure and development on a mask with an N + layer by adopting a photoetching process, leaving a patterned photoresist PR on the surface as a barrier layer, injecting N-type impurities into a high-concentration shallow layer on the surface of a P-EPI (2) of a P-type epitaxial layer by adopting an ion injection process to form an N-type source end (17), an N-type drain end (18) and an N-type NBL electrode end (19), and removing the photoresist; carrying out exposure and development on a mask plate of a P + layer by adopting a photoetching process, leaving a patterned photoresist PR on the surface as a barrier layer, injecting P-type impurities into a high-concentration shallow layer on the surface of a P-EPI (2) of a P-type epitaxial layer by adopting an ion injection process to form a Substrate electrode end (20) of the P-type epitaxial layer and a Substrate electrode end (21) of the P-type Substrate, and removing the photoresist; and obtaining the fully-isolated N-type LDMOS device.

Images