CN114816254A - Hard disk data access method, device, equipment and medium - Google Patents

Abstract

The application discloses a hard disk data access method, a device, equipment and a medium, which relate to the technical field of computers, and the method comprises the following steps: acquiring a target access request sent by a central processing unit aiming at target data; judging the data type of the target data based on a preset large-capacity judgment rule and a preset small-capacity judgment rule; if the data type is large-capacity data, directly utilizing a first data transmission link between a double-rate synchronous dynamic random access memory and a central processing unit, which is established based on a first target protocol, to carry out data transmission so as to complete access operation aiming at the target data through the first data transmission link; and if the data type is small-capacity data, directly utilizing a second data transmission link between the nonvolatile memory and the central processing unit, which is established based on a second target protocol, to carry out data transmission so as to complete the access operation aiming at the target data through the second data transmission link. Therefore, the access speed of the hard disk is improved, and the time delay is reduced.

Description

A hard disk data access method, device, device and medium

technical field

The present invention relates to the field of computer technology, and in particular, to a method, device, device and medium for accessing hard disk data.

Background technique

At present, with the rapid development of electronic technology and manufacturing process, in the computer architecture, the operating frequency of CPU (central processing unit, central processing unit) and DDR (Double Data Rate, double-rate synchronous dynamic random access memory) is getting higher and higher. , the processing power is getting stronger and stronger, and although large-capacity storage media is also developing, from mechanical hard drives to SATA (Serial Advanced Technology Attachment, Serial Advanced Technology Attachment), NVME (NVMExpress, non-volatile memory host controller interface) Standard) SSD (Solid State Disk or Solid State Drive, solid state drive), but its development speed is seriously lagging behind the development speed of CPU, how to improve the read and write access speed of hard disk IO (input\output) has become the key to affecting the performance of computer systems. At present, among large-capacity storage media devices, SSD solid-state drives are gradually replacing traditional mechanical hard drives with their performance advantages. SSDs mainly include SATA2.0\SATA3.0\PCIe (Peripheral Component Interconnect Express) interface solid state drives, among which SSDs based on the NVME protocol specification have better performance and have gradually become the first choice for design. But relative to the operating frequency of CPU and DDR, it is still the main bottleneck of computer system performance.

To sum up, how to improve the access speed of the hard disk and reduce the delay is an urgent problem to be solved at present.

SUMMARY OF THE INVENTION

In view of this, the purpose of the present invention is to provide a hard disk data access method, device, device and medium, which can improve the hard disk access speed and reduce the delay. Its specific plan is as follows:

In a first aspect, the present application discloses a hard disk data access method, including:

Obtain the target access request sent by the host's central processor for the target data;

Judging the data type of the target data based on the preset large-capacity discrimination rule and the preset small-capacity discrimination rule;

If the data type of the target data is large-capacity data, the first data transmission link between the double-rate synchronous dynamic random access memory established based on the first target protocol and the central processing unit is directly used for data transmission, so as to Complete the access operation for the target data through the first data transmission link;

If the data type of the target data is small-capacity data, the second data transmission link between the non-volatile memory established based on the second target protocol and the central processing unit is directly used for data transmission, so as to The second data transmission link completes the access operation for the target data.

Optionally, if the data type of the target data is large-capacity data, the first data transmission chain between the double-rate synchronous dynamic random access memory and the central processing unit established based on the first target protocol is directly used. data transmission through the first data transmission link, so as to complete the access operation for the target data through the first data transmission link, including:

If the data type of the target data is large-capacity data, and the operation type of the access operation in the target access request is a write operation, the first data transmission link is directly used to transfer the central processing unit to the central processing unit. The sent target data is written into the double-rate synchronous dynamic random access memory;

The target data in the double-rate synchronous dynamic random access memory is written into the non-volatile memory to complete the write operation on the target data.

Optionally, if the data type of the target data is large-capacity data, the first data transmission chain between the double-rate synchronous dynamic random access memory and the central processing unit established based on the first target protocol is directly used. data transmission through the first data transmission link, so as to complete the access operation for the target data through the first data transmission link, including:

If the data type of the target data is bulk data, and the operation type of the access operation in the target access request is a read operation, the target data in the non-volatile memory is transferred to the the double-rate synchronous dynamic random access memory, so that the central processing unit directly reads the target data from the double-rate synchronous dynamic random access memory by using the first data transmission link, so as to complete the processing of the target data of the read operation.

Optionally, if the data type of the target data is small-capacity data, directly use the second data transmission link between the non-volatile memory established based on the second target protocol and the central processing unit. Data transmission, so as to complete the access operation for the target data through the second data transmission link, including:

If the data type of the target data is small-capacity data, and the operation type of the access operation in the target access request is a write operation, use the second data transmission link to directly send the central processing unit to the central processing unit. The target data is written into the non-volatile memory to complete the write operation on the target data.

Optionally, if the data type of the target data is small-capacity data, directly use the second data transmission link between the non-volatile memory established based on the second target protocol and the central processing unit. Data transmission, so as to complete the access operation for the target data through the second data transmission link, including:

If the data type of the target data is small-capacity data, and the operation type of the access operation in the target access request is a read operation, the second data transmission link is used to send the target data to the The central processing unit is used to complete the read operation of the target data.

Optionally, the sending the target data to the central processing unit by using the second data transmission link includes:

A data packet is created based on the target data in the non-volatile memory, and the data packet is sent to the central processing unit using the second data transmission link.

Optionally, the hard disk data access method further includes:

The communication between the host and the hard disk is implemented using a third target protocol.

In a second aspect, the present application discloses a hard disk data access device, comprising:

a request acquisition module, used to acquire the target access request sent by the central processing unit of the host for the target data;

The discrimination module is used for judging the data type of the target data based on the preset large-capacity discrimination rule and the preset small-capacity discrimination rule;

The first access module is configured to directly utilize the first data transmission between the double-rate synchronous dynamic random access memory and the central processing unit established based on the first target protocol if the data type of the target data is large-capacity data The link performs data transmission, so as to complete the access operation for the target data through the first data transmission link;

The second access module is configured to directly utilize the second data transmission link between the non-volatile memory established based on the second target protocol and the central processing unit if the data type of the target data is small-capacity data Data transmission is performed to complete the access operation for the target data through the second data transmission link.

In a third aspect, the present application discloses an electronic device including a processor and a memory; wherein, the processor implements the aforementioned method for accessing hard disk data when executing a computer program stored in the memory.

In a fourth aspect, the present application discloses a computer-readable storage medium for storing a computer program; wherein, when the computer program is executed by a processor, the aforementioned method for accessing hard disk data is implemented.

It can be seen that the present application obtains the target access request sent by the central processing unit of the host for the target data; judges the data type of the target data based on the preset large-capacity discrimination rule and the preset small-capacity discrimination rule; if the data type of the target data For large-capacity data, the first data transmission link between the double-rate synchronous dynamic random access memory established based on the first target protocol and the central processing unit is directly used for data transmission, so as to pass the first data transmission link. complete the access operation for the target data; if the data type of the target data is small-capacity data, directly use the second target protocol between the non-volatile memory established based on the second target protocol and the central processing unit. The data transmission link performs data transmission, so as to complete the access operation for the target data through the second data transmission link. It can be seen that, for large-capacity data, data transmission between the double-rate synchronous dynamic random access memory and the central processing unit can be performed only through the first data link in the present application, and the double-rate data transmission in the host is no longer required. Synchronous dynamic random access memory, so when data transmission of large-capacity data is performed, the data transmission speed is improved, and the delay is reduced; for small-capacity data, the application can perform non-volatile memory and The data transmission between the central processing units no longer needs to pass through the double-rate synchronous dynamic random access memory in the host and the hard disk, so when the data transmission of small-capacity data is performed, the data transmission speed is improved and the delay time is reduced; In summary, in the process of data transmission, the present application improves the data transmission speed and reduces the delay, that is, the hard disk access speed is improved, the delay is reduced, and the access to the double-rate synchronous dynamic random access memory is also reduced. time disturbance.

Description of drawings

In order to illustrate the embodiments of the present invention or the technical solutions in the prior art more clearly, the following briefly introduces the accompanying drawings that need to be used in the description of the embodiments or the prior art. Obviously, the drawings in the following description are only It is an embodiment of the present invention. For those of ordinary skill in the art, other drawings can also be obtained according to the provided drawings without creative work.

Fig. 1 is a flow chart of a hard disk data access method provided by the application;

Fig. 2 is a schematic diagram of an existing hard disk data access method;

3 is a flowchart of a specific hard disk data access method provided by the application;

4 is a flowchart of a specific hard disk data access method provided by the application;

5 is a schematic diagram of hardware components of the hard disk data access method provided by the application;

6 is a schematic diagram of the composition of the firmware part of the hard disk data access method provided by the application;

Fig. 7 is the schematic flow chart of CPU read-write large-capacity data block provided by this application;

8 is a schematic flowchart of the CPU read and write small-capacity data blocks provided by the present application;

9 is a structural diagram of a hard disk data access device provided by the application;

FIG. 10 is a structural diagram of an electronic device provided by the application.

Detailed ways

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, but not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

At present, the slow access speed of SSD solid-state drives has become the main bottleneck of computer performance. In order to overcome the above problems, the present application provides a hard disk data access solution, which can improve the hard disk access speed and reduce the delay.

Referring to FIG. 1 , an embodiment of the present application discloses a method for accessing hard disk data, which includes:

Step S11: Obtain a target access request sent by the central processing unit of the host for the target data.

In the embodiments of the present application, there are mainly two methods for accessing hard disk data in the existing methods. The first method is SSD (Solid State Drive) based on SATA interface and AHCI (Advanced Host Controller Interface, Advanced Host Controller Interface) protocol specification. At the hardware level, the computer and SATA storage device can only have one queue. Even with multiple CPUs, all requests can only go through such a narrow path. At the same time, the communication between the external controller (PCH, Platform Controller Hub) of the SATA and SAS (SerialAttached SCSI) interfaces and the CPU will also bring extra delay. In terms of software layer, each command of AHCI needs to read the register 4 times, which will Consumes 8000 CPU cycles, resulting in a latency of about 2.5 microseconds. The second method, as shown in Figure 2, is an SSD based on the PCIe interface and the NVME protocol specification. At the hardware level, the NVME SSD uses the PCIe bus for transmission, and the bandwidth is significantly improved. At the same time, the NVMe protocol can have up to 64K queues, and multiple queues are responsible for the parallel ability of flash memory. Each CPU or core can have one queue, which greatly improves the degree of concurrency and greatly improves the throughput rate; specifically, the process of CPU accessing NVME SSD As follows: The SSD is inserted into the PCIe slot of the host system in the form of a PCIe card. When the CPU accesses large-capacity data, the CPU sets the NVME queue information, notifies the SSD, and then the SSD side controller reads the queue information and controls the data management module and DMA. , transfer the data in the NAND FLASH to the RDIMM (Registered DIMM) on the HOST (host) side through DMA (Direct Memory Access, direct memory access), and generate an interrupt to notify the CPU, and then the CPU accesses the RDIMM through the CACHE (cache memory), read fetch data. The data flow process is NAND FLASH→board DDR4→DMA→CPU DDR4→CACHE. When the CPU reads and writes small-capacity or IO data, the NVME driver converts the read information into PIO (Programmed Input-Output) operations, sends TLP packets (Transaction Layer Packet, transaction layer packets), and then the SSD side Read the NAND FLASH data and send it to the CPU cache in the form of a completion packet for reading. It can be seen that the technical disadvantages of the above method are mainly: first, the total delay time when the CPU accesses the SSD storage device is large, and the access efficiency is low; The access delay is large; third, frequent CPU DMA interrupts and PCIeNVME drivers will affect performance. Therefore, the present application proposes a hard disk data access method.

In the embodiment of the present application, the CXL (Compute Express Link) protocol is used for communication between the host and the hard disk. The CXL protocol further includes the CXL.mem sub-protocol, the CXL.cache sub-protocol and the CXL.io sub-protocol. In addition, the CXL protocol includes the CXL controller (CXL engine). The third target protocol, namely the CXL.io sub-protocol, is used to implement the communication between the host and the hard disk. It should be pointed out that CXL is a new computing interconnection standard.

In the embodiment of the present application, the overall link is first constructed and initialized, and then the target access request sent by the central processing unit of the host for the target data is obtained. Specifically, the central processing unit sends the target access request, and Generate the access request packet and send it to the hard disk. After the hard disk obtains the access request packet, it parses the access request packet to obtain the target access request. The CXL controller (CXL engine) sends out the CXL.io request packet. Then use the CXL controller (CXL engine) in the SSD to receive the CXL.io request packet and parse it to obtain the target access request. The target access request includes but is not limited to data source information, data type information and read/write flag.

Step S12: Determine the data type of the target data based on the preset large-capacity discrimination rule and the preset small-capacity discrimination rule.

In the embodiment of the present application, the data type of the target data is determined based on the preset large-capacity discrimination rule and the preset small-capacity discrimination rule, and then a corresponding access operation is performed on the target data based on the data type.

Step S13: If the data type of the target data is large-capacity data, directly use the first data transmission link between the double-rate synchronous dynamic random access memory established based on the first target protocol and the central processing unit to perform data processing. transmission, so as to complete the access operation for the target data through the first data transmission link.

In the embodiment of the present application, if the data type of the target data is large-capacity data, it is determined whether the access operation is a read operation or a write operation based on the read-write flag, and then the double-rate synchronous dynamic randomization established based on the first target protocol is directly used. A first data transmission link between the memory and the central processing unit performs data transmission, so as to complete a read operation or a write operation for the target data through the first data transmission link.

It should be pointed out that the first target protocol is the CXL.mem sub-protocol. CXL.mem realizes the direct management of the MEM (memory) on the SSD by the CPU, and the MEM can also be used as a DDR (double-rate synchronous dynamic random access memory), Therefore, through the first target protocol, the CPU can directly access the double-rate synchronous dynamic random access memory on the SSD, which reduces the steps for the CPU to synchronize the dynamic random access memory through the double-rate on the host, improves the speed, and reduces the delay. It should be pointed out that the initialization of the CXL link is performed again after the read operation or the write operation is completed.

It should be pointed out that, when performing large-capacity data access operations, the first target protocol and the third target protocol, that is, the CXL.mem sub-protocol and the CXL.io sub-protocol are mainly used.

Step S14: if the data type of the target data is small-capacity data, then directly use the second data transmission link between the non-volatile memory established based on the second target protocol and the central processing unit to perform data transmission, to complete the access operation for the target data through the second data transmission link.

In the embodiment of the present application, if the data type of the target data is small-capacity data, it is determined based on the read-write flag whether the access operation is a read operation or a write operation, and then the non-volatile memory established based on the second target protocol is directly used to communicate with the A second data transmission link between the central processors performs data transmission, so as to complete a read operation or a write operation for the target data through the second data transmission link.

It should be pointed out that the second target protocol is the CXL.cache sub-protocol. CXL.cache uses the firmware part corresponding to the hard disk, that is, the FPGA (Field Programmable Gate Array), and the internal RAM is used as the CPU CACHE , which is uniformly managed by the CPU CACHE consistency management module. The CPU CACHE can be understood as a buffer of the non-volatile memory. Therefore, the communication between the non-volatile memory and the central processing unit can be directly performed through the second target protocol. It reduces the steps of the CPU through the double-rate synchronous dynamic random access memory on the host and the double-rate synchronous dynamic random access memory on the SSD, which improves the speed and reduces the delay. It should be pointed out that the initialization of the CXL link is performed again after the read operation or the write operation is completed.

It should be pointed out that, when performing large-capacity data access operations, the second target protocol and the third target protocol, that is, the CXL.cache sub-protocol and the CXL.io sub-protocol, are mainly used.

It can be seen that the present application obtains the target access request sent by the central processing unit of the host for the target data; judges the data type of the target data based on the preset large-capacity discrimination rule and the preset small-capacity discrimination rule; if the data type of the target data For large-capacity data, the first data transmission link between the double-rate synchronous dynamic random access memory established based on the first target protocol and the central processing unit is directly used for data transmission, so as to pass the first data transmission link. complete the access operation for the target data; if the data type of the target data is small-capacity data, directly use the second target protocol between the non-volatile memory established based on the second target protocol and the central processing unit. The data transmission link performs data transmission, so as to complete the access operation for the target data through the second data transmission link. It can be seen that, for large-capacity data, data transmission between the double-rate synchronous dynamic random access memory and the central processing unit can be performed only through the first data link in the present application, and the double-rate data transmission in the host is no longer required. Synchronous dynamic random access memory, so when data transmission of large-capacity data is performed, the data transmission speed is improved, and the delay is reduced; for small-capacity data, the application can perform non-volatile memory and The data transmission between the central processing units no longer needs to pass through the double-rate synchronous dynamic random access memory in the host and the hard disk, so when the data transmission of small-capacity data is performed, the data transmission speed is improved and the delay time is reduced; In summary, in the process of data transmission, the present application improves the data transmission speed and reduces the delay, that is, the hard disk access speed is improved, the delay is reduced, and the access to the double-rate synchronous dynamic random access memory is also reduced. In addition, because there is no DMA, there is no frequent interruption, which improves the access speed.

Referring to FIG. 3 , an embodiment of the present application discloses a specific hard disk data access method, which includes:

Step S21: Obtain a target access request sent by the central processing unit of the host for the target data.

For other more specific processing procedures of step S21, reference may be made to the corresponding contents disclosed in the foregoing embodiments, which will not be repeated here.

Step S22: Determine the data type of the target data based on the preset large-capacity discrimination rule and the preset small-capacity discrimination rule.

For other more specific processing procedures of step S22, reference may be made to the corresponding contents disclosed in the foregoing embodiments, which will not be repeated here.

Step S23: If the data type of the target data is large-capacity data, and the operation type of the access operation in the target access request is a write operation, directly use the first data transmission link to transfer the The target data sent by the central processing unit is written into the double-rate synchronous dynamic random access memory; the target data in the double-rate synchronous dynamic random access memory is written into the non-volatile memory, so as to The write operation to the target data is completed.

In the embodiment of the present application, if the data type of the target data is large-capacity data, it is determined based on the read-write flag whether the access operation is a read operation or a write operation, and if the operation type of the access operation in the target access request is write operation, directly use the first data transmission link to write the target data sent by the central processing unit into the double-rate synchronous dynamic random access memory; write the double-rate synchronous dynamic random access memory into the double-rate synchronous dynamic random access memory The target data is written into the non-volatile memory to complete the write operation on the target data. It should be pointed out that the CXL protocol and the CXL controller (CXL engine) are included in the read-write judgment, and the CXL controller controls the use of the CXL protocol.

In the embodiment of the present application, the process of directly using the first data transmission link to write the target data sent by the central processing unit into the double-rate synchronous dynamic random access memory specifically includes: generating an interrupt to notify The CPU sends the target data, and then the CPU writes the target data sent by the central processing unit into the double-rate synchronous dynamic random access memory through the first data transmission link, and then uses the bus arbitration management module and the buffer read-write module . Write the target data in the double-rate synchronous dynamic random access memory into the non-volatile memory through the non-volatile memory controller, and then generate an interrupt again to notify the CPU that the write operation has been completed, and then re-initialize the CXL link.

It should be pointed out that the first data transmission link is a data transmission link between the double-rate synchronous dynamic random access memory and the central processing unit established based on the first target protocol; the first target protocol is CXL.mem sub-protocol; The described interrupt is generated to notify the CPU to send the target data or to notify the CPU that the write operation has been completed, which is completed by the CXL.io sub-protocol; In this application, the double-rate synchronous dynamic random access memory is the MEM space of the SSD; The bus arbitration management module and the buffer read/write module are located in the firmware part corresponding to the hard disk, that is, the FPGA firmware, and are responsible for data transmission in the non-volatile memory; the non-volatile memory is FLASH.

Step S24: If the data type of the target data is large-capacity data, and the operation type of the access operation in the target access request is a read operation, then the target data in the non-volatile memory is stored. Transfer to the double-rate synchronous dynamic random access memory, so that the central processing unit directly reads the target data from the double-rate synchronous dynamic random access memory by using the first data transmission link, so as to complete all the the read operation of the target data.

In the embodiment of the present application, if the data type of the target data is large-capacity data, it is determined based on the read-write flag whether the access operation is a read operation or a write operation, and if the operation type of the access operation in the target access request is read operation, the target data in the non-volatile memory is transferred to the double-rate synchronous dynamic random access memory, so that the central processing unit uses the first data transfer link directly from the dual The target data is read from the double-rate synchronous dynamic random access memory, so as to complete the read operation on the target data.

In the embodiment of the present application, according to the address information of the target data in the non-volatile memory, the target data is read from the non-volatile memory and transferred to the double-rate synchronous dynamic random access memory, and then an interrupt is generated to notify the CPU to read the data , so that the CPU uses the first data transmission link to read data from the double-rate synchronous dynamic random access memory of the SSD to complete the read operation.

It should be pointed out that the step of transferring the target data from the non-volatile memory to the double-rate synchronous dynamic random access memory is completed by the bus arbitration management module and the buffer read-write module; A data transmission link between the double-rate synchronous dynamic random access memory and the central processing unit established based on the first target protocol.

Step S25: if the data type of the target data is small-capacity data, then directly use the second data transmission link between the non-volatile memory established based on the second target protocol and the central processing unit to perform data transmission, to complete the access operation for the target data through the second data transmission link.

For other more specific processing procedures of step S25, reference may be made to the corresponding content disclosed in the foregoing embodiments, which will not be repeated here.

It can be seen that the present application obtains the target access request sent by the central processing unit of the host for the target data; judges the data type of the target data based on the preset large-capacity discrimination rule and the preset small-capacity discrimination rule; if the data type of the target data is large capacity data, then directly use the first data transmission link between the double-rate synchronous dynamic random access memory established based on the first target protocol and the central processing unit to perform data transmission, so as to complete the data transmission through the first data transmission link The access operation for the target data; if the data type of the target data is small-capacity data, directly use the second data transmission between the non-volatile memory established based on the second target protocol and the central processing unit The link performs data transmission, so as to complete the access operation for the target data through the second data transmission link. It can be seen that, for large-capacity data, data transmission between the double-rate synchronous dynamic random access memory and the central processing unit can be performed only through the first data link in the present application, and the double-rate data transmission in the host is no longer required. Synchronous dynamic random access memory, so when data transmission of large-capacity data is performed, the data transmission speed is improved, and the delay is reduced; for small-capacity data, the application can perform non-volatile memory and The data transmission between the central processing units no longer needs to pass through the double-rate synchronous dynamic random access memory in the host and the hard disk, so when the data transmission of small-capacity data is performed, the data transmission speed is improved and the delay time is reduced; In summary, in the process of data transmission, the present application improves the data transmission speed and reduces the delay, that is, the hard disk access speed is improved, the delay is reduced, and the access to the double-rate synchronous dynamic random access memory is also reduced. time disturbance.

Referring to FIG. 4 , an embodiment of the present application discloses a specific hard disk data access method, which includes:

Step S31: Obtain a target access request sent by the central processing unit of the host for the target data.

For other more specific processing procedures of step S31, reference may be made to the corresponding content disclosed in the foregoing embodiments, which will not be repeated here.

Step S32: Determine the data type of the target data based on the preset large-capacity discrimination rule and the preset small-capacity discrimination rule.

For other more specific processing procedures of step S32, reference may be made to the corresponding contents disclosed in the foregoing embodiments, which will not be repeated here.

Step S33: If the data type of the target data is large-capacity data, directly use the first data transmission link between the double-rate synchronous dynamic random access memory established based on the first target protocol and the central processing unit to perform data processing. transmission, so as to complete the access operation for the target data through the first data transmission link.

Wherein, for other more specific processing procedures of step S33, reference may be made to the corresponding content disclosed in the foregoing embodiments, which will not be repeated here.

Step S34: If the data type of the target data is small-capacity data, and the operation type of the access operation in the target access request is a write operation, use the second data transmission link to directly transfer the data to the central The target data sent by the processor is written into the non-volatile memory to complete the write operation on the target data.

In the embodiment of the present application, if the data type of the target data is small-capacity data, it is determined based on the read-write flag whether the access operation is a read operation or a write operation, and if the operation type of the access operation in the target access request is write operation, then use the second data transmission link to directly write the target data sent by the central processing unit into the non-volatile memory, so as to complete the write operation to the target data .

In the embodiment of the present application, the step of directly writing the target data sent by the central processing unit into the non-volatile memory by using the second data transmission link is, specifically, obtaining the CPU-based target data Generate a data packet, parse the data packet to get the target data, and then write the target data into the buffer of the non-volatile memory, and then the bus arbitration management module and the buffer read-write module will transfer the buffer of the non-volatile memory to the buffer of the non-volatile memory. The target data in is written to the non-volatile memory. It should be pointed out that before the CPU generates a data packet, the host generates a completion packet, and uses the completion packet to notify the CPU to send data.

It should be pointed out that the process of generating a data completion packet and notifying the CPU to send data is performed by the CXL controller (CXLengine); the data packet is a CXL.cache data packet; the process of parsing the data packet is performed by the CXL controller (CXL engine).

Step S35: If the data type of the target data is small-capacity data, and the operation type of the access operation in the target access request is a read operation, use the second data transmission link to transfer the target data. Sent to the central processing unit to complete the read operation of the target data.

In the embodiment of the present application, if the data type of the target data is small-capacity data, it is determined based on the read-write flag whether the access operation is a read operation or a write operation, and if the operation type of the access operation in the target access request is read operation, then use the second data transmission link to send the target data to the central processing unit to complete the read operation of the target data, specifically, based on the data in the non-volatile memory The target data creates a data packet, and sends the data packet to the central processing unit by using the second data transmission link.

It should be noted that the target data in the non-volatile memory can be written into a buffer of the non-volatile memory, and then the target data of the buffer can be transferred to the buffer using the second data transmission link. The data is sent to the central processing unit to complete the read operation of the target data; specifically, the target data in the non-volatile memory can be written into the buffer of the non-volatile memory, and then Create a data packet based on the target data in the buffer, and send the data packet to the central processing unit by using the second data transmission link.

It should be pointed out that the step of writing the target data in the non-volatile memory into the buffer of the non-volatile memory is completed by the bus arbitration management module and the buffer read-write module; the CXL controller ( CXL engine) reads the target data from the buffer to generate a data message; the data message is a CXL.cache data message.

It can be seen that the present application obtains the target access request sent by the central processing unit of the host for the target data; judges the data type of the target data based on the preset large-capacity discrimination rule and the preset small-capacity discrimination rule; if the data type of the target data is large capacity data, then directly use the first data transmission link between the double-rate synchronous dynamic random access memory established based on the first target protocol and the central processing unit to perform data transmission, so as to complete the data transmission through the first data transmission link The access operation for the target data; if the data type of the target data is small-capacity data, directly use the second data transmission between the non-volatile memory established based on the second target protocol and the central processing unit The link performs data transmission, so as to complete the access operation for the target data through the second data transmission link. It can be seen that, for large-capacity data, data transmission between the double-rate synchronous dynamic random access memory and the central processing unit can be performed only through the first data link in the present application, and the double-rate data transmission in the host is no longer required. Synchronous dynamic random access memory, so when data transmission of large-capacity data is performed, the data transmission speed is improved, and the delay is reduced; for small-capacity data, the application can perform non-volatile memory and The data transmission between the central processing units no longer needs to pass through the double-rate synchronous dynamic random access memory in the host and the hard disk, so when the data transmission of small-capacity data is performed, the data transmission speed is improved and the delay time is reduced; In summary, in the process of data transmission, the present application improves the data transmission speed and reduces the delay, that is, the hard disk access speed is improved, the delay is reduced, and the access to the double-rate synchronous dynamic random access memory is also reduced. time disturbance.

Referring to FIG. 5 , the hardware components disclosed in this application are composed. FPGA is used as the main processing chip and supports 2 channels of DDR4. One of the routing data management modules manages metadata and FLASH block mapping, and the other is used as a cache for FLASH array data, which is jointly accessed by the data management module and the CXL protocol. The memory subsystem includes a FLASH array, a FLASH controller, a data management module and DDR4. The interface adopts the CXL protocol, which is compatible with the PCIe protocol in physical form, and the board can be directly inserted into the motherboard PCIe slot through the golden finger. It should be pointed out that the physical layer is compatible with the PCIe interface, and the PCIe slots can be reused without the need for new connectors.

Referring to FIG. 6 , the firmware disclosed in this application is composed of the firmware part. The key firmware modules in the FPGA firmware part include CXL subsystem (including CXL.io, CXL.cache, CXL.mem protocol layer, CXL Coherency Engine and CXLphy), buffer Area read/write module, bus arbitration management module, control register, status register, NAND FLASH subsystem (FLASH controller, FLASH data management module), CXL.io is used to implement IO communication between HOST and SSD, including link training, commands For functions such as sending and msi interrupt, CXL.cache uses the internal RAM of the FPGA as the CPU CACHE, which is managed by the CPU CACHE consistency management module. The CPU can access the CACHE on the SSD just like accessing the local CACHE, thereby simplifying the path for the CPU to access the SSD. Reduce access latency. CXL.mem implements the direct management of the MEM on the SSD by the CPU. The buffer read-write module and the bus arbitration management module are responsible for the transmission of FLASH data. The focus of this article is to explain how to reduce the overall CPU access time to SSD through CXL, so the storage subsystem will not be described in detail.

Referring to Figure 7, the specific process of reading and writing large-capacity data blocks for the CPU is as follows:

S40: In the initial state, the initialization of the CXL link is completed.

S41: The CPU sends an IO request, and sends a CXL.io request packet through the host-side CXL controller (CXL engine).

S42: The CXL engine on the SSD side receives the host CXL.io request packet, and the CXL.io sub-protocol parses the packet to obtain the relevant information of the IO request, such as the read/write flag, data source, size and other information.

S43: CXL engine performs read and write interpretation based on the information parsed by CXL.io. If it is a write operation, jump to the state S44, if it is a read operation, jump to the state S47.

S44: Generate a CXL interrupt through CXL.io to notify the CPU that data can be sent.

S45: The CXL on the CPU side directly writes data to the MEM space of the SSD through the CXL.mem protocol.

S46: The bus arbitration management module cooperates with the buffer read/write module to write the data in the MEM space into the FLASH through the FLASH controller, and then send an interrupt to the CPU to realize the SSD write operation. Return to the initial state S40.

S47: When it is determined that the IO is a read request, read the data from the FLASH according to the address information.

S48: The bus arbitration management module cooperates with the buffer read/write module to move the data to the MEM space of the SSD.

S49: Notify the CPU to read the data, and the CPU reads the MEM space data of the SSD through the CXL.mem protocol on the HOST side to complete the read operation.

Referring to Figure 8, the specific process of reading and writing small-capacity data blocks for the CPU is as follows:

S50: Initial state, complete the CXL initialization, wait for the CPU command, and control the CPU to send an IO request, and send a CXL.io packet request through the host-side CXL controller.

S51: The CXL engine on the SSD side receives the CXL.io request packet from the host, and the CXL engine parses the CXL.io packet based on the CXL.io sub-protocol to determine whether the CPU is a read operation or a write operation. If it is a read operation, jump to S55 to change state, if it is a write operation, jump to S52 to change state.

S52: The CXL engine sends a CXL.io completion packet to notify the CPU to send data.

S53: The CPU sends the CXL.cache data packet, CXL.Engine parses the data packet, and writes the data into the FLASH buffer

S54: Write data into FLASH through the bus arbitration management module and the read-write buffer module.

S55: CPU read operation, the bus arbitration management module and the read-write buffer module read the FLASH data and write the buffer.

S56: The CXL engine reads the buffer data, generates a CXL.cache data packet and sends it to the CPU.

S57: The CPU side receives the CXL.cash data packet and completes the read operation.

To sum up, this application proposes a new type of SSD solid-state drive based on the CXL protocol from the perspective of reducing the overall link delay of CPU-CACHE-DDR-SSD, which implements CXL.io, CXL.cache, CXL. The CXL.mem sub-protocol uses the internal high-speed RAM or REG of the FPGA as the SSD cache cache, and the CPU can directly access the Cache on the SSD solid state drive, thereby improving the IO storage speed. Reduce transmission delay. Mainly, in view of the relatively large delay of the current CPU accessing SSD through DMA or IO, a new protocol CXL is implemented to further improve the IO performance of CPU accessing SSD and reduce the access delay. At the same time, this solution can also reduce The additional perturbation introduced by the CPU accessing the local DDR provides overall computer system performance. Specifically, first, for large-capacity data transmission, through the CXL.mem sub-protocol, the MEM on the FPGA side is used as the MEM of the CPU on the HOST side to form a FLASH-local DDR-CXL.mem data path to avoid FLASH data on the local DDR and HOST sides. Propagation delay between DDRs. The second is small-capacity data transmission. Through the CXL.cache sub-protocol, the FLASH data can be read and written directly, bypassing the local DDR operation. At the same time, the CXL.IO protocol packet is simplified compared to the PCIe IO packet, which further reduces the delay. Third, CPU-CXL-local DDR-FLASH forms a complete data path, without the participation of RDIMM on the HOST side, which avoids the disturbance of RDIMM access, where the HOST is the host.

Referring to FIG. 9, an embodiment of the present application discloses a hard disk data access device, including:

The request acquisition module 11 is used to acquire the target access request sent by the central processing unit of the host for the target data;

The discrimination module 12 is used for judging the data type of the target data based on the preset large-capacity discrimination rule and the preset small-capacity discrimination rule;

The first access module 13 is configured to directly utilize the first data between the double-rate synchronous dynamic random access memory and the central processing unit established based on the first target protocol if the data type of the target data is large-capacity data The transmission link performs data transmission, so as to complete the access operation for the target data through the first data transmission link;

The second access module 14 is configured to directly utilize the second data transmission chain between the non-volatile memory established based on the second target protocol and the central processing unit if the data type of the target data is small-capacity data data transmission through the second data transmission link, so as to complete the access operation for the target data through the second data transmission link.

For more specific working processes of the above-mentioned modules, reference may be made to the corresponding contents disclosed in the foregoing embodiments, which will not be repeated here.

It can be seen that the present application obtains the target access request sent by the central processing unit of the host for the target data; judges the data type of the target data based on the preset large-capacity discrimination rule and the preset small-capacity discrimination rule; if the data type of the target data For large-capacity data, the first data transmission link between the double-rate synchronous dynamic random access memory established based on the first target protocol and the central processing unit is directly used for data transmission, so as to pass the first data transmission link. complete the access operation for the target data; if the data type of the target data is small-capacity data, directly use the second target protocol between the non-volatile memory established based on the second target protocol and the central processing unit. The data transmission link performs data transmission, so as to complete the access operation for the target data through the second data transmission link. It can be seen that, for large-capacity data, data transmission between the double-rate synchronous dynamic random access memory and the central processing unit can be performed only through the first data link in the present application, and the double-rate data transmission in the host is no longer required. Synchronous dynamic random access memory, so when data transmission of large-capacity data is performed, the data transmission speed is improved, and the delay is reduced; for small-capacity data, the application can perform non-volatile memory and The data transmission between the central processing units no longer needs to pass through the double-rate synchronous dynamic random access memory in the host and the hard disk, so when the data transmission of small-capacity data is performed, the data transmission speed is improved and the delay time is reduced; In summary, in the process of data transmission, the present application improves the data transmission speed and reduces the delay, that is, the hard disk access speed is improved, the delay is reduced, and the access to the double-rate synchronous dynamic random access memory is also reduced. time disturbance.

Further, an embodiment of the present application also provides an electronic device. FIG. 10 is a structural diagram of an electronic device 20 according to an exemplary embodiment, and the content in the figure should not be considered as any limitation on the scope of use of the present application.

FIG. 10 is a schematic structural diagram of an electronic device 20 according to an embodiment of the present application. The electronic device 20 may specifically include: at least one processor 21 , at least one memory 22 , a power supply 23 , an input and output interface 24 , a communication interface 25 and a communication bus 26 . The memory 22 is used for storing a computer program, and the computer program is loaded and executed by the processor 21 to implement the relevant steps of the hard disk data access method disclosed in any of the foregoing embodiments.

In this embodiment, the power supply 23 is used to provide working voltage for each hardware device on the electronic device 20; the communication interface 25 can create a data transmission channel between the electronic device 20 and external devices, and the communication protocol it follows is applicable Any communication protocol in the technical solution of the present application is not specifically limited here; the input and output interface 24 is used to obtain external input data or output data to the outside world, and its specific interface type can be selected according to specific application needs, here No specific limitation is made.

In addition, as a carrier for resource storage, the memory 22 can be a read-only memory, a random access memory, a magnetic disk or an optical disk, etc. The memory 22 can include a random access memory as a running memory and a non-volatile non-volatile memory used for storage purposes of external memory The memory, the storage resources on it include the operating system 221, the computer program 222, etc., and the storage mode can be short-term storage or permanent storage.

The operating system 221 is used to manage and control various hardware devices and computer programs 222 on the electronic device 20 on the source host, and the operating system 221 may be Windows, Unix, Linux, or the like. In addition to the computer program that can be used to complete the hard disk data access method performed by the electronic device 20 disclosed in any of the foregoing embodiments, the computer program 222 may further include a computer program that can be used to complete other specific tasks.

In this embodiment, the input/output interface 24 may specifically include, but is not limited to, a USB interface, a hard disk reading interface, a serial interface, a voice input interface, a fingerprint input interface, and the like.

Further, an embodiment of the present application further discloses a computer-readable storage medium for storing a computer program; wherein, when the computer program is executed by a processor, the aforementioned method for accessing hard disk data is implemented.

For the specific steps of the method, reference may be made to the corresponding content disclosed in the foregoing embodiments, which will not be repeated here.

The computer-readable storage medium mentioned here includes random access memory (Random Access Memory, RAM), memory, read-only memory (Read-Only Memory, ROM), electrically programmable ROM, electrically erasable programmable ROM, registers , hard disk, magnetic disk or optical disk or any other form of storage medium known in the art. Wherein, when the computer program is executed by the processor, the aforementioned hard disk data access method is implemented. For the specific steps of the method, reference may be made to the corresponding content disclosed in the foregoing embodiments, which will not be repeated here.

The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments, and the same or similar parts between the various embodiments may be referred to each other. For the device disclosed in the embodiment, since it corresponds to the hard disk data access method disclosed in the embodiment, the description is relatively simple, and the relevant part can be referred to the description of the method.

Professionals may further realize that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two, in order to clearly illustrate the possibilities of hardware and software. Interchangeability, the above description has generally described the components and steps of each example in terms of functionality. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Skilled artisans may implement the described functionality using different methods for each particular application, but such implementations should not be considered beyond the scope of this application.

The steps of an algorithm described in connection with the embodiments disclosed herein may be implemented directly in hardware, a software module executed by a processor, or a combination of the two. A software module can be placed in random access memory (RAM), internal memory, read only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, removable disk, CD-ROM, or any other in the art. in any other known form of storage medium.

Finally, it should also be noted that in this document, relational terms such as first and second are used only to distinguish one entity or operation from another, and do not necessarily require or imply these entities or there is any such actual relationship or sequence between operations. Moreover, the terms "comprising", "comprising" or any other variation thereof are intended to encompass a non-exclusive inclusion such that a process, method, article or device comprising a list of elements includes not only those elements, but also includes not explicitly listed or other elements inherent to such a process, method, article or apparatus. Without further limitation, an element qualified by the phrase "comprising a..." does not preclude the presence of additional identical elements in a process, method, article or apparatus that includes the element.

A method, device, device and medium for accessing hard disk data provided by the present invention have been described in detail above. Specific examples are used in this paper to illustrate the principles and implementations of the present invention. The descriptions of the above embodiments are only used to help Understand the method of the present invention and its core idea; at the same time, for those skilled in the art, according to the idea of the present invention, there will be changes in the specific implementation and application scope. In summary, the content of this specification does not It should be understood as a limitation of the present invention.

Claims (10)

1. A hard disk data access method is characterized by comprising the following steps:

acquiring a target access request sent by a central processing unit of a host aiming at target data;

judging the data type of the target data based on a preset large-capacity judgment rule and a preset small-capacity judgment rule;

if the data type of the target data is high-capacity data, directly utilizing a first data transmission link between a double-rate synchronous dynamic random access memory and the central processing unit, which is established based on a first target protocol, to carry out data transmission so as to complete access operation aiming at the target data through the first data transmission link;

and if the data type of the target data is small-capacity data, directly utilizing a second data transmission link between the nonvolatile memory and the central processing unit, which is established based on a second target protocol, to perform data transmission so as to complete the access operation aiming at the target data through the second data transmission link.

2. The method according to claim 1, wherein if the data type of the target data is large-capacity data, the data is directly transmitted by using a first data transmission link between a double-data-rate synchronous dynamic random access memory (ddr sdram) established based on a first target protocol and the central processing unit, so as to complete the access operation for the target data through the first data transmission link, including:

if the data type of the target data is high-capacity data and the operation type of the access operation in the target access request is a write operation, directly utilizing the first data transmission link to write the target data sent by the central processing unit into the double-rate synchronous dynamic random access memory;

writing the target data in the double-rate synchronous dynamic random access memory into the nonvolatile memory to complete the write operation of the target data.

3. The method according to claim 1, wherein if the data type of the target data is large-capacity data, the data is directly transmitted by using a first data transmission link between a double-data-rate synchronous dynamic random access memory (ddr sdram) established based on a first target protocol and the central processing unit, so as to complete the access operation for the target data through the first data transmission link, including:

if the data type of the target data is large-capacity data and the operation type of the access operation in the target access request is a read operation, transmitting the target data in the nonvolatile memory to the double-rate synchronous dynamic random access memory, so that the central processing unit directly reads the target data from the double-rate synchronous dynamic random access memory by using the first data transmission link to complete the read operation on the target data.

4. The hard disk data access method according to claim 1, wherein if the data type of the target data is small-capacity data, directly performing data transmission by using a second data transmission link between the nonvolatile memory and the central processor, which is established based on a second target protocol, to complete an access operation for the target data through the second data transmission link, the method includes:

if the data type of the target data is small-capacity data and the operation type of the access operation in the target access request is a write operation, directly writing the target data sent by the central processing unit into the nonvolatile memory by using the second data transmission link to complete the write operation on the target data.

5. The hard disk data access method according to claim 1, wherein if the data type of the target data is small-capacity data, directly performing data transmission by using a second data transmission link between the nonvolatile memory and the central processor, which is established based on a second target protocol, to complete an access operation for the target data through the second data transmission link, the method includes:

and if the data type of the target data is small-capacity data and the operation type of the access operation in the target access request is a read operation, sending the target data to the central processing unit by using the second data transmission link so as to complete the read operation of the target data.

6. The hard disk data access method of claim 5, wherein the sending the target data to the central processor using the second data transmission link comprises:

creating a data packet based on the target data in the non-volatile memory and sending the data packet to the central processor using the second data transmission link.

7. The hard disk data access method according to any one of claims 1 to 6, further comprising:

and realizing the communication between the host and the hard disk by utilizing a third target protocol.

8. A hard disk data access device, comprising:

the request acquisition module is used for acquiring a target access request sent by a central processing unit of the host aiming at target data;

the judging module is used for judging the data type of the target data based on a preset large-capacity judging rule and a preset small-capacity judging rule;

the first access module is used for directly utilizing a first data transmission link between a double-rate synchronous dynamic random access memory and the central processing unit which is established based on a first target protocol to carry out data transmission if the data type of the target data is high-capacity data, so as to complete the access operation aiming at the target data through the first data transmission link;

and the second access module is used for directly utilizing a second data transmission link between the nonvolatile memory and the central processing unit which is established based on a second target protocol to carry out data transmission if the data type of the target data is the small-capacity data, so as to complete the access operation aiming at the target data through the second data transmission link.

9. An electronic device comprising a processor and a memory; wherein the processor, when executing the computer program stored in the memory, implements the hard disk data access method of any of claims 1 to 7.

10. A computer-readable storage medium for storing a computer program; wherein the computer program when executed by a processor implements a hard disk data access method as claimed in any one of claims 1 to 7.

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