CN114695082A - Processing method for generating oxide layer after conductive layer is exposed - Google Patents

Abstract

The invention provides a processing method for generating an oxide layer after a conductive layer is exposed, a rework method of an MIM capacitor, a memory and a forming method thereof. Cleaning by using a solution containing HF to remove an oxide layer generated after the conductive layer is exposed, and ensuring that the conductive layer can be normally etched without being influenced by the oxide layer in a treatment method for generating the oxide layer after the conductive layer is exposed; in the rework method of the MIM capacitor, the first conductive layer can be normally etched to form a first electrode; in the memory and the forming method thereof, the second conducting layer can be normally etched to form the second electrode and the control grid lead layers which are distributed at intervals, so that the control grid lead layers which are distributed at intervals are not bridged, the failure rate of a read-write program of the memory is reduced, and the yield of the memory is improved.

Description

Processing method for generating oxide layer after conductive layer is exposed

technical field

The invention belongs to the technical field of integrated circuit manufacturing, and in particular relates to a processing method for generating an oxide layer after a conductive layer is exposed, a method for forming a MIM capacitor, a memory and a method for forming the same.

Background technique

A metal-insulator-metal (MIM: Metal-insulator-Metal) structure, as an integrated capacitor, can be used to store charges in various semiconductor devices, and it is widely used in radio frequency integrated circuits and analog/mixed-signal integrated circuits. MIM capacitors are formed laterally on a semiconductor wafer with two metal plates sandwiching a dielectric layer.

During the fabrication of the MIM capacitor, the process of exposing the conductive layer (usually a metal layer and serving as the electrode of the MIM capacitor) affects the fabrication quality of the subsequent conductive layer. In the memory including the MIM capacitor, the conductive layer is used as the lead layer of the memory, and the exposed conductive layer is easily oxidized, resulting in a high failure rate of the memory read and write procedures.

SUMMARY OF THE INVENTION

The purpose of the present invention is to provide a processing method for generating an oxide layer after the conductive layer is exposed, a rework method for an MIM capacitor, a memory and a method for forming the same. It is ensured that the conductive layer can be etched normally and is not affected by the oxide layer; the fabrication quality of the conductive layer is improved; the failure rate of the reading and writing procedures of the memory is reduced, and the yield rate of the memory is improved.

The present invention provides a processing method for generating an oxide layer after the conductive layer is exposed, comprising:

providing a substrate on which a conductive layer and a cover layer covering the conductive layer are formed;

Use an etching or ashing process to remove part or all of the cover layer to expose part or all of the conductive layer;

The exposed surface of the conductive layer is oxidized to form an oxide layer;

The oxide layer is removed by washing with an HF-containing solution.

Further, the HF-containing solution includes a mixed solution of H ₂ SO ₄ , HF and H ₂ O.

Further, in the solution containing HF, the volume ratio of H ₂ SO ₄ , HF and H ₂ O ranges from 0.5 to 2:0.5 to 2.5:9 to 13, and the concentration of HF ranges from 500ppm to 800ppm.

Further, the material of the conductive layer includes at least one of titanium nitride, titanium, aluminum, copper, copper alloy, aluminum alloy, or copper aluminum alloy.

Further, the material of the cover layer includes at least one of silicon nitride, silicon oxide, silicon oxynitride, a high dielectric constant dielectric material and a photoresist.

The present invention also provides a rework method for a metal-insulator-metal (MIM) capacitor, comprising:

providing a substrate on which a first conductive layer, a first insulating layer and a second conductive layer are formed from top to bottom, and a photoresist layer is formed on the first conductive layer;

An abnormality occurs in the photolithography process, and the photoresist layer is removed by rework with an ashing process to expose the first conductive layer;

The exposed surface of the first conductive layer is oxidized in the ashing process to form an oxide layer;

The oxide layer is removed by using the above-mentioned processing method of generating an oxide layer after exposing the conductive layer.

Further, after removing the oxide layer, the method further includes:

etching the first conductive layer to form a first electrode, and the first electrode exposes part of the first insulating layer;

forming a second insulating layer covering the upper surface and sidewall of the first electrode and the exposed surface of the first insulating layer;

The second insulating layer and the first insulating layer are etched, and the second insulating layer remaining on the surface of the sidewall of the first electrode and the first insulating layer below it form a sidewall, which is located below the first electrode The first insulating layer constitutes a dielectric layer; the etching exposes the upper surface of the first electrode and the second conductive layer on the side of the sidewall spacer away from the first electrode;

The second conductive layer is etched to form a second electrode.

The present invention also provides a method for forming a memory, comprising:

A substrate is provided on which a storage layer is formed, the storage layer includes a common word line, a first floating gate and a first control gate located on one side of the common word line, and a the other side-shaped second floating gate and second control gate;

A MIM capacitor is formed, and the MIM capacitor is electrically connected to the storage layer; the MIM capacitor includes from top to bottom: a first electrode, a dielectric layer and a second conductive layer, and the sides of the first electrode and the dielectric layer are A spacer is formed on the wall; in the process of forming the spacer, the exposed upper surface of the first electrode and/or the exposed upper surface of the second conductive layer is oxidized to form an oxide layer;

The oxide layer is removed by using the above-mentioned processing method of generating an oxide layer after exposing the conductive layer.

The second conductive layer is etched to form a second electrode and control gate lead layers distributed at intervals, and the control gate lead layers distributed at intervals are respectively electrically connected to the first control gate and the second control gate.

The present invention also provides a memory, comprising:

a substrate on which a storage layer is formed, the storage layer including a common word line, a first floating gate and a first control gate located on one side of the common word line, and another one located on the common word line side-shaped second floating gate and second control gate;

MIM capacitor, the MIM capacitor is electrically connected to the storage layer; the MIM capacitor includes from top to bottom: a first electrode, a dielectric layer and a second electrode, the first electrode and the sidewall of the dielectric layer are formed have side walls;

Control gate wiring layers distributed at intervals, the control gate wiring layers distributed at intervals are located in the same layer and of the same material as the second electrode; the control gate wiring layers distributed at intervals are respectively the same as the first control gate and the second electrode. The second control gate is electrically connected.

Further, an interlayer interconnection structure layer is provided between the storage layer and the MIM capacitor, and the spaced control gate lead layers are respectively connected with the interlayer interconnection structure layer through the interconnection layer located in the interlayer interconnection structure layer. The first control gate and the second control gate are electrically connected.

Compared with the prior art, the present invention has the following beneficial effects:

The invention provides a processing method for generating an oxide layer after the conductive layer is exposed, a rework method for an MIM capacitor, a memory and a method for forming the same. In the processing method for generating an oxide layer after the conductive layer is exposed, a solution containing HF is used to clean and remove the oxide layer generated after the conductive layer is exposed, so as to ensure that the conductive layer can be etched normally and is not affected by the oxide layer.

In the rework method of the MIM capacitor, a solution containing HF is used to clean and remove the oxide layer generated by the ashing process of the conductive layer (the first conductive layer), so that the first conductive layer can be etched (etched through) normally to form the first conductive layer. electrode.

In the memory and the method for forming the same, after etching to form the sidewall, the oxide layer is removed by cleaning with a solution containing HF. The second conductive layer can be normally etched (etched through) to form the second electrode and the control gate wiring layer distributed at intervals, so that no bridge occurs between the control gate wiring layers distributed at intervals, and the corresponding first control gate of the memory There is no short circuit with the second control gate, and the read and write procedures can be independently applied to the first control gate and the second control gate respectively, the failure rate of the read and write procedures is reduced, and the yield of the memory is improved.

Description of drawings

FIG. 1 is a schematic flowchart of a processing method for generating an oxide layer after exposing a conductive layer according to an embodiment of the present invention.

2 to 9a are schematic diagrams of steps of a method for forming a memory according to an embodiment of the present invention.

9a is a schematic diagram illustrating successful etching of the second conductive layer using the method for forming a memory according to an embodiment of the present invention;

FIG. 9b is a schematic diagram illustrating the failure of etching of the second conductive layer due to the formation of an oxide layer after the conductive layer in the memory is exposed;

FIG. 9c is a schematic diagram of bridging (adhesion) occurring corresponding to the etching failure of the second conductive layer in FIG. 9b.

FIG. 10 is a schematic diagram of a memory according to an embodiment of the present invention.

FIG. 11a is a test diagram of forming a memory by removing the oxide layer formed after the conductive layer is exposed by using the improved method for forming a memory of this embodiment.

FIG. 11b is a test diagram of an untreated memory formed by an oxide layer formed after the conductive layer in the memory before improvement is exposed.

FIG. 12 to FIG. 14 are schematic diagrams of steps of a rework method for an MIM capacitor according to an embodiment of the present invention.

Among them, the reference numerals are as follows:

100-substrate; 110-second conductive layer; 1101-conductive layer one; 1102-conductive layer two; 1103-conductive layer three; 111-second electrode; 112-control gate lead layer; 120-first insulating layer; 121 - Dielectric layer; 130 - first conductive layer; 131 - first electrode; 140 - second insulating layer; 150 - spacer; 16 - oxide layer; 170 - third insulating layer; 180 - photoresist layer; 190 - oxide Floor.

200-gate oxide layer; 210-first floating gate; 220-first control gate; 310-second floating gate; 320-second control gate; 410-shared word line.

Detailed ways

The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the accompanying drawings are in a very simplified form and use inaccurate scales, and are only used to facilitate and clearly assist the purpose of explaining the embodiments of the present invention.

For the convenience of description, some embodiments of the present application may use spatially relative terms such as "above", "below", "top", "below", etc., to describe an element as shown in the drawings of the embodiments or the relationship of a component to another (or other) elements or components. It should be understood that spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "below" or "beneath" other elements or features would then be oriented "above" or "over" the other elements or features. The terms "first," "second," etc. hereinafter are used to distinguish between similar elements, and are not necessarily used to describe a particular order or temporal order. It is to be understood that these terms so used may be substituted under appropriate circumstances.

An embodiment of the present invention provides a processing method for generating an oxide layer after the conductive layer is exposed, as shown in FIG. 1 , including:

Step S11, providing a substrate on which a conductive layer and a cover layer covering the conductive layer are formed;

Step S12, using an etching or ashing process to remove part or all of the cover layer to expose part or all of the conductive layer;

Step S13, the exposed surface of the conductive layer is oxidized to form an oxide layer;

Step S14, using a solution containing HF to remove the oxide layer.

Specifically, the HF-containing solution includes a mixed solution of H ₂ SO ₄ , HF and H ₂ O. Exemplarily, in the HF-containing solution, the volume ratio of H ₂ SO ₄ , HF and H ₂ O ranges from 0.5 to 2:0.5 to 2.5:9 to 13, and the concentration of HF ranges from 500ppm to 800ppm. The preferred volume ratio of H ₂ SO ₄ , HF and H ₂ O is 1:1.33:11, and the concentration of HF is 500ppm-800ppm. Exemplarily, the HF-containing solution is formed by mixing H ₂ SO ₄ , HF and H ₂ O, such as 0.5X-2X H ₂ SO ₄ , 0.5X-2.5X HF, 9X-13X H ₂ O mixed with three, where X is a volume unit, such as L, mL, etc.

The material of the conductive layer includes at least one of titanium nitride, titanium, aluminum, copper, copper alloy, aluminum alloy or copper aluminum alloy. The material of the cover layer includes: at least one of silicon nitride, silicon oxide, silicon oxynitride, high dielectric constant dielectric material and photoresist.

An embodiment of the present invention also provides a method for forming a memory, including:

Step S21, providing a substrate on which a storage layer is formed, the storage layer including a common word line, a first floating gate and a first control gate located on one side of the common word line, and a first floating gate and a first control gate located on one side of the common word line, a second floating gate and a second control gate formed on the other side of the word line;

Step S22, forming a MIM capacitor, the MIM capacitor is electrically connected to the storage layer; the MIM capacitor includes from top to bottom: a first electrode, a dielectric layer and a second conductive layer, the first electrode and the dielectric A spacer is formed on the sidewall of the layer; in the process of forming the spacer, the exposed upper surface of the first electrode and/or the exposed upper surface of the second conductive layer is oxidized to form an oxide layer ;

Step S23, removing the oxide layer by using the above-mentioned processing method for generating an oxide layer after the conductive layer is exposed;

Step S24, etching the second conductive layer to form a second electrode and a control gate lead layer distributed at intervals, and the control gate lead layer distributed at intervals is electrically connected to the first control gate and the second control gate respectively. connect.

Specifically, as shown in FIGS. 9 a to 10 , in step S21 , a substrate 100 is provided, and a storage layer T is formed on the substrate 100 , and the storage layer T includes a gate oxide layer 200 located on the substrate 100 and located in the gate oxide layer. The common word line 410 above the layer 200 , the first floating gate 210 and the first control gate 220 on one side of the common word line 410 , and the second floating gate on the other side of the common word line 410 310 and a second control gate 320.

Step S22 , forming the MIM capacitor. The steps of forming the MIM capacitor are described in detail below with reference to FIGS. 2 to 8 . Figures 2 to 8 focus on MIM capacitors, and the storage layer T is not shown.

Referring to FIG. 2 , a substrate 100 is provided, and the substrate 100 has a first conductive layer 130 , a first insulating layer 120 and a second conductive layer 110 thereon in order from top to bottom.

In this embodiment, the substrate 100 is a silicon wafer. Various semiconductor device units and connection structures and isolation structures therebetween may be formed in the substrate 100 , for example, the semiconductor device units may be metal oxide semiconductor field effect transistors (MOSFETs), bipolar junction transistors (BJTs) ), high-voltage transistors, high-frequency transistors, diodes, optical devices, MEMS (Micro-electro mechanical System) devices or other components. In other embodiments, the substrate 100 may also be other semiconductor materials or insulating materials. For example, the substrate 100 can also be made of silicon germanium, germanium, or III-V semiconductor materials, or the like, or a multi-layer structure material such as Si-SiGe, Si-SiC, silicon-on-insulator (SOI), or germanium-on-insulator (GOI). ; or insulating materials such as glass.

The second conductive layer 110 , the first insulating layer 120 and the first conductive layer 130 can be sequentially formed on the surface of the substrate 100 through a deposition process from bottom to top, and are respectively used to form MIM capacitors in subsequent processes. the second electrode, the dielectric layer and the first electrode. The structures of the first conductive layer 130 and the second conductive layer 110 may be single-layer or multi-layer, and the material may be metal or other conductive materials, such as titanium nitride, titanium, aluminum, copper, copper alloy, At least one of aluminum alloy or copper aluminum alloy. The structure of the first insulating layer 120 may also be a single layer or multiple layers, and the material may be at least one of silicon nitride, silicon oxide, silicon oxynitride or a high dielectric constant dielectric material.

In this embodiment, the material of the first conductive layer 130 is, for example, titanium nitride; the material of the first insulating layer 120 is, for example, silicon nitride; the second conductive layer 110 includes conductive layers in sequence from bottom to top The first 1101, the second conductive layer 1102 and the third conductive layer 1103; the first conductive layer 1101 includes a titanium nitride (TiN) layer and/or a titanium (Ti) layer, the second conductive layer 1102 is, for example, an aluminum layer, and the third conductive layer 1103 also includes nitrogen Titanium (TiN) layer and/or titanium (Ti) layer.

Next, as shown in FIG. 2 and FIG. 3 , the first conductive layer 130 is etched to form a first electrode 131 , and the first electrode 131 exposes a part of the first insulating layer 120 .

Specifically, a mask layer (not shown) may be formed on the first conductive layer 130 first, and the mask layer is formed with a pattern corresponding to the shape of the first electrode 131 to be formed through a photolithography process. The mask layer can be a photoresist layer or a hard mask layer; then the first conductive layer 130 is etched according to the pattern on the mask layer until the surface of the first insulating layer 120 is exposed, and then removed. The material of the first conductive layer outside the first electrode to be formed forms the first electrode; and finally the mask layer is removed. In this embodiment, the etching gas used in the etching process has a high selectivity ratio to titanium nitride and silicon nitride, so that the etching process can be stopped on the surface of the first insulating layer 120 .

In this embodiment, after the first conductive layer 130 is etched to form the first electrode 131 , the substrate 100 and the first electrode 131 and the first insulating layer 120 thereon are also cleaned. After the etch process, organic polymers and sputtering residues are often formed that negatively affect the resistivity, leakage current, and yield of the resulting device. The cleaning process is used to remove the organic polymer and sputtering residues. The solution used in the cleaning process can be selected according to specific processes and materials, which is not limited in the present invention.

In some other embodiments, after the first conductive layer 130 is etched to form the first electrode 131, the first insulating layer 120 exposed by the first electrode 131 may be etched continuously to remove part of the first electrode 131. insulating layer 120 . Continue to etch the first insulating layer 120 to reduce the thickness of the first insulating layer 120 exposed by the first electrode 131, so that the first conductive layer material outside the first electrode 131 can be removed cleanly, and the The difficulty of etching the first insulating layer 120 in subsequent processes can be reduced.

Next, as shown in FIG. 4 , a second insulating layer 140 covering the upper surface and sidewalls of the first electrode 131 and part of the upper surface of the first insulating layer 120 is formed.

Specifically, the second insulating layer 140 may be formed by chemical vapor deposition, physical vapor deposition or atomic layer deposition process. The material of the second insulating layer 140 is one or more of silicon nitride, silicon oxynitride or silicon oxide. In this embodiment, the materials of the second insulating layer 140 and the first insulating layer 120 are the same, and both are silicon nitride. The thickness of the second insulating layer 140 is related to the width of the spacer to be formed. In this embodiment, in order to enable the sidewall spacers to sufficiently protect the dielectric layer, the thickness of the second insulating layer 140 is, for example, 100 angstroms to 2000 angstroms. Since the second insulating layer 140 and the first insulating layer 120 need to be etched to form spacers in the subsequent process, the second insulating layer 140 and the first insulating layer 120 are made of the same material. Reducing the difficulty of etching, on the other hand, can also enhance the bonding strength between the two.

Next, as shown in FIG. 4 and FIG. 5 , the second insulating layer 140 and the first insulating layer 120 are etched, leaving the second insulating layer 1502 on the sidewall surface of the first electrode 131 and the lower part thereof. The first insulating layer 1501 constitutes the sidewall spacer 150, and the first insulating layer under the first electrode 131 constitutes the dielectric layer 121; the etching exposes the upper surface of the first electrode 131 and the sidewall spacer 150 away from all the second conductive layer 110 on the side of the first electrode 131 .

Specifically, after the second insulating layer 140 is formed, the sidewall etching is performed without a mask, and the etching process adopts plasma etching, which has good directionality; The thickness of the second insulating layer material on the wall is larger in the vertical direction. When the upper surface of the first electrode 131 and the second insulating layer material on the first insulating layer 120 are removed, the sidewall of the first electrode 131 is removed. Part of the material of the second insulating layer on the upper part is retained; with the progress of the etching process, the first insulating layer 120 outside the area covered by the first electrode 131 continues to be removed by etching, which is located under the first electrode 131 and all the The first insulating layer under the second insulating material layer remains on the sidewall surface of the first electrode 131; after the etching process is completed, the second insulating layer 1502 remaining on the sidewall surface of the first electrode 131, The sidewall 150 is formed together with the first insulating layer 1501 under the second insulating layer 1502 on the sidewall surface of the first electrode 131 . The etching gas used in the above etching process has a relatively high selectivity ratio to silicon nitride and titanium nitride, so that the etching process can be stopped on the surface of the second conductive layer 110 . It should also be noted that, in the above description, “down” and “below” refer to a direction perpendicular to the first electrode 131 and facing the substrate 100 .

In the implementation of the present invention, the spacer 150 is formed by etching the second insulating layer 140 and the first insulating layer 120 . The spacer 150 can protect the dielectric layer 121 under the first electrode 131 and reduce the amount of the dielectric The plasma damage to the layer 121 during the etching process improves the capacitance and Time Dependent Dielectric Breakdown (TDDB: Time Dependent Dielectric Breakdown) characteristics of the finally formed MIM. Moreover, since the dielectric layer 121 is protected by the spacers 150, the thickness of the dielectric layer 121 can be made smaller, which increases the capacitance value of the MIM capacitor finally formed.

Next, as shown in FIG. 6 and FIG. 7 , in the etching process of forming the spacer 150 , the upper surface of the first electrode 131 and the side of the spacer 150 away from the first electrode 131 are exposed. the upper surface of the second conductive layer 110 . The exposed upper surface of the first electrode 131 and the exposed upper surface of the second conductive layer 110 are oxidized to form an oxide layer 160 . The oxide layer 160 is formed by natural oxidation in an etching atmosphere, which is not desirable. The oxide layer 160 is an oxidation product of the second conductive layer 110 , for example, including at least one of titanium oxide, aluminum oxide, or copper oxide.

Step S23 , as shown in FIG. 6 and FIG. 7 , in this embodiment, after the sidewall spacers 150 are formed by etching, a solution containing HF is used to remove the oxide layer 160 . The HF-containing solution includes a mixed solution of H ₂ SO ₄ , HF and H ₂ O. Specifically, in the HF-containing solution, the volume ratio of H ₂ SO ₄ , HF and H ₂ O ranges from 0.5 to ₂ : 0.5 to 2.5: 9 to 13 _. The volume ratio of H ₂ O is in the range of 1:1.33:11, and the concentration of HF is 500ppm-800ppm. Exemplarily, the HF-containing solution is formed by mixing H ₂ SO ₄ , HF and H ₂ O, such as 0.5X-2X H ₂ SO ₄ , 0.5X-2.5X HF, 9X-13X H ₂ O mixed with three, where X is a volume unit, such as L, mL, etc. In this embodiment, the substrate 100 and the first electrode 131 , the sidewall spacer 150 , the second conductive layer 110 , etc. on the substrate 100 are also cleaned, so as to remove organic polymers and sputtering residues during the etching process. In this embodiment, a solution containing HF is used to clean and remove the oxide layer formed after the conductive layer (the first electrode 131 and/or the second conductive layer 110) is exposed, so that the second conductive layer 110 can be etched (etched through) normally, thereby increasing the The window of the subsequent etching process of the second conductive layer 110 is enlarged, and the fabrication quality of the second conductive layer 110 is improved. It solves the problem that the oxide layer generated on the surface cannot be removed by conventional EKC cleaning solution (including a mixed solution of hydroxylamine, alcohols, catechol and polar solvents).

Next, as shown in FIG. 8 , a third insulating layer 170 is deposited, and the third insulating layer 170 covers the first electrode 131 , the spacer 150 and a part of the second conductive layer 110 . The material of the third insulating layer 170 is one or more of silicon nitride, silicon oxynitride or silicon oxide. In this embodiment, the material of the third insulating layer 170 is silicon oxynitride. The third insulating layer 170 can protect the first electrode 131 and the dielectric layer 121 in the subsequent etching process of the second conductive layer 110; in addition, since the second conductive layer 110 is usually a metal , the reflection of light is relatively strong, and the third insulating layer 170 can also be used as a dark layer in the photolithography process to reduce light reflection.

Step S24, etching the second conductive layer; FIG. 9a is a schematic diagram of the successful etching of the second conductive layer using the method for forming a memory according to an embodiment of the present invention; FIG. 9b is an oxide layer generated after the conductive layer in the memory is exposed. Figure 9c is a schematic diagram of bridging (adhesion) corresponding to the failure of etching the second conductive layer in Figure 9b. FIG. 10 is a schematic diagram of a memory according to an embodiment of the present invention. As shown in FIG. 9a to FIG. 10 , the second conductive layer is etched to form second electrodes 111 and control gate wiring layers 112 distributed at intervals, and the control gate wiring layers distributed at intervals are respectively connected to the first control gate 220 and the second control gate 320 are electrically connected.

Specifically, as shown in FIG. 8 , FIG. 9 a and FIG. 10 , a patterned mask layer (not shown) is formed on the third insulating layer 170 , and the patterned mask layer may be bottom-to-bottom A stack of DARC (Bottom Anti-Reflection Coating) layers and photoresist layers on top. The third insulating layer 170 and the second conductive layer 110 are etched along the openings in the patterned mask layer until the surface of the substrate 100 is exposed, that is, the second conductive layer 110 is etched The second electrode 111 and the control gate lead layer 112 distributed at intervals are formed, and the second electrode 111 is used as the lower electrode of the MIM capacitor; the control gate lead layer 112 distributed at intervals is respectively connected with the first control gate 220 and the The second control gate 320 is electrically connected; for example, the control gate wiring layer 112 a is electrically connected to the first control gate 220 , and the control gate wiring layer 112 b is electrically connected to the second control gate 320 .

The shape and size of the second electrode 111 are designed according to specific applications, which are not limited in the present invention. As shown in FIG. 9 a , the size of the second electrode 111 may be larger than that of the first electrode 131 . In this embodiment, after the second conductive layer 110 is etched, the substrate 100 and the first electrode 131 , the spacer structure 150 and the second electrode 111 on the substrate 100 are also cleaned to remove organic polymers and sputtering. shoot residue.

FIG. 9b is a schematic diagram illustrating the failure of etching of the second conductive layer due to the formation of an oxide layer after the conductive layer in the memory is exposed. As shown in FIG. 9b, studies have found that if the exposed upper surface of the first electrode 131 and/or the exposed upper surface of the second conductive layer is not treated with the oxide layer 160 generated, the oxide layer 160 will not be treated. Existing, increases the thickness of the layer to be etched in the memory, resulting in instability of the etching process. For example, the etching parameters set according to the normal process cannot etch the second conductive layer (including conductive layer 1 1101, conductive layer 2 1102 and conductive layer 3 1103) to the bottom (etch through), and the second conductive layer in region IV is etched not to the bottom (cut through), resulting in bridging (adhesion) between the spaced control gate wiring layers 112 (for example, at a), for example, the adjacent control gate wiring layers 112a and the control gate wiring layer 112b are bridged (adhesion), Eventually, the first control gate 220 and the second control gate 320 of the memory are short-circuited.

FIG. 9a is a schematic diagram illustrating that the second conductive layer is successfully etched by the method for forming a memory according to an embodiment of the present invention; as shown in FIG. 9a, in the method for forming a memory according to an embodiment of the present invention, the sidewall 150 is formed by etching in this embodiment. Afterwards, the oxide layer 160 is removed by cleaning with a solution containing HF. So that the second conductive layer 110 can be etched (etched through) normally, the second electrode 111 and the control gate lead layers 112 distributed at intervals are formed, and no bridging (adhesion) occurs between the control gate lead layers 112 distributed at intervals, and the corresponding , the first control gate 220 and the second control gate 320 of the memory will not be short-circuited, and can independently apply voltages to the first control gate 220 and the second control gate 320 to perform read and write procedures, and the read and write procedures fail. The rate is reduced, and the yield of the memory is improved.

FIG. 11a is a test diagram of the improved memory using the method for forming a memory of this embodiment, and an oxide layer is formed after the conductive layer is removed and exposed; FIG. The dots in the wafers in Figures 11a and 11b indicate that the chip read and write procedures failed at that location; Figure 11b shows that there are many points where the chip read and write procedures fail in the memory before the improvement, and the chip read and write procedures have a high probability of failure, and concentrated distribution. Compared with FIG. 11b , in FIG. 11 a , the points where the chip read and write program failures occur in the memory after the improvement are significantly reduced, and the points are in a random distribution state. 11a and FIG. 11b are compared, further confirming that the method for forming a memory according to an embodiment of the present invention improves the yield of the memory.

An embodiment of the present invention further provides a memory, as shown in FIG. 9a and FIG. 10 , including:

A substrate 100, on which a storage layer T is formed, the storage layer T includes a common word line 410, a first floating gate 210 and a first control gate 220 on one side of the common word line 410, and a first control gate 220 on one side of the common word line 410. a second floating gate 310 and a second control gate 320 formed on the other side of the common word line 410;

MIM capacitor, the MIM capacitor is electrically connected to the storage layer; the MIM capacitor includes from top to bottom: a first electrode 131 , a dielectric layer 121 and a second electrode 111 , the first electrode 131 and the dielectric layer The side walls of 121 are formed with side walls 150;

Control gate lead layers 112 distributed at intervals, the control gate lead layers 112 distributed at intervals and the second electrodes 111 are located in the same layer and of the same material; the control gate lead layers distributed at intervals are respectively the same as the first control gate 220 and the second control gate 320 are electrically connected. The control gate wiring layers 112 distributed at intervals may be distributed in array stripes.

An interlayer interconnection structure layer may also be provided between the storage layer T and the MIM capacitor, and the interlayer interconnection structure layer may be provided with a through-silicon hole or a contact hole, and an interconnection is formed in the through-silicon hole or the contact hole. The interconnection layer is made of at least one of copper, tungsten or aluminum. The control gate wiring layers 112 distributed at intervals are electrically connected to the first control gate 220 and the second control gate 320 through the interconnection layers located in the interlayer interconnection structure layer, respectively.

The present invention also provides a rework method for a metal-insulator-metal (MIM) capacitor, comprising:

As shown in FIG. 12 , a substrate 100 is provided, and a first conductive layer 130 , a first insulating layer 120 and a second conductive layer 110 are formed on the substrate 100 from top to bottom, and a light source is formed on the first conductive layer 130 resistance layer 180;

As shown in FIG. 13 , an abnormality occurs in the photolithography process, and an ashing process is used to rework to remove the photoresist layer to expose the first conductive layer 130 ; the exposed surface of the first conductive layer 130 is in the ashing process. After the process, it is oxidized to form an oxide layer 190;

As shown in FIG. 14 , the oxide layer 190 is removed by using the above-mentioned processing method of generating an oxide layer after exposing the conductive layer.

The study found that the photoresist layer 180 was formed on the surface of the first conductive layer 130, and there was an abnormality in the lithography, such as unqualified critical dimensions formed by lithography, particle defects or misalignment of the exposure pattern, etc., which led to the need to rework to remove the original light. barrier layer 180 . The surface of the first conductive layer 130 exposed after removing the photoresist layer 180 is easily oxidized to form an oxide layer 190 after the ashing process. If the oxide layer 190 is not treated, the subsequent etching process of the MIM capacitor will be affected. Specifically, the photoresist layer is reworked to form a photoresist layer on the surface of the oxide layer 190. The oxide layer 190 is an excess layer from natural oxidation, which is not within the design range. In the subsequent process of etching the first conductive layer 130 to form the first electrode 131, Due to the influence of the oxide layer 190 due to the predetermined etching parameters, the first conductive layer 130 cannot be etched to the predetermined depth, or the etching to the predetermined depth actually takes longer than the designed time, thereby affecting the normal fabrication of the MIM capacitor. The oxide layer 190 formed after ashing is removed by cleaning with a solution containing HF, which ensures the normal and stable etching process of the subsequent MIM capacitor.

After removing the oxide layer, the method further includes:

etching the first conductive layer to form a first electrode, and the first electrode exposes part of the first insulating layer;

forming a second insulating layer covering the upper surface and sidewall of the first electrode and the exposed surface of the first insulating layer;

The second insulating layer and the first insulating layer are etched, and the second insulating layer remaining on the surface of the sidewall of the first electrode and the first insulating layer below it form a sidewall, which is located below the first electrode The first insulating layer constitutes a dielectric layer; the etching exposes the upper surface of the first electrode and the second conductive layer on the side of the sidewall spacer away from the first electrode;

The second conductive layer is etched to form a second electrode.

After the oxide layer is removed, the subsequent fabrication method of the MIM capacitor is the same as the method for forming the MIM capacitor in the above step S22, and will not be described again.

To sum up, the present invention provides a processing method for generating an oxide layer after the conductive layer is exposed, a reworking method for an MIM capacitor, a memory and a method for forming the same. In the processing method for generating an oxide layer after the conductive layer is exposed, a solution containing HF is used to clean and remove the oxide layer generated after the conductive layer is exposed, so as to ensure that the conductive layer can be etched normally and is not affected by the oxide layer.

In the rework method of the MIM capacitor, a solution containing HF is used to clean and remove the oxide layer generated after the conductive layer (the first conductive layer) is exposed, so that the first conductive layer can be etched normally according to the preset process parameters to form the first electrode. .

In the memory and the method for forming the same, after etching to form the sidewall, the oxide layer is removed by cleaning with a solution containing HF. The second conductive layer can be etched (etched through) normally to form the second electrode and the control gate wiring layers distributed at intervals, and no bridging occurs between the control gate wiring layers distributed at intervals, and the corresponding first control gate and The second control gate is not short-circuited, and the read and write procedures can be independently applied to the first control gate and the second control gate respectively, the failure rate of the read and write procedures is reduced, and the yield of the memory is improved.

The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments, and the same and similar parts between the various embodiments can be referred to each other. As for the method disclosed in the embodiment, since it corresponds to the device disclosed in the embodiment, the description is relatively simple, and the relevant part can be referred to the description of the method.

The above description is only a description of the preferred embodiments of the present invention, and does not limit the scope of the rights of the present invention. Any person skilled in the art can use the methods and technical contents disclosed above to improve the present invention without departing from the spirit and scope of the present invention. The technical solutions are subject to possible changes and modifications. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments according to the technical essence of the present invention without departing from the content of the technical solutions of the present invention belong to the technical solutions of the present invention. protected range.

Claims (10)

1. A processing method for generating an oxide layer after a conductive layer is exposed is characterized by comprising the following steps:

providing a substrate, wherein a conductive layer and a covering layer covering the conductive layer are formed on the substrate;

removing part or all of the covering layer by adopting an etching or ashing process so as to expose part or all of the conducting layer;

oxidizing the exposed surface of the conductive layer to generate an oxide layer;

and cleaning by using a solution containing HF to remove the oxide layer.

2. The method of claim 1 wherein the HF-containing solution comprises H₂SO₄HF and H₂And (3) mixed solution of O.

3. The method according to claim 2, wherein H is H in the HF-containing solution₂SO₄HF and H₂The volume ratio of the oxygen to the nitrogen is 0.5-2: 0.5-2.5: 9-13, and the concentration of the HF is 500-800 ppm.

4. The method of claim 1, wherein the conductive layer comprises at least one of titanium nitride, titanium, aluminum, copper alloy, aluminum alloy, or copper aluminum alloy.

5. The method of claim 1, wherein the capping layer comprises a material selected from the group consisting of: at least one of silicon nitride, silicon oxide, silicon oxynitride, high-k dielectric material, and photoresist.

6. A method of reworking a metal-insulator-metal (MIM) capacitor, comprising:

providing a substrate, wherein a first conducting layer, a first insulating layer and a second conducting layer are formed on the substrate from top to bottom, and a photoresist layer is formed on the first conducting layer;

removing the photoresist layer by adopting an ashing process when the photoetching process is abnormal, and exposing the first conducting layer;

the exposed surface of the first conductive layer is oxidized in the ashing process to generate an oxide layer;

removing the oxide layer using the method of any one of claims 1 to 5.

7. The method of rework of a metal-insulator-metal (MIM) capacitor of claim 6, further comprising, after removing the oxide layer:

etching the first conducting layer to form a first electrode, wherein a part of the first insulating layer is exposed out of the first electrode;

forming a second insulating layer covering the upper surface and the side wall of the first electrode and the exposed surface of the first insulating layer;

etching the second insulating layer and the first insulating layer, wherein the second insulating layer remained on the surface of the side wall of the first electrode and the first insulating layer below the second insulating layer form a side wall, and the first insulating layer below the first electrode forms a dielectric layer; the second conducting layer on the upper surface of the first electrode and on one side, far away from the first electrode, of the side wall is exposed through etching;

and etching the second conductive layer to form a second electrode.

8. A method for forming a memory, comprising:

providing a substrate, wherein a storage layer is formed on the substrate, the storage layer comprises a common word line, a first floating gate and a first control gate which are positioned on one side of the common word line, and a second floating gate and a second control gate which are positioned on the other side of the common word line;

forming an MIM capacitor electrically connected with the storage layer; the MIM capacitor comprises the following components from top to bottom: the dielectric layer is formed on the first electrode, and a side wall is formed on the side wall of the dielectric layer; in the process of forming the side wall, the exposed upper surface of the first electrode and/or the exposed upper surface of the second conducting layer are oxidized to generate an oxide layer;

removing the oxide layer by the method of any one of claims 1 to 5;

and etching the second conducting layer to form a second electrode and control gate lead layers distributed at intervals, wherein the control gate lead layers distributed at intervals are electrically connected with the first control gate and the second control gate respectively.

9. A memory, comprising:

the memory device comprises a substrate, wherein a memory layer is formed on the substrate and comprises a common word line, a first floating gate and a first control gate which are positioned on one side of the common word line, and a second floating gate and a second control gate which are positioned on the other side of the common word line;

a MIM capacitor electrically connected with the storage layer; the MIM capacitor comprises the following components from top to bottom: the dielectric layer is arranged on the first electrode, and a side wall is formed on the side wall of the dielectric layer;

the control gate lead layers are distributed at intervals, and the control gate lead layers and the second electrodes are positioned on the same layer and are made of the same material; the control gate lead layers distributed at intervals are electrically connected with the first control gate and the second control gate respectively.

10. The memory of claim 9,

an interlayer interconnection structure layer is arranged between the storage layer and the MIM capacitor, and the control gate lead layers distributed at intervals are electrically connected with the first control gate and the second control gate respectively through interconnection layers in the interlayer interconnection structure layer.

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