CN114625202B - Reference voltage generating circuit and method - Google Patents
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- CN114625202B CN114625202B CN202011450867.9A CN202011450867A CN114625202B CN 114625202 B CN114625202 B CN 114625202B CN 202011450867 A CN202011450867 A CN 202011450867A CN 114625202 B CN114625202 B CN 114625202B
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/625—Regulating voltage or current wherein it is irrelevant whether the variable actually regulated is AC or DC
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Abstract
The invention discloses a reference voltage generating circuit and a generating method thereof, wherein the circuit comprises: a counter for generating a plurality of count clocks based on an initial clock signal; and the digital-to-analog converter is used for carrying out digital-to-analog conversion on count values characterized by the plurality of counting clocks based on the first reference voltage and the second reference voltage to generate reference voltages, wherein the voltage value of at least one of the first reference voltage and the second reference voltage is adjustable in different counting periods of the counter. The reference voltage generating circuit and the generating method thereof can generate reference voltage with any slope and realize any adjustment of the change direction (including positive change or negative change) of the reference voltage.
Description
Technical Field
The present invention relates to the field of integrated circuits, and in particular, to a reference voltage generating circuit and a method for generating the same.
Background
In the circuit application field, there is a need for reference voltage supply, and a common solution is shown in fig. 1a, fig. 1a shows a schematic circuit structure of a conventional reference voltage generating circuit, and a reference voltage Vref is obtained at an intermediate node between a current source i and a capacitor C by connecting the current source i and the capacitor C in series between a power source terminal VDD and a reference ground.
However, as shown in fig. 1b, fig. 1b shows a schematic diagram of the reference voltage of fig. 1a with time, and the reference voltage Vref generated by the circuit is linear with time, which cannot meet the application requirement of different slopes. Meanwhile, based on the circuit structure, if the reference voltage Vref is to be utilized for a long period of time, the current provided by the current source i is required to be particularly small, or the capacitance value of the capacitor C is particularly large, which is not easy to realize.
Accordingly, there is a need to provide an improved solution to overcome the above technical problems in the prior art.
Disclosure of Invention
In order to solve the technical problems, the invention provides a reference voltage generating circuit and a reference voltage generating method, which can generate reference voltage with any slope and realize any adjustment of the change direction (including positive change or negative change) of the reference voltage.
According to a first aspect, the present invention provides a reference voltage generating circuit, comprising: a counter for generating a plurality of count clocks based on an initial clock signal;
A digital-to-analog converter connected with the counter and receiving a first reference voltage and a second reference voltage for performing digital-to-analog conversion on count values characterized by the plurality of count clocks based on the first reference voltage and the second reference voltage to generate a reference voltage,
Wherein, in different counting periods of the counter, the voltage value of at least one of the first reference voltage and the second reference voltage is adjustable.
Optionally, the digital-to-analog converter includes:
the first branch circuit comprises a plurality of second resistors and a plurality of first resistors which are connected in series between a first reference voltage input end and a reference voltage output end;
A plurality of second branches, each second branch comprising:
the first input end of the selection switch is connected with the first reference voltage input end, and the second input end of the selection switch is connected with the second reference voltage input end;
a plurality of second resistors connected between the first branch and the output end of the selection switch,
The plurality of selection switches on the plurality of second branches correspondingly receive the plurality of counting clocks, and a first resistor is arranged between any two adjacent second branches and the connection node of the first branch.
Optionally, each second branch includes a second resistor, and a resistance value of each second resistor is twice that of the first resistor.
Optionally, each second branch circuit includes two second resistors connected in series, and a resistance value of each second resistor is equal to a resistance value of the first resistor.
Optionally, in any two counting periods of the counter, a magnitude relation between the first reference voltage and the second reference voltage is unchanged, and a difference value between the first reference voltage and the second reference voltage is different.
Optionally, in any two counting periods of the counter, the magnitude relation between the first reference voltages is different.
Optionally, the voltage value of the first reference voltage in the second counting period of the counter is equal to the voltage value of the second reference voltage in the first counting period of the counter,
The first counting period and the second counting period are adjacent, and the reference voltage is stepped from the first reference voltage to the second reference voltage in the first counting period and the second counting period.
In a second aspect, the present invention provides a method for generating a reference voltage, including: generating a plurality of count clocks based on the initial clock signal;
Performing digital-to-analog conversion on count values characterized by the plurality of count clocks based on the first reference voltage and the second reference voltage to generate reference voltages,
Wherein, in different counting periods of the counter, the voltage value of at least one of the first reference voltage and the second reference voltage is adjustable.
The beneficial effects of the invention are as follows: the present disclosure relates to a reference voltage generating circuit and a method thereof, which uses a counter and a digital-to-analog converter to generate a reference voltage with an arbitrary slope. In the process of generating the reference voltage, as the voltage value of at least one of the first reference voltage and the second reference voltage received by the digital-to-analog converter is adjustable in different counting periods (the period duration of each counting period is equal) of the counter, the change amplitude of the reference voltage in the same time can be changed by adjusting at least one of the first reference voltage and the second reference voltage, and the purpose of adjusting the generation slope of the reference voltage is achieved. And in adjusting at least one of the first reference voltage and the second reference voltage, reference voltages having different slopes can be generated based on the first reference voltage and the second reference voltage having different differences (including different magnitudes of the differences, and/or different positive and negative differences). Therefore, the reference voltage with any slope can be generated in different counting periods of the counter, and any adjustment of the change direction (including positive change or negative change) of the reference voltage is realized.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention as claimed.
Drawings
The above and other objects, features and advantages of the present invention will become more apparent from the following description of embodiments of the present invention with reference to the accompanying drawings.
FIG. 1a is a schematic diagram showing a circuit configuration of a conventional reference voltage generating circuit;
FIG. 1b is a graph showing the reference voltage of FIG. 1a as a function of time;
fig. 2 illustrates a schematic diagram of a reference voltage generation circuit provided according to an embodiment of the present disclosure;
FIG. 3 shows a schematic diagram of the internal circuit structure of the digital-to-analog converter of FIG. 2;
FIG. 4 is a graph showing reference voltage versus time provided in accordance with an embodiment of the present disclosure;
Fig. 5 shows a flow chart diagram of a method of generating a reference voltage provided in accordance with an embodiment of the present disclosure.
Detailed Description
In order that the invention may be readily understood, a more complete description of the invention will be rendered by reference to the appended drawings. Preferred embodiments of the present invention are shown in the drawings. The invention may, however, be embodied in different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention.
The present invention will be described in detail with reference to the accompanying drawings.
Fig. 2 illustrates a schematic diagram of a reference voltage generation circuit provided according to an embodiment of the present disclosure.
As shown in fig. 2, in the embodiment of the present disclosure, a reference voltage generating circuit includes: a counter 100 and a digital to analog converter 200.
Wherein the counter 100 is used for generating a plurality of count clocks based on an initial clock signal CLK.
In this embodiment, the input end of the counter 100 receives an initial clock signal CLK, and the counter 100 generates a plurality of count clocks based on a clock period corresponding to the initial clock signal CLK, and further counts according to different level states of the plurality of count clocks.
Herein, for example, the counter 100 may output 9 count clocks, the plurality of count clocks (denoted as D <0:8 >) may include: the first count clock D <0>, the second count clock D <1>, the third count clock D <2>, the fourth count clock D <3>, the fifth count clock D <4>, the sixth count clock D <5>, the seventh count clock D <6>, the eighth count clock D <7> and the ninth count clock D <8>. Thus, 512 groups of control signals in 111111111 ～ 000000000 can be output and the reference voltage Vref can be realized in one counting periodIs a variation in accuracy. Further, if the clock period T (CLK) =2us of the initial clock signal CLK is assumed, one counting period (denoted as T) of the counter 100 is t=512×t (CLK)/2=512 us.
It should be understood that the number of output ends of the counter 100, that is, the number of counting clocks generated by the counter is proportional to the step precision of the reference voltage Vref along with time, that is, if the precision requirement of the corresponding reference voltage Vref is high, the counter 100 with a larger number of output ends can be selected to meet the requirement of high precision; if the accuracy requirement corresponding to the reference voltage Vref is low, the counter 100 with a relatively small number of output terminals can be selected to save circuit area and cost. And correspondingly, the counter with more output ends can be directly selected, and the number of the output ends in the actually effective access circuit is selected according to the requirement only when circuit connection is carried out. The present disclosure does not specifically limit this, and in practice, the selection may be performed according to different application scenarios.
It should be noted that one counting period of the counter 100 may be equal to the minimum adjustment period when the slope of the reference voltage Vref is adjusted. And herein, for convenience of understanding, one count period of the counter 100 will be set as an adjustment period when the slope of the reference voltage Vref is adjusted.
The digital-to-analog converter 200 is connected to the output terminal of the counter 100 and receives the first reference voltage VA and the second reference voltage VB at the same time, and the digital-to-analog converter 200 is configured to perform digital-to-analog conversion on count values represented by a plurality of count clocks outputted by the counter 100 based on the first reference voltage VA and the second reference voltage VB, so as to generate a reference voltage.
In this embodiment, the dac 200 performs digital-to-analog conversion on the count value of the counter 100 based on the first reference voltage VA and the second reference voltage VB, and when the counter 100 performs continuous counting based on the initial clock signal CLK, the dac 200 may obtain a continuous voltage curve (the curve described herein includes a special curve including a straight line and a broken line) that changes with time after performing digital-to-analog conversion on the continuous count value, and the voltage curve is a voltage variation curve of the reference voltage Vref with time.
Further, in the present embodiment, the digital-to-analog converter 200 includes: a first leg and a plurality of second legs. The first branch circuit comprises a plurality of second resistors and a plurality of first resistors which are connected in series between the input end of the first reference voltage VA and the output end of the reference voltage Vref. Each of the plurality of second branches includes: the first input end of the selection switch is connected with the input end of the first reference voltage VA, and the second input end of the selection switch is connected with the input end of the second reference voltage VB; the second resistors are connected between the first branch and the output end of the selection switch. The plurality of selection switches on the plurality of second branches (each of the second branches includes a selection switch) corresponds to a plurality of counting clocks output by the receiving counter 100 (i.e., each of the selection switches corresponds to receiving a counting clock), and a first resistor is included between any two adjacent connection nodes between the second branches and the first branch.
It will be appreciated that the number of second branches in the digital-to-analog converter 200 is equal to the number of counting clocks output by the counter 100 and the number of selection switches.
Optionally, the selection switch on each second branch includes, but is not limited to, a two-out selection switch or a relay, etc.
Optionally, in a first embodiment of the present disclosure, each second branch includes a second resistor, and a resistance value of the second resistor on each second branch is twice a resistance value of the first resistor. At this time, if the resistance of the first resistor is R, the resistance of the second resistor is 2R. Therefore, only one resistor is connected in series on each second branch, so that the area of the step diagram is saved.
Optionally, in the first embodiment of the present disclosure, each second branch includes two second resistors connected in series, and a resistance value of each second resistor on each second branch is equal to a resistance value of the first resistor. At this time, if the resistance of the first resistor is R, the resistance of the second resistor is R. In this way, the resistors with the same resistance value are adopted in the digital-to-analog converter 200, so that the specification of the resistors can be unified, and the influence of the resistance difference of the resistors with different specifications on the performance of the digital-to-analog converter 200 is avoided.
Further, in the present embodiment, the voltage value of at least one of the first reference voltage VA and the second reference voltage VB is adjustable in different counting periods of the counter 100.
Based on the operation principle of the digital-to-analog converter, it can be seen that, in one counting period of the counter 100, the slope k= (VB-VA)/T of the reference voltage curve generated by the digital-to-analog converter 200 based on the plurality of counting clocks and the first reference voltage VA and the second reference voltage VB is unchanged. Then the slope K of the reference voltage curve can be adjusted by adjusting the value of (VB-VA) at different counting cycles of the counter 100. That is, in different counting periods of the counter 100, the voltage value of at least one of the first reference voltage VA and the second reference voltage VB is set to be adjustable, so that the purpose of generating the reference voltage Vref with any slope can be achieved, and any adjustment of the changing direction (including positive change or negative change) of the reference voltage can be achieved.
Specifically, in the first embodiment of the present disclosure, when the voltage value of at least one of the first reference voltage VA and the second reference voltage VB is adjusted, the magnitude relation between the adjusted first reference voltage VA and second reference voltage VB in any adjacent two counting periods of the counter 100 is unchanged, and only the difference between the first reference voltage VA and the second reference voltage VB is different. Such as: so that in the first counting period of the counter 100, the adjusted voltage value of the first reference voltage VA is smaller than the voltage value of the second reference voltage VB, and there is a first difference between the voltage value of the first reference voltage VA and the voltage value of the second reference voltage VB, and in the second counting period of the counter 100, the adjusted voltage value of the first reference voltage VA is also smaller than the voltage value of the second reference voltage VB, and there is a second difference between the voltage value of the first reference voltage VA and the voltage value of the second reference voltage VB, wherein the first counting period and the second counting period are adjacent, and the first difference is unequal to the second difference; or the adjusted voltage value of the first reference voltage VA is greater than the voltage value of the second reference voltage VB in the first counting period of the counter 100, and a third difference is formed between the voltage value of the first reference voltage VA and the voltage value of the second reference voltage VB, and the adjusted voltage value of the first reference voltage VA is also greater than the voltage value of the second reference voltage VB in the second counting period of the counter 100, and a fourth difference is formed between the voltage value of the first reference voltage VA and the voltage value of the second reference voltage VB, wherein the first counting period and the second counting period are adjacent, and the third difference is not equal to the fourth difference. In this way, it is possible to adjust only the value of the generation slope of the reference voltage Vref during any adjacent two or more counting periods of the counter 100, while keeping the positive and negative of the generation slope of the reference voltage Vref unchanged.
In the second embodiment of the present disclosure, when the voltage value of at least one of the first reference voltage VA and the second reference voltage VB is adjusted, the magnitude relation between the adjusted first reference voltage VA and second reference voltage VB in adjacent two counting periods of the counter 100 is different, but the difference between the first reference voltage VA and the second reference voltage VB is the same; or the magnitude relation between the adjusted first reference voltage VA and the adjusted second reference voltage VB in two adjacent counting periods of the counter 100 is different, and the difference between the first reference voltage VA and the adjusted second reference voltage VB is also different. Such as: such that the voltage value of the adjusted first reference voltage VA is smaller than the voltage value of the second reference voltage VB during the first counting period of the counter 100, and the voltage value of the adjusted first reference voltage VA is larger than the voltage value of the second reference voltage VB during the second counting period of the counter 100, wherein the first and second counting periods are adjacent. In this way, positive and negative adjustment of the generation slope of the reference voltage Vref, or both the magnitude adjustment and the positive and negative adjustment of the generation slope of the reference voltage Vref can be achieved in any adjacent two or more counting periods of the counter 100.
Further, if the reference voltage Vref is stepped from the first reference voltage VA to the second reference voltage VB in each counting period of the counter 100. At this time, when the voltage value of at least one of the first reference voltage VA and the second reference voltage VB is adjusted, the voltage value of the adjusted first reference voltage VA is equal to the voltage value of the second reference voltage VB before adjustment in any two counting periods of the counter 100 (i.e., the voltage value of the first reference voltage VA in the second counting period of the counter 100 is equal to the voltage value of the second reference voltage VB in the first counting period of the counter 100, which is adjacent to the second counting period). Thus, a continuous reference voltage curve can be obtained, and the voltage value of the reference voltage Vref is prevented from jumping between adjacent adjustment periods.
By way of example, also taking the example that the counter 100 can output 9 count clocks, referring to fig. 3, fig. 3 shows a schematic diagram of the internal circuit structure of the digital-to-analog converter in fig. 2. At this time, the digital-to-analog converter 200 has 9 second branches, and a plurality of selection switches (including S0, S1, S2, & gt, S8) in the 9 second branches correspond to the first count clock D <0>, the second count clock D <1>, the third count clock D <2>, the fourth count clock D <3>, the fifth count clock D <4>, the sixth count clock D <5>, the seventh count clock D <6>, the eighth count clock D <7>, and the ninth count clock D <8> outputted by the reception counter 100, respectively, as respective control signals, so that the reference voltage Vref can be controlled to change from VA to VB in 512 steps. It is understood that the sub-clock signals selected by the counter 100 are different, and the clock periods of the corresponding counting clocks D <0> to D <8> are also different.
Meanwhile, it is assumed that in this example, each of the selection switches in the digital-to-analog converter 200 selects to output the first reference voltage VA to the corresponding node of the first branch when the corresponding received control signal is high (or corresponding to logic 1), and selects to output the second reference voltage VB to the corresponding node of the first branch when the corresponding received control signal is low (or corresponding to logic 0). Further, as can be seen from fig. 3, the reference voltage Vref is changed as follows in one counting period of the counter:
in the initial state of the counter 100 (corresponding time t=0us): d <8:0> =111111111, vref=va.
At the final state of the counter 100 (corresponding time t=512 us): d <8:0> =0000000000, vref=vb.
Based on this, if the voltage value of at least one of the first reference voltage VA and the second reference voltage VB is adjusted, the initial value and the final value of the reference voltage Vref also change accordingly. In this process, if the duration of one counting period T of the counter 100 is kept unchanged or the ratio of the duration of the counting period T of the counter 100 is kept different from the ratio of the (VB-VA), a reference voltage curve with an arbitrary slope can be finally generated, so as to realize an arbitrary adjustment of the slope of the reference voltage Vref in different counting periods.
For example, referring to fig. 4, three curves in fig. 4 represent voltage variation curves of the first reference voltage VA, the second reference voltage VB, and the reference voltage Vref, respectively. Assuming that va=0v and vb=2v during the first counting period of the counter 100 (i.e. during time period 0-512 us), then the corresponding:
In the initial state (corresponding time t=0us): d <8:0> =111111111, vref=0v.
In the final state (corresponding time t=512 us): d <8:0> =0000000000, vref=2v.
Thereafter, the counter 100 restarts counting, and va=2v, vb=1v during the second counting period of the counter 100, i.e., the period 512 to 1024 us), then the following applies:
In the initial state (corresponding time t=0us): d <8:0> =111111111, vref=2v.
In the final state (corresponding time t=512 us): d <8:0> =0000000000, vref=1v.
Thereafter, the counter 100 restarts counting again, and va=1v, vb=2v during the period 1024 to 1536us, which is the third counting period of the counter 100), then the following applies:
In the initial state (corresponding time t=0us): d <8:0> =111111111, vref=1v.
In the final state (corresponding time t=512 us): d <8:0> =0000000000, vref=2v.
It can be seen from this that by adjusting the first reference voltage VA and/or the second reference voltage VB, it is possible to achieve any adjustment of the magnitude and/or the positive/negative of the curve slope of the reference voltage Vref in different counting periods.
Fig. 5 shows a flow chart diagram of a method of generating a reference voltage provided in accordance with an embodiment of the present disclosure.
As shown in fig. 5, in the present embodiment, the reference voltage generating method includes performing steps S1 to S2.
Wherein in step S1 a plurality of count clocks are generated based on the initial clock signal.
In step S2, digital-to-analog conversion is performed on count values characterized by the plurality of count clocks based on the first reference voltage and the second reference voltage, and a reference voltage is generated.
Further, in this embodiment, in different counting periods of the counter, a voltage value of at least one of the first reference voltage and the second reference voltage is adjustable.
The specific adjustment principle of the adjustment process can be referred to the description of fig. 2 to 4 herein, and will not be repeated here.
In summary, the present disclosure is directed to generating a reference voltage of arbitrary slope by employing a counter and a digital-to-analog converter. In the process of generating the reference voltage, as the voltage value of at least one of the first reference voltage and the second reference voltage received by the digital-to-analog converter is adjustable in different counting periods (the period duration of each counting period is equal) of the counter, the change amplitude of the reference voltage in the same time can be changed by adjusting at least one of the first reference voltage and the second reference voltage, and the purpose of adjusting the generation slope of the reference voltage is achieved. And in adjusting at least one of the first reference voltage and the second reference voltage, reference voltages having different slopes can be generated based on the first reference voltage and the second reference voltage having different differences (including different magnitudes of the differences, and/or different positive and negative differences). Therefore, the reference voltage with any slope can be generated in different counting periods of the counter, and any adjustment of the change direction (including positive change or negative change) of the reference voltage is realized.
It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
Finally, it should be noted that: it is apparent that the above examples are only illustrative of the present invention and are not limiting of the embodiments. Other variations or modifications of the above teachings will be apparent to those of ordinary skill in the art. It is not necessary here nor is it exhaustive of all embodiments. And obvious variations or modifications thereof are contemplated as falling within the scope of the present invention.
Claims (8)
1. A reference voltage generating circuit, comprising:
a counter for performing continuous counting based on an initial clock signal, generating a plurality of count clocks;
A digital-to-analog converter connected with the counter and receiving a first reference voltage and a second reference voltage for performing digital-to-analog conversion on successive count values characterized by the plurality of count clocks based on the first reference voltage and the second reference voltage to generate a reference voltage whose voltage value varies with time,
And in different counting periods of the counter, the voltage value of at least one of the first reference voltage and the second reference voltage is adjustable, and the purpose of generating the reference voltage with any slope is achieved by adjusting at least one of the first reference voltage and the second reference voltage to change the variation amplitude of the reference voltage in the same time, wherein the slope of the reference voltage is equal to the ratio of the difference value of the first reference voltage and the second reference voltage to the counting period.
2. The reference voltage generation circuit of claim 1 wherein the digital-to-analog converter comprises:
the first branch circuit comprises a plurality of second resistors and a plurality of first resistors which are connected in series between a first reference voltage input end and a reference voltage output end;
A plurality of second branches, each second branch comprising:
the first input end of the selection switch is connected with the first reference voltage input end, and the second input end of the selection switch is connected with the second reference voltage input end;
a plurality of second resistors connected between the first branch and the output end of the selection switch,
The plurality of selection switches on the plurality of second branches correspondingly receive the plurality of counting clocks, and a first resistor is arranged between any two adjacent second branches and the connection node of the first branch.
3. The reference voltage generating circuit according to claim 2, wherein each of the second branches includes a second resistor, and a resistance value of each of the second resistors is twice a resistance value of the first resistor.
4. The reference voltage generation circuit according to claim 2, wherein each second branch includes two second resistors connected in series, and a resistance value of each second resistor is equal to a resistance value of the first resistor.
5. The reference voltage generation circuit according to claim 2, wherein a magnitude relation between the first reference voltage and the second reference voltage is unchanged and a difference between the first reference voltage and the second reference voltage is different in any two count periods of the counter.
6. The reference voltage generation circuit according to claim 2, wherein the magnitude relation between the first reference voltages is different in any two counting periods of the counter.
7. The reference voltage generating circuit according to claim 1, wherein a voltage value of the first reference voltage in the second counting period of the counter is equal to a voltage value of the second reference voltage in the first counting period of the counter,
The first counting period and the second counting period are adjacent, and the reference voltage is stepped from the first reference voltage to the second reference voltage in the first counting period and the second counting period.
8. A method for generating a reference voltage, comprising:
Continuously counting based on the initial clock signal to generate a plurality of counting clocks;
performing digital-to-analog conversion on successive count values characterized by the plurality of count clocks based on the first reference voltage and the second reference voltage, generating a reference voltage having a voltage value that varies with time,
And in different counting periods of the counter, the voltage value of at least one of the first reference voltage and the second reference voltage is adjustable, and the purpose of generating the reference voltage with any slope is achieved by adjusting at least one of the first reference voltage and the second reference voltage to change the variation amplitude of the reference voltage in the same time, wherein the slope of the reference voltage is equal to the ratio of the difference value of the first reference voltage and the second reference voltage to the counting period.
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| CN108648717A (en) * | 2018-07-27 | 2018-10-12 | 北京集创北方科技股份有限公司 | A kind of reference voltage generating circuit, reference voltage generation method, chip and liquid crystal display |
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| Publication number | Publication date |
|---|---|
| CN114625202A (en) | 2022-06-14 |
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