CN114578212A - Chip testing method and system - Google Patents

Abstract

The present disclosure relates to the field of electronic technologies, and in particular, to a chip testing method and a chip testing system. The method is used for testing a preset number of test signals in a chip to be tested, and comprises the following steps: determining the number of output ports for testing in the chip and the number of test signals required to be output by each output port; setting a marking signal corresponding to each test output port in the chip; for each test output port, sampling a test signal required to be output by the test output port and a corresponding mark signal according to a clock signal and a preset sampling frequency based on a parallel-serial signal converter arranged in a chip, and outputting the obtained serial signal from the test output port; and recovering the received serial signals by using the editable logic device to obtain a preset number of test signals, and testing the preset number of test signals by using the logic analyzer. The method can save the output port for testing the chip and reduce the development period and the cost of the chip.

Description

A chip testing method and testing system

technical field

The present application relates to the field of electronic technology, and in particular, to a chip testing method and testing system.

Background technique

With the development of science and technology, chips have been applied to all walks of life. In order to meet the needs of users, the functions of chips are increasing. Therefore, during chip testing, more output ports are required to transmit the logic signals corresponding to multiple chip functions in parallel to the logic analyzer, and then the logic analyzer analyzes and tests the received signals to determine the Whether there is any abnormal signal in the chip.

However, with the continuous increase of chip functions, the size of the chip is getting smaller and smaller. If multiple output ports are used, the development cycle and development cost of the chip will be seriously affected.

Therefore, there is an urgent need for a chip testing method and a testing system to solve the above problems.

SUMMARY OF THE INVENTION

The present application provides a chip testing method and testing system, which can save output ports for chip testing, thereby reducing the development cycle and development cost of the chip.

In a first aspect, an embodiment of the present application provides a chip testing method for testing a preset number of test signals in a chip to be tested, and the method includes:

Determine the test output ports for outputting test signals among the available output ports of the chip to be tested, and determine the number of test signals that each test output port needs to output;

According to the number of test signals required to be output by each test output port, a marker signal corresponding to the test output port is set inside the chip to be tested;

For each test output port, based on the parallel-to-serial signal converter set inside the chip to be tested, serialize the test signal to be output by the test output port and the corresponding marker signal according to the clock signal according to the preset sampling frequency Sampling, outputting the serial signal obtained by serial sampling from the test output port;

An editable logic device is used to receive the serial signal output by each of the test output ports, and the serial signal is restored according to the sampling frequency to obtain the preset number of test signals, and the preset number of test signals is obtained. A number of test signals are output to the logic analyzer in parallel;

The received test signal is tested by using the logic analyzer.

In a possible design, the marker signal is a periodic signal, and in each cycle, the time interval between adjacent signal values is equal to the test signal corresponding to the marker signal and the marker signal being performed once Time required for serial sampling.

In a possible design, the serial sampling of the test signal and the corresponding marker signal to be output by the test output port according to the preset sampling frequency according to the clock signal, including:

determining the sampling sequence for serially sampling the test signal and the corresponding marker signal to be output by the test output port;

According to the sampling sequence, the test signal and the corresponding mark signal to be output by the test output port are sequentially and cyclically sampled according to the sampling frequency, and the sampled signals are connected in series to form a serial signal.

In a possible design, restoring each serial signal according to the sampling frequency includes:

Determine the target number of parallel signals to be serially sampled when the serial signal is obtained; the parallel signals include mark signals and test signals;

According to the sampling frequency and the target number, the signal values are sequentially and cyclically extracted from the serial signal, and the signal values extracted in each cycle are sorted in time order to generate a new parallel signal; a quantity equal to said target quantity;

Determine the position of the marker signal corresponding to the serial signal in the generated new parallel signal, determine new parallel signals other than the marker signal corresponding to the serial signal according to the position and the sampling order, and obtain the serial signal Corresponding relationship of each test signal that is serially sampled when the line signal is performed;

According to the corresponding relationship, new parallel signals other than the mark signal corresponding to the serial signal are restored to each test signal.

In a possible design, restoring new parallel signals other than the marked signal corresponding to the serial signal to each test signal according to the corresponding relationship includes:

For each new parallel signal, determine the time interval between the signal period of the test signal corresponding to the new parallel signal and the adjacent signal values; according to the time interval between the signal period of the test signal and the adjacent signal values and the extraction time of each signal value in the new parallel signal, place each signal value in the new parallel signal in the signal period according to its position on the signal period, and restore the new parallel signal to Test signal with full signal period.

In one possible design, the test output port is one.

In a possible design, the programmable logic device is an FPGA;

and / or,

The sampling frequency of the clock signal is 200MHZ.

In a second aspect, an embodiment of the present application provides a chip testing system, including a chip to be tested, an editable logic device, and a logic analyzer;

The chip to be tested has a test output port, and a mark signal corresponding to the test output port is set inside the chip to be tested. Based on the parallel-serial signal converter set inside the chip to be tested, according to the clock signal The preset sampling frequency performs serial sampling on the test signal required to be output by the test output port and the corresponding marker signal, and outputs the serial signal obtained by serial sampling from the test output port;

The editable logic device is connected in communication with the output port of the chip to be tested and the logic analyzer, and is used for receiving the serial signal output by each of the test output ports, and according to the sampling frequency. recovering the serial signal to obtain the preset number of test signals, and output the preset number of test signals to the logic analyzer in parallel;

The logic analyzer is used to test the received test signal.

In a possible design, the marker signal is a periodic signal, and in each cycle, the time interval between adjacent signal values is equal to the test signal corresponding to the marker signal and the marker signal being performed once Time required for serial sampling

In a possible design, the serial sampling of the test signal and the corresponding marker signal to be output by the test output port according to the preset sampling frequency according to the clock signal, including:

determining the sampling sequence for serially sampling the test signal and the corresponding marker signal to be output by the test output port;

According to the sampling sequence, the test signal and the corresponding mark signal to be output by the test output port are sequentially and cyclically sampled according to the sampling frequency, and the sampled signals are connected in series to form a serial signal.

The invention firstly determines the number of test output ports of the chip to be tested and the number of test signals that each output port needs to output, and then sets the corresponding mark signal inside the chip to be tested. Then, for each test output port, based on the parallel-serial signal converter set inside the chip to be tested, serially sample the test signal and the corresponding marker signal required to be output by the test output port according to the clock signal according to the preset sampling frequency. , the serial signal obtained by serial sampling is output from the test output port to the editable logic device, and the editable logic device restores the serial signal according to the sampling frequency to obtain the required output test signal, and The obtained test signal is output to the logic analyzer in parallel; finally, the received test signal is tested by the logic analyzer. The chip measurement method and the measurement system provided by the present invention can save output ports for chip testing, thereby reducing the development cycle and development cost of the chip.

Description of drawings

In order to illustrate the embodiments of the present invention or the technical solutions in the prior art more clearly, the following briefly introduces the accompanying drawings that need to be used in the description of the embodiments or the prior art. Obviously, the drawings in the following description are For some embodiments of the present invention, for those of ordinary skill in the art, other drawings can also be obtained according to these drawings without creative efforts.

1 is a schematic diagram of a chip testing method provided by an embodiment of the present invention;

FIG. 2 is a schematic diagram of a chip testing system provided by an embodiment of the present invention.

Detailed ways

The present application will be described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application, but not to limit the present application.

In the description of the embodiments of the present application, unless otherwise explicitly specified and limited, the terms "first" and "second" are only used for the purpose of description, and cannot be understood as indicating or implying relative importance; unless otherwise specified Or to illustrate, the term "plurality" refers to two or more; the terms "connection" and "fixed" should be understood in a broad sense, for example, "connection" can be a fixed connection or a detachable connection, or It is integrally connected, or electrically connected; it can be directly connected or indirectly connected through an intermediate medium. For those of ordinary skill in the art, the specific meanings of the above terms in this application can be understood according to specific situations.

In the description of this specification, it should be understood that the directional words such as "upper" and "lower" described in the embodiments of the present application are described from the perspective shown in the accompanying drawings, and should not be construed as referring to the embodiments of the present application. limited. Also, in this context, it should also be understood that when an element is referred to as being "on" or "under" another element, it can not only be directly connected "on" or "under" the other element, but also Indirectly connected "on" or "under" another element through intervening elements.

As mentioned above, in the prior art, chip functions are more and more, but the chip size is getting smaller and smaller. If multiple output ports are used for chip testing, the development cycle and development cost of the chip will be seriously affected.

In order to solve this technical problem, it can be considered to set a marker signal in the chip, and then convert the marker signal and the signal to be tested into serial signals and output them together from the test output port, thereby saving the test output port.

As shown in FIG. 1 , an embodiment of the present invention provides a chip testing method, which is used to test a preset number of test signals in a chip to be tested, and the method includes:

Step 100: Determine a test output port for outputting test signals among the available output ports of the chip under test, and determine the number of test signals required to be output by each test output port;

Step 102, according to the quantity of the test signal required to be output by each test output port, set a marker signal corresponding to the test output port inside the chip to be tested;

Step 104, for each test output port, based on the parallel-to-serial signal converter set inside the chip to be tested, according to the clock signal according to the preset sampling frequency, serially sample the test signal and the corresponding marker signal to be output by the test output port. , output the serial signal obtained by serial sampling from the test output port;

Step 106, use the programmable logic device to receive the serial signal output by each test output port, and restore the serial signal according to the sampling frequency to obtain a preset number of test signals, and output the preset number of test signals in parallel to logic analyzer;

Step 108, use a logic analyzer to test the received test signal.

In the embodiment of the present invention, first determine the number of test output ports of the chip under test and the number of test signals that each output port needs to output, and then set corresponding mark signals inside the chip under test. Then, for each test output port, based on the parallel-serial signal converter set inside the chip to be tested, serially sample the test signal and the corresponding marker signal required to be output by the test output port according to the clock signal according to the preset sampling frequency. , the serial signal obtained by serial sampling is output from the test output port to the editable logic device, and the editable logic device restores the serial signal according to the sampling frequency to obtain the required output test signal, and The obtained test signal is output to the logic analyzer in parallel; finally, the received test signal is tested by the logic analyzer. The chip measurement method provided in this embodiment can save output ports for chip testing, thereby reducing the development cycle and development cost of the chip.

The following describes how each step shown in FIG. 1 is performed.

First, for step 100, a test output port for outputting test signals is determined among the available output ports of the chip under test, and the number of test signals required to be output by each test output port is determined.

A chip is an integrated circuit made up of a large number of transistors. As mentioned above, the functions of the chip are more and more, but the size of the chip is getting smaller and smaller. Therefore, in order to reduce the number of the general-purpose output ports of the chip, multiple test signals can be output from one test output port.

For a chip to be tested, the number of test output ports can be determined according to the number of available output ports and the number of signals to be tested. For example, if there are many signals to be tested, serial sampling of all the signals to be tested is likely to cause confusion or technically impermissible, then the signals to be tested can be grouped, and each group of signals is output from a different output port.

Then, for step 102, according to the number of test signals required to be output by each test output port, a marker signal corresponding to the test output port is set inside the chip under test.

In this embodiment, in order to save the output port of the chip, the clock signal port is not reserved, then after the programmable logic device receives the serial signal sent by the test output port, it cannot synchronously sample the serial signal, so it is impossible to The corresponding relationship between the new parallel signal restored by the editable logic device and the original test signal is determined.

Therefore, a marker signal needs to be set inside the chip to be tested, and the marker signal corresponds to the test output port and the signal to be tested. In this way, by using the marker signal, it is possible to determine the difference between the new parallel signal restored by the programmable logic device and the original test signal. Correspondence. It should be noted that if the number of test signals required to be output by the test output port is one, there is no need to set a flag signal inside the chip, because in this case, the serial signal can be directly determined as the test signal.

It should be noted that, in order to ensure that the marker signal functions as a marker, it is necessary to ensure that in each serial sampling period, the signal values of the collected marker signal are arranged according to the arrangement rule of the marker signal in one cycle. For example, the arrangement rule of marker signals in one cycle is 1001, then the value of the marker signal collected in the first serial sampling cycle is 1, the value of the marker signal collected in the second serial sampling cycle is 0, and the value of the marker signal collected in the second serial sampling cycle is 0. The value of the marker signal collected in the first serial sampling period is 0, the value of the marker signal collected in the fourth serial sampling period is 1, the value of the marker signal collected in the fifth serial sampling period is 1, and the value of the marker signal collected in the sixth serial sampling period The value of the mark signal collected in the line sampling period is 0, the value of the mark signal collected in the seventh serial sampling period is 0, the value of the mark signal collected in the eighth serial sampling period is 1, and so on.

In order to achieve the above purpose, in some embodiments, the marker signal is a periodic signal, and in each cycle, the time interval between adjacent signal values is equal to the test signal and the marker signal corresponding to the marker signal. The time required to take one serial sample. It should be noted that the periodic signal here has the characteristic that the time interval between adjacent periods is equal to the time interval between adjacent signal values.

For example, the marking signal may be a binary number with a fixed number of bits, and in each period, the marking signal is arranged according to the law of 1010_1100. In this way, when the number of test signals corresponding to the marker signal is 7, the corresponding parallel-serial signal converter needs to perform cyclic sampling on the marker signal and its corresponding 7 test signals, that is, 8 samples are performed in each cycle, If each sampling interval is 1 second, then the time required for one serial sampling is 8 seconds. At this time, in each cycle of the flag signal, the time interval between adjacent signal values is 8 seconds. In this way, it can be ensured that the first rising edge of the clock signal collects the 1 sent by the marker signal, the ninth rising edge collects the 0 sent by the marker signal, the 17th rising edge collects the 1 sent by the marker signal, and the 25th rise. The 0 sent along the acquisition to the marker signal... and so on, 8 cycles. In this way, after the programmable logic device receives the serial signal corresponding to the marking signal, the serial signal is restored according to the same sampling frequency, and the marking signal 1010_1100 can be obtained by sampling.

Then, for step 104, for each test output port, based on the parallel-serial signal converter set inside the chip under test, according to the clock signal according to the preset sampling frequency, the test signal and the corresponding mark signal required to be output by the test output port. Take serial sampling, including:

Step A1, determine the sampling order of serial sampling of the required output test signal of the test output port and the corresponding marker signal;

Step A2: According to the sampling sequence, according to the sampling frequency, the test signal and the corresponding mark signal to be output by the test output port are sampled sequentially and cyclically, and the sampled signals are connected in series to form a serial signal.

For step A1, for example, there are 7 test signals, which are respectively denoted as B signal, C signal, D signal, E signal, F signal, G signal and H signal, and the marked signal is denoted as A signal. Then, for these 8 signals, the sampling order can be determined to be sequentially sampled from the A to H signals.

For step A2, according to the sampling sequence determined in step A1, according to the preset sampling frequency, in the first cycle, the first rising edge of the clock signal collects the signal value of the A signal, and the second rising edge collects the signal value of the B signal. Signal value, the 3rd rising edge collects the signal value of the C signal... The 8th rising edge collects the signal value of the H signal, and so on, 8 cycles.

Finally, the cyclically sampled signals are concatenated into a serial signal.

In this embodiment, the test signal and the mark signal are sorted and then sampled in this order, so that confusion can be avoided when the parallel signals are serialized and the serial signals are subsequently restored to new parallel signals.

It should be noted that after the signal period T of the clock signal is determined, the user can determine the sampling frequency according to the test needs, for example, the sampling frequency f=1/T, or the sampling frequency f=1/(2T), the application No specific limitation is made; in addition, the signal may be collected on the rising edge of the clock signal, or the signal may be collected on the falling edge, as long as the signal is collected according to a certain rule, which is not specifically limited in this application.

Next, for step 106, use the programmable logic device to receive the serial signal output by each test output port, and restore the serial signal according to the sampling frequency to obtain a preset number of test signals, including:

Determine the target number of parallel signals to be serially sampled when the serial signal is obtained; the parallel signals include mark signals and test signals;

According to the sampling frequency and the target number, the signal values are sequentially and cyclically extracted from the serial signal, and the signal values extracted in each cycle are sorted in time order to generate a new parallel signal; a quantity equal to said target quantity;

Determine the position of the marker signal corresponding to the serial signal in the generated new parallel signal, determine new parallel signals other than the marker signal corresponding to the serial signal according to the position and the sampling order, and obtain the serial signal Corresponding relationship of each test signal that is serially sampled when the line signal is performed;

According to the corresponding relationship, new parallel signals other than the mark signal corresponding to the serial signal are restored to each test signal.

The following describes the specific process of restoring the serial signal to a new parallel signal in this implementation manner with a specific example:

First, determine the target number of parallel signals to be serially sampled when the serial signal is obtained. For example, 7 test signals are used in serial, which are denoted as B signal, C signal, D signal, E signal, F signal, G signal and H signal respectively, and 1 mark signal is denoted as A signal.

Then the target number of the parallel signals is 8, and the 8 signals are sampled sequentially in the sampling order from the A to H signals.

Then, assuming that there are 640 signal values in the serial signal, then according to the sampling frequency and the target number of 8, the 1st, 9th, 17th, 25th...633rd signal values in the 640 signal values can be regarded as the first 1 new parallel signal; 2, 10, 18, 26...634 signal values in the 640 signal values as the 2 new parallel signal; , 19, 27...635 signal values as the 3rd new parallel signal; and so on, the 8th, 16th, 24th, 32nd... parallel signal, so that the serial signal can be converted into 8 new parallel signals.

Then, from the 8 new parallel signals, the third new parallel signal is determined as the marker signal A, then in combination with the sampling sequence A to H, it can be seen that the fourth new parallel signal corresponds to the test signal B, and the fifth new parallel signal corresponds to the test signal B and the fifth new parallel signal. The parallel signal corresponds to the test signal C... and so on, the second new parallel signal corresponds to the test signal H.

Finally, restore the new parallel signals other than the marked signal corresponding to the serial signal to each test signal according to the corresponding relationship, in some embodiments, including:

For each new parallel signal, determine the time interval between the signal period of the test signal corresponding to the new parallel signal and the adjacent signal values; according to the time interval between the signal period of the test signal and the adjacent signal values and the extraction time of each signal value in the new parallel signal, place each signal value in the new parallel signal in the signal period according to its position on the signal period, and restore the new parallel signal to Test signal with full signal period.

Next, the implementation process of this embodiment is described by taking the fourth new parallel signal as an example.

As mentioned above, the fourth new parallel signal corresponds to the test signal B, assuming that the signal period of the B signal is 10 seconds, the time interval between adjacent signal values is 1 second, and it is assumed that the fourth new parallel signal has a signal period of 10 seconds. The signal value arrangement rule is 10101101..., then for the first signal value 1, according to its extraction time, it can be determined which signal value 1 corresponds to the number of signal cycles in the B test signal (for example, The third signal value of the second signal period), and so on, each signal value in the fourth new parallel signal can be corresponding to the corresponding signal period of the B measurement signal and the position on the signal period, so , the new parallel signal can be restored to a test signal with a full signal period.

Finally, for step 108, a logic analyzer is used to test the received test signal.

A logic analyzer is an instrument that analyzes the logical relationship of a digital system. It is an instrument that uses a clock to collect and display digital signals from test equipment. Its main function is to determine timing. The present application firstly uses a logic analyzer to receive parallel signals transmitted by an editable logic device, then compares the received signal with a preset threshold level, and finally locates an abnormal signal according to the comparison result.

In this embodiment, the logic analyzer can receive multiple test signals at the same time, and test the multiple test signals at the same time, if the abnormal signal can be quickly located.

In some embodiments, in order to save the output port of the chip to the greatest extent and reduce the size of the chip, there is only one test output port, so that the development cycle and development cost of the chip can be reduced to the maximum extent.

In some embodiments, in order to improve the function and versatility of the system, the programmable logic device is an FPGA; this is because FPGA can not only solve the shortcomings of custom circuits, but also overcome the shortcomings of the limited number of gate circuits of the original programmable device, Using FPGA, the system is simple and the cost is low.

In addition, in order to improve the sampling accuracy, in some embodiments, the sampling frequency of the clock signal is 200MHz. The sampling frequency can more accurately capture the signal value of each test signal.

It should be noted that selecting an FPGA and a sampling frequency of 200MHZ is a preferred method. In other embodiments, the editable logic device can also select a CPLD, and the sampling frequency can also be other frequencies, which are not specifically limited in this application.

As shown in FIG. 2 , an embodiment of the present invention further provides a chip testing system, which includes a chip to be tested, an editable logic device, and a logic analyzer;

The chip to be tested has a test output port, and a mark signal corresponding to the test output port is set inside the chip to be tested. Based on the parallel-serial signal converter set inside the chip to be tested, according to the clock signal The preset sampling frequency performs serial sampling on the test signal required to be output by the test output port and the corresponding marker signal, and outputs the serial signal obtained by serial sampling from the test output port;

The editable logic device is connected in communication with the output port of the chip to be tested and the logic analyzer, and is used for receiving the serial signal output by each of the test output ports, and according to the sampling frequency. recovering the serial signal to obtain the preset number of test signals, and output the preset number of test signals to the logic analyzer in parallel;

The logic analyzer is used to test the received test signal.

In some implementations, the marker signal is a periodic signal, and in each cycle, the time interval between adjacent signal values is equal to one serialization of the test signal corresponding to the marker signal and the marker signal Time required for sampling.

In some embodiments, the serial sampling of the test signal and the corresponding marker signal to be output by the test output port according to the preset sampling frequency according to the clock signal includes:

determining the sampling sequence for serially sampling the test signal and the corresponding marker signal to be output by the test output port;

According to the sampling sequence, the test signal and the corresponding mark signal to be output by the test output port are sequentially and cyclically sampled according to the sampling frequency, and the sampled signals are connected in series to form a serial signal.

In some embodiments, the recovering each serial signal according to the sampling frequency includes:

Determine the target number of parallel signals to be serially sampled when the serial signal is obtained; the parallel signals include mark signals and test signals;

According to the sampling frequency and the target number, the signal values are sequentially and cyclically extracted from the serial signal, and the signal values extracted in each cycle are sorted in time order to generate a new parallel signal; a quantity equal to said target quantity;

Determine the position of the marker signal corresponding to the serial signal in the generated new parallel signal, determine new parallel signals other than the marker signal corresponding to the serial signal according to the position and the sampling order, and obtain the serial signal Corresponding relationship of each test signal that is serially sampled when the line signal is performed;

According to the corresponding relationship, new parallel signals other than the mark signal corresponding to the serial signal are restored to each test signal.

In some embodiments, restoring new parallel signals other than the marked signal corresponding to the serial signal to each test signal according to the corresponding relationship includes:

For each new parallel signal, determine the time interval between the signal period of the test signal corresponding to the new parallel signal and the adjacent signal values; according to the time interval between the signal period of the test signal and the adjacent signal values and the extraction time of each signal value in the new parallel signal, place each signal value in the new parallel signal in the signal period according to its position on the signal period, and restore the new parallel signal to Test signal with full signal period.

In some embodiments, the test output port is one.

In some embodiments,

The editable logic device is an FPGA;

and / or,

The sampling frequency of the clock signal is 200MHZ.

Since the above-mentioned chip testing system and the embodiment of the testing method of the present invention are based on the same concept, the specific content can be referred to the description in the embodiment of the positioning system of the present invention, which will not be repeated here.

It should be noted that, in this document, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply a relationship between these entities or operations. There is no such actual relationship or sequence. Moreover, the terms "comprising", "comprising" or any other variation thereof are intended to encompass a non-exclusive inclusion such that a process, method, article or device that includes a list of elements includes not only those elements, but also includes not explicitly listed or other elements inherent to such a process, method, article or apparatus. Without further limitation, an element qualified by the phrase "comprising a..." does not preclude the presence of additional identical elements in the process, method, article, or device that includes the element.

Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, but not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that it can still be The technical solutions described in the foregoing embodiments are modified, or some technical features thereof are equivalently replaced; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims (10)

1. a chip testing method is characterized in that, for testing the test signal of preset quantity in the chip to be tested, the method comprises: Determine the test output ports for outputting test signals among the available output ports of the chip to be tested, and determine the number of test signals that each test output port needs to output; According to the number of test signals required to be output by each test output port, a marker signal corresponding to the test output port is set inside the chip to be tested; For each test output port, based on the parallel-to-serial signal converter set inside the chip to be tested, serialize the test signal to be output by the test output port and the corresponding marker signal according to the clock signal according to the preset sampling frequency Sampling, outputting the serial signal obtained by serial sampling from the test output port; An editable logic device is used to receive the serial signal output by each of the test output ports, and the serial signal is restored according to the sampling frequency to obtain the preset number of test signals, and the preset number of test signals is obtained. A number of test signals are output to the logic analyzer in parallel; The received test signal is tested by using the logic analyzer. 2 . The test method according to claim 1 , wherein the marker signal is a periodic signal, and in each cycle, the time interval between adjacent signal values is equal to the test corresponding to the marker signal. 3 . The time required for one serial sampling of the signal and the marker signal. 3. test method according to claim 2, is characterized in that, described according to clock signal according to preset sampling frequency to described test output port required output test signal and corresponding mark signal carry out serial sampling, comprising: determining the sampling sequence for serially sampling the test signal and the corresponding marker signal to be output by the test output port; According to the sampling sequence, the test signal and the corresponding mark signal to be output by the test output port are sequentially and cyclically sampled according to the sampling frequency, and the sampled signals are connected in series to form a serial signal. 4. The test method according to claim 3, wherein, recovering each serial signal according to the sampling frequency, comprising: Determine the target number of parallel signals to be serially sampled when the serial signal is obtained; the parallel signals include mark signals and test signals; According to the sampling frequency and the target number, the signal values are sequentially and cyclically extracted from the serial signal, and the signal values extracted in each cycle are sorted in time order to generate a new parallel signal; a quantity equal to said target quantity; Determine the position of the marker signal corresponding to the serial signal in the generated new parallel signal, determine new parallel signals other than the marker signal corresponding to the serial signal according to the position and the sampling order, and obtain the serial signal Corresponding relationship of each test signal that is serially sampled when the line signal is performed; According to the corresponding relationship, new parallel signals other than the mark signal corresponding to the serial signal are restored to each test signal. 5. The test method according to claim 4 , wherein the new parallel signals other than the corresponding marked signal of the serial signal are restored to each test signal according to the corresponding relationship, comprising: For each new parallel signal, determine the time interval between the signal period of the test signal corresponding to the new parallel signal and the adjacent signal values; according to the time interval between the signal period of the test signal and the adjacent signal values and the extraction time of each signal value in the new parallel signal, place each signal value in the new parallel signal in the signal period according to its position on the signal period, and restore the new parallel signal to Test signal with full signal period. 6. The test method according to any one of claims 1-5, wherein the test output port is one. 7. test method according to any one of claim 1-6, is characterized in that, The editable logic device is an FPGA; and / or, The sampling frequency of the clock signal is 200MHZ. 8. A chip testing system, comprising a chip to be tested, an editable logic device and a logic analyzer; The chip under test has a test output port, and the chip under test is provided with a mark signal corresponding to the test output port. Based on the parallel-serial signal converter set inside the chip under test, according to the clock signal The preset sampling frequency performs serial sampling on the test signal required to be output by the test output port and the corresponding marker signal, and outputs the serial signal obtained by serial sampling from the test output port; The editable logic device is connected in communication with the output port of the chip to be tested and the logic analyzer, and is used for receiving the serial signal output by each of the test output ports, and according to the sampling frequency. recovering the serial signal to obtain the preset number of test signals, and output the preset number of test signals to the logic analyzer in parallel; The logic analyzer is used to test the received test signal. 9 . The testing system according to claim 8 , wherein the marker signal is a periodic signal, and in each cycle, the time interval between adjacent signal values is equal to the test corresponding to the marker signal. 10 . The time required for one serial sampling of the signal and the marker signal. 10. The test system according to claim 9, wherein the test signal and the corresponding marker signal required to be output by the test output port are serially sampled according to the preset sampling frequency according to the clock signal, comprising: determining the sampling sequence for serial sampling of the test signal and the corresponding marker signal to be output by the test output port; According to the sampling sequence, the test signal and the corresponding mark signal to be output by the test output port are sequentially and cyclically sampled according to the sampling frequency, and the sampled signals are connected in series to form a serial signal.

Images