CN114496032B - 4T3R circuit structure for realizing high-speed logic operation based on resistance change type memory - Google Patents
4T3R circuit structure for realizing high-speed logic operation based on resistance change type memoryInfo
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- CN114496032B CN114496032B CN202210042707.3A CN202210042707A CN114496032B CN 114496032 B CN114496032 B CN 114496032B CN 202210042707 A CN202210042707 A CN 202210042707A CN 114496032 B CN114496032 B CN 114496032B
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
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Abstract
本发明公开了一种基于阻变式存储器实现高速逻辑运算的4T3R电路结构，包括RRAM1的底部电极与NMOS晶体管M1的漏极、NMOS晶体管M2的漏极电连接；M1的栅极与WLA电连接；M2的栅极与WLC电连接；NMOS晶体管M2的源极和NMOS晶体管M3的源极均与RRAM2的顶部电极电连接；NMOS晶体管M3的栅极与WLB电连接；RRAM3的底部电极与NMOS晶体管M4的漏极电连接；M4的栅极与WLS电连接；NMOS晶体管M1的源极、RRAM2的底部电极、NMOS晶体管M4的源极均与SL和电阻R1电连接，而电阻R1的另一端接地。本发明采用RRAM实现了在内存内计算中基本的逻辑运算，提高了电路的逻辑运算效率。
The present invention discloses a 4T3R circuit structure for implementing high-speed logic operations based on resistive random access memory (RRAM), comprising: a bottom electrode of RRAM1 electrically connected to the drain of NMOS transistor M1 and the drain of NMOS transistor M2; a gate of M1 electrically connected to WLA; a gate of M2 electrically connected to WLC; a source of NMOS transistor M2 and a source of NMOS transistor M3 electrically connected to the top electrode of RRAM2; a gate of NMOS transistor M3 electrically connected to WLB; a bottom electrode of RRAM3 electrically connected to the drain of NMOS transistor M4; a gate of M4 electrically connected to WLS; a source of NMOS transistor M1, a bottom electrode of RRAM2, and a source of NMOS transistor M4 electrically connected to SL and a resistor R1, with the other end of resistor R1 being grounded. The present invention uses RRAM to implement basic logic operations in in-memory computing, thereby improving the logic operation efficiency of the circuit.
Description
Technical Field
The invention relates to the technical field of resistance change memories (RESISTIVE RANDOM ACCESS MEMORY, RRAM), in particular to a 4T3R circuit structure for realizing high-speed logic operation based on the resistance change memories.
Background
In recent years, artificial intelligence algorithms have been rapidly developed, and have demonstrated significant performance advantages in the fields of image processing, speech recognition, and the like. In a traditional von neumann-structured computer, the separation of the computing unit from the memory unit is an important factor that hinders the development of these applications. As the parallelism of computation increases, the bandwidth of the required data transfer limits the computation speed, commonly referred to as von neumann bottleneck. To overcome the drawbacks of these conventional von neumann architectures, in-memory calculations (computing in memory, CIM) have been developed. In-memory computing, a non-von neumann architecture, is considered one of the main trends in the future of artificial intelligence algorithm hardware acceleration. The cooperation of the memory unit and the logic unit is the key of hardware acceleration of the artificial intelligence algorithm. The separation of the storage unit and the logic unit in the traditional structure is abandoned, and the bandwidth limitation of data transmission is effectively avoided, so that the calculation speed of the circuit can be improved. In-memory computing theoretically has multiple working modes, and unlike traditional logic operation, in-memory computing uses the current storage state of a storage unit in the operation process. The actual working modes can be divided into 3 types, namely a mode 1, wherein the calculation result is related to the input and storage states, the result is directly output, a mode 2, wherein the calculation result is related to the input and storage states, the result is stored in a storage unit, and a mode 3, wherein the calculation result is related to the input and storage states, and the result is output and the storage state is updated at the same time. The in-memory computing technology breaks through the limitation of the traditional von neumann architecture, optimizes the structures of the memory unit and the logic unit, and relieves the problem of data handling, thereby obviously reducing the energy consumption.
Non-volatile memory devices are critical for in-memory computing to land. For non-volatile memory devices, such as NOR Flash, RRAM, and the like, analog storage, non-volatility, and low power consumption are all significant advantages, which is a core competitive embodiment of the in-memory computing scheme. In the category of non-volatile memories, the technology of NOR Flash as a memory is mature, and technological parameters, device models and module designs all have mature tools, so that an in-memory computing solution is realized first. In the future, the core design of the system architecture of the NOR Flash can be migrated to novel nonvolatile devices such as RRAM and the like, so that the technical iterative innovation and product continuation can be realized. However, in the prior art, the logic operation efficiency of the in-memory computing circuit implemented by using the RRAM is low, and improvement is needed.
In view of this, the present invention has been made.
Disclosure of Invention
The invention aims to provide a 4T3R circuit structure for realizing high-speed logic operation based on a resistance change type memory, so as to solve the technical problems in the prior art. The invention adopts RRAM to realize basic logic operation in memory internal calculation, and improves the logic operation efficiency of the circuit.
The invention aims at realizing the following technical scheme:
A4T 3R circuit structure for realizing high-speed logic operation based on resistance-change memories comprises 4 NMOS transistors, 3 resistance-change memories and 1 resistor R1, wherein the 4 NMOS transistors are respectively defined as M1, M2, M3 and M4, the 3 resistance-change memories are respectively defined as RRAM1, RRAM2 and RRAM3, the arrangement directions of the resistance-change memories RRAM1, RRAM2 and RRAM3 are the same, the top electrode is upward, the bottom electrode is downward, the bottom electrode of the resistance-change memory RRAM1 is electrically connected with the drain electrode of the NMOS transistor M1 and the drain electrode of the NMOS transistor M2, the grid electrode of the NMOS transistor M1 is electrically connected with a signal line WLA, the grid electrode of the NMOS transistor M2 is electrically connected with a signal line WLC, the source electrode of the NMOS transistor M2 and the source electrode of the NMOS transistor M3 are electrically connected with the top electrode of the resistance-change memory RRAM2, the grid electrode of the NMOS transistor M3 is electrically connected with the signal line WLB, the bottom electrode of the NMOS transistor RRAM3 and the drain electrode of the NMOS transistor M4 is connected with the drain electrode of the NMOS transistor 1 and the drain electrode of the NMOS transistor 1 is connected with the drain electrode of the NMOS transistor 1.
Preferably, at least one of the following logical operations of the circuit structure can be implemented by controlling on and off of the NMOS transistors M1, M2, M3, M4 through the signal lines WLA, WLC, WLB, WLS, respectively:
(1) By opening WLA and WLB and turning off WLC, the parallel connection of the resistance change type memory RRAM1 and the resistance change type memory RRAM2 is realized, so that OR operation of the circuit structure is realized;
(2) By turning off WLA and WLB and turning on WLC, the series connection of the resistance change type memory RRAM1 and the resistance change type memory RRAM2 is realized, thereby realizing the AND operation of the circuit structure;
(3) By turning on WLA, WLB, and WLS and turning off WLC, parallel connection of the resistance change memory RRAM1 and the resistance change memory RRAM2 is realized, thereby realizing writing of the result of logical nor operation of the resistance change memory RRAM1 and the resistance change memory RRAM2 into the resistance change memory RRAM 3;
(4) By turning off WLA and WLB and turning on WLC and WLS, series connection of the resistance change memory RRAM1 and the resistance change memory RRAM2 is realized, thereby realizing writing of the result of logical nand operation of the resistance change memory RRAM1 and the resistance change memory RRAM2 into the resistance change memory RRAM 3;
(5) The serial connection of the resistive random access memory RRAM1 and the resistive random access memory RRAM2 is realized by turning off WLA and WLB and turning on WLC and WLS, so that the result of the logical NAND operation of the resistive random access memory RRAM1 and the resistive random access memory RRAM2 is written into the resistive random access memory RRAM3, and then the structure of the resistive random access memory RRAM1 and the resistive random access memory RRAM2 is connected in series with the resistive random access memory RRAM3 by turning on WLA, WLB and WLS and turning off WLC, so that the exclusive OR operation of the circuit structure is realized.
Preferably, the top electrode of the resistance change type memory RRAM1 is electrically connected to the signal line BLA, the drain of the NMOS transistor M3 is electrically connected to the signal line BLB, and the top electrode of the resistance change type memory RRAM3 is electrically connected to the signal line BL 0.
Compared with the prior art, the invention adopts 4 NMOS transistors, 3 resistance change memories and 1 resistor R1 to construct a 4T3R circuit structure, data is stored in the resistance change memories, then the on and off of the NMOS transistors M1, M2, M3 and M4 are respectively controlled through the signal line WLA, WLC, WLB, WLS, and further the series-parallel connection of the resistance change memories RRAM1, RRAM2 and RRAM3 is controlled, so that the 4T3R circuit structure can realize the basic logic operations such as OR operation, AND operation, NOR operation, NAND operation and XOR operation of a circuit in the internal memory calculation according to the characteristics of the RRAM high resistance state and low resistance state, and finally the stored data is read out, thereby improving the logic operation efficiency of the data.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed in the description of the embodiments will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of the overall structure of a 4T3R circuit structure for implementing high-speed logic operation based on a resistance variable memory according to an embodiment of the present invention;
FIG. 2 is a block diagram of a NAND circuit for writing RRAM3, as used in an embodiment of the invention;
FIG. 3 is a diagram of a circuit configuration during a write NAND circuit breaker according to an embodiment of the present invention;
FIG. 4 is a diagram of a nor circuit for writing RRAM3 used in an embodiment of the invention;
FIG. 5 is a timing diagram of the operation of an example of the present invention;
FIG. 6 is a diagram of simulation results of resistance states of a non-RRAM provided by an example of the invention;
fig. 7 is a diagram of the resistive state and the exclusive or output simulation result of the RRAM provided by the example of the present invention.
Detailed Description
The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are only some embodiments of the present invention, not all embodiments of the present invention, and this is not limiting to the present invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to fall within the scope of the invention.
The terms that may be used herein will first be described as follows:
The terms "comprises," "comprising," "includes," "including," "has," "having" or other similar referents are to be construed to cover a non-exclusive inclusion. For example, inclusion of a feature (e.g., a starting material, component, ingredient, carrier, dosage form, material, size, part, component, mechanism, apparatus, step, procedure, method, reaction condition, processing condition, parameter, algorithm, signal, data, product or article of manufacture, etc.) should be construed as including not only the feature explicitly recited, but also other features known in the art that are not explicitly recited.
The following describes the structure of the 4T3R circuit for realizing high-speed logic operation based on the resistance variable memory. What is not described in detail in the present invention belongs to the prior art known to those skilled in the art. The specific conditions are not noted in the examples of the present invention and are carried out according to the conditions conventional in the art or suggested by the manufacturer. The reagents or apparatus used in the examples of the present invention were conventional products commercially available without the manufacturer's knowledge.
Example 1
As shown in fig. 1 to 7, embodiment 1 of the present invention provides a 4T3R circuit structure for implementing high-speed logic operation based on a resistance variable memory, which is a circuit structure for implementing high-speed logic operation by using RRAM in-memory computation, and includes 4 NMOS transistors, 3 resistance variable memories and 1 resistor R1, wherein the 4 NMOS transistors are respectively defined as M1, M2, M3 and M4, and the 3 resistance variable memories are respectively defined as RRAM1, RRAM2 and RRAM3.
The resistive random access memory RRAM1, the resistive random access memory RRAM2 and the resistive random access memory RRAM3 are arranged in the same direction, and the top electrode is upward and the bottom electrode is downward.
The bottom electrode of the resistance change memory RRAM1 is electrically connected to the drain of the NMOS transistor M1 and the drain of the NMOS transistor M2, the gate of the NMOS transistor M1 is electrically connected to the signal line WLA, and the gate of the NMOS transistor M2 is electrically connected to the signal line WLC.
The source of the NMOS transistor M2 and the source of the NMOS transistor M3 are electrically connected to the top electrode of the resistance change memory RRAM2, and the gate of the NMOS transistor M3 is electrically connected to the signal line WLB.
The bottom electrode of the resistance change memory RRAM3 is electrically connected to the drain of the NMOS transistor M4, and the gate of the NMOS transistor M4 is electrically connected to the signal line WLS.
The source of the NMOS transistor M1, the bottom electrode of the resistance change memory RRAM2, and the source of the NMOS transistor M4 are all electrically connected to the signal line SL, and are also all electrically connected to one end of the resistor R1, while the other end of the resistor R1 is grounded.
The top electrode of the resistance change memory RRAM1 is electrically connected to the signal line BLA, the drain of the NMOS transistor M3 is electrically connected to the signal line BLB, and the top electrode of the resistance change memory RRAM3 is electrically connected to the signal line BL 0.
Specifically, in this 4T3R circuit structure, at least one of the following logical operations of the circuit structure can be realized by controlling on and off of the NMOS transistors M1, M2, M3, and M4 by the signal lines WLA, WLC, WLB, and WLS, respectively:
(1) By turning on WLA and WLB and turning off WLC, parallel connection of the resistance change memory RRAM1 and the resistance change memory RRAM2 is realized, thereby realizing or operation of the circuit structure.
(2) By turning off WLA and WLB and turning on WLC, series connection of the resistance change memory RRAM1 and the resistance change memory RRAM2 is realized, thereby realizing and operation of the circuit structure.
(3) By turning on WLA, WLB, and WLS and turning off WLC, parallel connection of the resistance change memory RRAM1 and the resistance change memory RRAM2 is realized, thereby realizing writing of the result of logical nor operation of the resistance change memory RRAM1 and the resistance change memory RRAM2 into the resistance change memory RRAM 3.
(4) By turning off WLA and WLB and turning on WLC and WLS, series connection of the resistance change memory RRAM1 and the resistance change memory RRAM2 is realized, thereby realizing writing of the result of the logical nand operation of the resistance change memory RRAM1 and the resistance change memory RRAM2 into the resistance change memory RRAM 3.
(5) The serial connection of the resistive random access memory RRAM1 and the resistive random access memory RRAM2 is realized by turning off WLA and WLB and turning on WLC and WLS, so that the result of the logical NAND operation of the resistive random access memory RRAM1 and the resistive random access memory RRAM2 is written into the resistive random access memory RRAM3, and then the structure of the resistive random access memory RRAM1 and the resistive random access memory RRAM2 is connected in series with the resistive random access memory RRAM3 by turning on WLA, WLB and WLS and turning off WLC, so that the exclusive OR operation of the circuit structure is realized.
Further, the whole process of performing two basic logic operations by using the 4T3R circuit structure for implementing high-speed logic operations based on the resistance change memory provided in embodiment 1 of the present invention is fully described by way of the following examples, and the feasibility of the present invention is verified by using a simulation diagram:
The 4T3R circuit structure for realizing high-speed logic operation based on the resistance change memory provided by the embodiment 1 of the invention can be realized by the working principle of RRAM, when RRAM is connected in parallel, if and only if both RRAM are in a High Resistance State (HRS) circuit and are not conducted, and when RRAM is connected in series, if and only if both RRAM are in a Low Resistance State (LRS) circuit and are conducted.
And (one) the whole process and simulation of exclusive OR logic operation:
As shown in fig. 1, a basic circuit configuration diagram of embodiment 1 of the present invention is shown. The High Resistance State (HRS) of RRAM is defined as 0 and the Low Resistance State (LRS) is defined as 1. In the period a, the gate voltage of the NMOS transistor M1 is set to Vh by the signal line WLA, the gate voltage of the NMOS transistor M3 is set to Vh by the signal line WLB, the gate voltage of the NMOS transistor M4 is set to Vh by the signal line WLS, and in the period B, the gate voltage of the NMOS transistor M4 is set to VL by the signal line WLS, so that (VL-VR) =vgs < Vth is satisfied after the circuit is turned on, and WLS is sufficiently turned off.
In the period a, a logic value is written into the resistance change memories RRAM1 and RRAM2, and the resistance change memory RRAM3 is initialized to a High Resistance State (HRS).
Turning on WLA and WLB, turning off WLC and WLS, applying Vset voltage at BLA and BLB terminals, setting SL voltage to 0, setting resistance change memories RRAM1 and RRAM2 to Low Resistance State (LRS), namely resistance change memories RRAM1 and RRAM2 constitute logic value 11.
WLA, WLB and WLC are turned off, WLS is turned on, vreset voltage is applied at the SL terminal, BL0 is set to 0, and resistance change memory RRAM3 is reset to a High Resistance State (HRS).
In the period B, as shown in fig. 2, the circuit structure is turned on, WLA and WLB are turned off, WLC and WLS are turned on, a lower VL gate voltage needs to be applied to WLS in the present period, VR voltage is applied to the WLA terminal, and a short Vset voltage is applied at the end of the present period, which enables series connection of resistive random access memory RRAM1 and resistive random access memory RRAM 2.
When the resistance change memory RRAM1 and the resistance change memory RRAM2 are both in a low resistance state (i.e., the resistance change memory RRAM1 and the resistance change memory RRAM2 form a logic value 11), the circuit is turned on, so that the source voltage of the WLS is raised to turn off the WLS, and the resistance change memory RRAM3 is kept in a High Resistance State (HRS), thus forming a circuit path structure as shown in fig. 3.
When at least one of the resistive memory RRAM1 and the resistive memory RRAM2 is in a high resistance state (i.e., the resistive memory RRAM1 and the resistive memory RRAM2 form a logic value of 00, 01 or 10), the circuit is not conductive, which sets the resistive memory RRAM3 to a Low Resistance State (LRS).
By the above operation, it is possible to perform a nand operation on the logic values written into the resistance change memories RRAM1 and RRAM2 and write the result of the nand operation into the resistance change memory RRAM3, the simulation result of which is the resistance change memory RRAM3 resistance state shown in fig. 6.
And in the period C, by opening WLA, WLB and WLS and turning off WLC, the resistance change type memory RRAM1 and the resistance change type memory RRAM2 are connected in parallel and then connected in series with the resistance change type memory RRAM3, so that the exclusive OR operation of the circuit structure is realized. The exclusive OR operation is completed and the current I2t is detected at BL0 as shown in FIG. 7.
WLA, WLB and WLS are turned on, WLC is turned off, and a read voltage Vr is applied at BLA and BLB. The period of each logic operation is divided into three periods, namely a period A, a period B and a period C. The period a completes the state writing to the resistance change memory RRAM1 and the resistance change memory RRAM2, the period B completes the state writing to the resistance change memory RRAM3, and the period C completes the output of the exclusive or result.
When the logic 1 is written into the resistance change memory RRAM1 and the resistance change memory RRAM2 in the period A, the resistance change memory RRAM3 is kept to be in a High Resistance State (HRS) in the period B, the read voltage is applied in the period C, the circuit is not conducted, and the BL0 end detects that the output current is logic 0.
When a logic 1 is written into the resistance change memory RRAM1 and a logic 0 is written into the resistance change memory RRAM2 in the period A, the resistance change memory RRAM3 is in a Low Resistance State (LRS) in the period B, the read voltage is applied in the period C at BLA, the circuit is conducted, and the detection output current at the BL0 end is logic 1.
When the logic 0 is written into the resistance change memory RRAM1 and the resistance change memory RRAM2 in the period A, the resistance change memory RRAM3 is written into the Low Resistance State (LRS) in the period B, the read voltage is applied in the period C, the circuit is not conducted, and the BL0 end detects that the output current is logic 0.
When writing logic 0 into the resistance change memory RRAM1 and logic 1 into the resistance change memory RRAM2 in the period A, writing the resistance change memory RRAM3 into the Low Resistance State (LRS) in the period B, applying a read voltage in the period C at BLA, conducting a circuit, and detecting that the output current is logic 1 at the BL0 end.
The exclusive or operation of the circuit can be realized by the above operation, and the output result can be detected at the BL0 end, and the simulation result and the input timing are as shown in fig. 5.
(II) the whole process of nor logic operation and simulation:
In the period a, a logic value is written into the resistance change memory RRAM1 and the resistance change memory RRAM2, and the resistance change memory RRAM3 is initialized to a High Resistance State (HRS).
Turning on WLA and WLB, turning off WLC and WLS, applying Vset voltage at BLA and BLB terminals, setting SL voltage to 0, setting resistance change memories RRAM1 and RRAM2 to Low Resistance State (LRS), namely resistance change memories RRAM1 and RRAM2 constitute logic value 11.
WLA, WLB and WLC are turned off, WLS is turned on, vreset voltage is applied at the SL terminal, BL0 is set to 0, and resistance change memory RRAM3 is reset to a High Resistance State (HRS).
In the period B, as in the on circuit structure shown in fig. 4, WLA, WLB, and WLS are turned on, WLC is turned off, parallel connection of the resistance change memory RRAM1 and the resistance change memory RRAM2 is realized, and thus writing of the result of logical nor operation of the resistance change memory RRAM1 and the resistance change memory RRAM2 into the resistance change memory RRAM3 is realized.
Turning on WLA, WLB and WLS, turning off WLC requires applying a lower VL voltage to WLS during this period. The VR voltage is applied at the WLA terminal and a brief Vset voltage is applied at the end of the current period.
When the resistance change memory RRAM1 and the resistance change memory RRAM2 are both in a high resistance state (i.e., the resistance change memory RRAM1 and the resistance change memory RRAM2 form a logic value of 00), the circuit is not conductive, so that the source voltage of WLS is raised to turn off WLS, and the resistance change memory RRAM3 is set in a Low Resistance State (LRS).
When at least one of the resistive random access memory RRAM1 and the resistive random access memory RRAM2 is in a low resistance state (i.e. the resistive random access memory RRAM1 and the resistive random access memory RRAM2 form logic values 01, 10 or 11), the circuit is conducted, so that the resistive random access memory RRAM1 maintains a High Resistance State (HRS).
The nor operation of the circuit can be realized by the above operation, and the operation result is saved in the RRAM 3.
In summary, the embodiment of the invention adopts RRAM to realize basic logic operation in internal memory calculation, and improves the logic operation efficiency of the circuit.
The foregoing is only a preferred embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions easily contemplated by those skilled in the art within the scope of the present invention should be included in the scope of the present invention. Therefore, the protection scope of the present invention should be subject to the protection scope of the claims. The information disclosed in the background section herein is only for enhancement of understanding of the general background of the invention and is not to be taken as an admission or any form of suggestion that this information forms the prior art already known to those of ordinary skill in the art.
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| CN112802515A (en) * | 2021-01-21 | 2021-05-14 | 中国科学院微电子研究所 | Three-state spin electronic device, storage unit, storage array and read-write circuit |
| CN113590082A (en) * | 2021-06-28 | 2021-11-02 | 杭州电子科技大学 | Three-value memory resistance full adder circuit based on character operation |
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| WO2019147522A2 (en) * | 2018-01-23 | 2019-08-01 | Anaflash Inc. | Neural network circuits having non-volatile synapse arrays |
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| CN113590082A (en) * | 2021-06-28 | 2021-11-02 | 杭州电子科技大学 | Three-value memory resistance full adder circuit based on character operation |
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