CN114385379B - Method, system, terminal and storage medium for detecting on-board information refreshing - Google Patents

Abstract

The invention relates to the technical field of servers, and particularly provides a method, a system, a terminal and a storage medium for detecting on-board information refreshing, which comprise the following steps: identifying the firmware of the target hardware and a first cache and a second cache for refreshing the on-board information, and setting the first cache as a valid cache; after the on-board information is written, resetting the firmware and switching the effective cache into a second cache; and reading actual on-board information in target hardware, and comparing the consistency of the actual on-board information and the updated on-board information. According to the invention, by setting two caches, after the on-board information is written, the hardware switching cache is reset, the on-board information is written into the hardware, and after the cache is switched, the on-board information written into the hardware is directly read, so that the on-board information is detected. The invention saves the time of one-time startup and shutdown, reduces the time cost and improves the detection efficiency of the on-board information.

Description

Onboard information flash detection method, system, terminal and storage medium

Technical field

The invention relates to the field of server technology, and specifically to an onboard information rewriting detection method, system, terminal and storage medium.

Background technique

With the development of PCBA technology, there is an increasingly strong demand for carrying board information directly on the hardware. The board information is written on the hardware and then read out through software. The whole process before the server is shipped It is very convenient during machine testing and customer use. Currently, after the onboard information is flashed, the onboard information is not written to the hardware immediately, but is first written to the cache. It needs to be powered off to write to the real hardware. If you want to check whether the board information is actually written, you need to power on again to check.

One of the existing technical solutions is not to check whether the onboard information is actually written. This method will cause the problematic board to flow out of the factory, which is a hidden danger for quality control. The other method is to turn off the power and then power it on again. Check whether the onboard information is actually written. This method takes a long time to test and is costly. The tooling investment will also double under the same production capacity requirements.

Contents of the invention

In view of the above-mentioned deficiencies of the prior art, the present invention provides an onboard information rewriting detection method, system, terminal and storage medium to solve the above-mentioned technical problems.

In a first aspect, the present invention provides an onboard information rewriting detection method, which includes:

Identify the firmware of the target hardware and the first cache and the second cache used to flash onboard information, and set the first cache as a valid cache;

After flashing the onboard information, reset the firmware and switch the effective cache to the second cache;

Read the actual onboard information in the target hardware, and compare the consistency between the actual onboard information and the flashed onboard information.

Further, after flashing the onboard information, reset the firmware and switch the effective cache to the second cache, including:

Scan the onboard information of the board and flash the onboard information to the target hardware;

Read the currently valid cached information and cache the information as the initial valid cached information;

Execute the reset command and switch the effective cache during the reset process;

Re-read the valid cache information, and compare the consistency of the re-read valid cache information with the initial effective cache information. If the two are inconsistent, it is determined that the cache switch is successful.

Further, read the actual onboard information in the target hardware and compare the consistency between the actual onboard information and the flashed onboard information, including:

After scanning the onboard information, caching the onboard information as initial onboard information;

Read the actual onboard information in the target hardware, read the initial onboard information from the specified cache address, compare the consistency of the actual onboard information and the initial onboard information, and determine the onboard information if they are consistent. Flashing successful.

In a second aspect, the present invention provides an onboard information rewriting detection system, including:

A target identification unit, used to identify the firmware of the target hardware and the first cache and the second cache used to refresh the onboard information, and set the first cache as a valid cache;

A flash execution unit, configured to reset the firmware and switch the effective cache to the second cache after flashing the onboard information;

The flash verification unit is used to read the actual onboard information in the target hardware and compare the consistency of the actual onboard information with the flashed onboard information.

Further, the flash execution unit includes:

The board scanning module is used to scan the onboard information of the board and flash the onboard information to the target hardware;

The cache reading module is used to read the currently valid cached information and cache the information as the initial valid cached information;

The reset execution module is used to execute the reset command and switch the effective cache during the reset process;

The switching verification module is used to re-read the effective cache information and compare the consistency of the re-read effective cache information with the initial effective cache information. If the two are inconsistent, it is determined that the cache switch is successful.

Further, the flash verification unit includes:

An initial cache module, configured to cache the onboard information as initial onboard information after scanning the onboard information;

The flash verification module is used to read the actual onboard information in the target hardware, read the initial onboard information from the specified cache address, and compare the consistency of the actual onboard information with the initial onboard information. If If the two are consistent, it is determined that the onboard information is successfully written.

In the third aspect, a terminal is provided, including:

processor, memory, where,

This memory is used to store computer programs,

The processor is used to call and run the computer program from the memory, so that the terminal executes the above terminal method.

In a fourth aspect, a computer storage medium is provided. The computer-readable storage medium stores instructions, which when run on a computer, cause the computer to perform the methods described in the above aspects.

The beneficial effect of the present invention is that the onboard information flash detection method, system, terminal and storage medium provided by the present invention set up two caches, and after the onboard information is flashed, the onboard information is switched to the cache by resetting the hardware. Write to the hardware, and directly read the onboard information written to the hardware after switching caches to detect the onboard information. The invention saves the time of turning on and off the machine once, reduces the time cost, and improves the detection efficiency of onboard information.

In addition, the design principle of the invention is reliable, the structure is simple, and it has very broad application prospects.

Description of drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those of ordinary skill in the art, It is said that other drawings can also be obtained based on these drawings without exerting creative work.

Figure 1 is a schematic flow chart of a method according to an embodiment of the present invention.

Figure 2 is a schematic block diagram of a system according to an embodiment of the present invention.

Figure 3 is a schematic structural diagram of a terminal provided by an embodiment of the present invention.

Detailed ways

In order to enable those skilled in the art to better understand the technical solutions in the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described The embodiments are only some of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts should fall within the scope of protection of the present invention.

Key terms appearing in the present invention are explained below.

BMC, the execution server remote management controller, the English full name is Baseboard ManagementController. It is the baseboard management controller. It can upgrade the firmware of the machine, check the machine equipment, and other operations when the machine is not turned on. Full implementation of IPMI functionality in the BMC requires a powerful 16-bit or 32-bit microcontroller as well as RAM for data storage, flash memory and firmware for non-volatile data storage, and secure remote restart. , safe power cycle, LAN warning and system health monitoring can provide basic remote manageability. In addition to basic IPMI functions and system operation monitoring functions, mBMC can also enable BIOS fast component selection and protection by utilizing one of the two flash memories to store the previous BIOS. For example, when the system cannot boot after a remote BIOS upgrade, the remote administrator can switch back to the previously working BIOS image to boot the system. Once the BIOS is upgraded, the BIOS image can also be locked to effectively prevent viruses from invading it.

Figure 1 is a schematic flow chart of a method according to an embodiment of the present invention. Among them, the execution subject in Figure 1 can be an onboard information flash detection system.

As shown in Figure 1, the method includes:

Step 110: Identify the firmware of the target hardware and the first cache and the second cache used to flash onboard information, and set the first cache as a valid cache;

Step 120, after flashing the onboard information, reset the firmware and switch the effective cache to the second cache;

Step 130: Read the actual onboard information in the target hardware, and compare the consistency between the actual onboard information and the flashed onboard information.

In order to facilitate the understanding of the present invention, the onboard information flash detection method provided by the present invention will be further described below based on the principle of the onboard information flash detection method of the present invention and the process of detecting onboard information flash in the embodiment. describe.

Specifically, the onboard information flash detection method includes:

S1. Identify the firmware of the target hardware and the first cache and the second cache used for flashing onboard information, and set the first cache as a valid cache.

Set up two non-volatile memories (flash), which are the first cache and the second cache. It is pre-identified whether the firmware and the first cache and the second cache are in place, and if not, an alarm message is generated.

S1. After flashing the onboard information, reset the firmware and switch the effective cache to the second cache.

The first cache is set as a valid cache, and the number of the first cache is written into the storage path of the valid cache information.

The board is powered on normally and tested, and the onboard information is flashed. At this time, the flashed information is in the first cache and has not been written to the board hardware. The specific process of flashing the onboard information is: install the RISER card and start the test, scan the PN/QN information of the board; flash the PN/QN information in the FRU information of the RISER card through the BMC.

Execute ipmitool mc reset cold to reset the BMC to complete the switching of different flashes, that is, switch the effective cache from the first cache to the second cache, and read the effective cache information (i.e., the second cache number) and the first cache under the storage path again. If the numbers are inconsistent, the switch is successful; otherwise, the switch fails. The onboard information in the first cache is written to the hardware while switching the active cache.

S3. Read the actual onboard information in the target hardware, and compare the consistency of the actual onboard information with the flashed onboard information.

After scanning the onboard information, cache the onboard information as the initial onboard information; read the actual onboard information in the target hardware, read the initial onboard information from the specified cache address, and compare it with the actual onboard information. The consistency between the onboard information and the initial onboard information is determined. If the two are consistent, the onboard information flashing is successful. If the two are inconsistent, the onboard information flashing failure is determined, and the detection results are output to the detection log.

As shown in Figure 2, the system 200 includes:

The target identification unit 210 is used to identify the firmware of the target hardware and the first cache and the second cache for flashing the onboard information, and set the first cache as a valid cache;

The flash execution unit 220 is configured to reset the firmware and switch the effective cache to the second cache after flashing the onboard information;

The flash verification unit 230 is used to read the actual onboard information in the target hardware and compare the consistency of the actual onboard information with the flashed onboard information.

Optionally, as an embodiment of the present invention, the flash execution unit includes:

The board scanning module is used to scan the onboard information of the board and flash the onboard information to the target hardware;

The cache reading module is used to read the currently valid cached information and cache the information as the initial valid cached information;

The reset execution module is used to execute the reset command and switch the effective cache during the reset process;

The switching verification module is used to re-read the effective cache information and compare the consistency of the re-read effective cache information with the initial effective cache information. If the two are inconsistent, it is determined that the cache switch is successful.

Optionally, as an embodiment of the present invention, the flash verification unit includes:

An initial cache module, configured to cache the onboard information as initial onboard information after scanning the onboard information;

The flash verification module is used to read the actual onboard information in the target hardware, read the initial onboard information from the specified cache address, and compare the consistency of the actual onboard information with the initial onboard information. If If the two are consistent, it is determined that the onboard information is successfully written.

FIG. 3 is a schematic structural diagram of a terminal 300 provided by an embodiment of the present invention. The terminal 300 can be used to perform the onboard information flash detection method provided by an embodiment of the present invention.

The terminal 300 may include: a processor 310, a memory 320, and a communication unit 330. These components communicate through one or more buses. Those skilled in the art can understand that the structure of the server shown in the figure does not limit the invention. It can be a bus structure, a star structure, or More or fewer components may be included than shown, or certain components may be combined, or may be arranged differently.

Among them, the memory 320 can be used to store execution instructions of the processor 310. The memory 320 can be implemented by any type of volatile or non-volatile storage terminals or their combination, such as static random access memory (SRAM), electronic Erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic or optical disk . When the execution instructions in the memory 320 are executed by the processor 310, the terminal 300 is enabled to perform some or all of the steps in the following method embodiments.

The processor 310 is the control center of the storage terminal, using various interfaces and lines to connect various parts of the entire electronic terminal, by running or executing software programs and/or modules stored in the memory 320, and calling data stored in the memory, To perform various functions of the electronic terminal and/or process data. The processor may be composed of an integrated circuit (IC for short), for example, it may be composed of a single packaged IC, or it may be composed of multiple packaged ICs connected with the same function or different functions. For example, the processor 310 may only include a central processing unit (Central Processing Unit, CPU for short). In the embodiment of the present invention, the CPU may be a single computing core or may include multiple computing cores.

The communication unit 330 is used to establish a communication channel so that the storage terminal can communicate with other terminals. Receive user data sent by other terminals or send user data to other terminals.

The present invention also provides a computer storage medium, wherein the computer storage medium can store a program, and when executed, the program can include some or all of the steps in the embodiments provided by the present invention. The storage medium may be a magnetic disk, an optical disk, a read-only memory (ROM) or a random access memory (RAM), etc.

Therefore, the present invention sets two caches, resets the hardware switching cache after flashing the onboard information, writes the onboard information to the hardware, and directly reads the onboard information written to the hardware after switching the cache to thereby perform the onboard processing of the board. Load information for testing. The present invention saves the time of turning on and off the machine once, reduces the time cost, and improves the detection efficiency of onboard information. The technical effects achieved by this embodiment can be found in the above description, and will not be described again here.

Those skilled in the art can clearly understand that the technology in the embodiments of the present invention can be implemented by means of software plus the necessary general hardware platform. Based on this understanding, the technical solutions in the embodiments of the present invention can be embodied in the form of software products in essence or in part that contribute to the existing technology. The computer software products are stored in a storage medium such as a USB flash drive or mobile phone. Hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), magnetic disk or optical disk and other media that can store program code, including a number of instructions to make a computer terminal (It can be a personal computer, a server, or a second terminal, a network terminal, etc.) to perform all or part of the steps of the methods described in various embodiments of the present invention.

The same and similar parts among the various embodiments in this specification can be referred to each other. In particular, for the terminal embodiment, since it is basically similar to the method embodiment, the description is relatively simple. For relevant details, please refer to the description in the method embodiment.

In the several embodiments provided by the present invention, it should be understood that the disclosed systems and methods can be implemented in other ways. For example, the system embodiments described above are only illustrative. For example, the division of the units is only a logical function division. In actual implementation, there may be other division methods. For example, multiple units or components may be combined or can be integrated into another system, or some features can be ignored, or not implemented. On the other hand, the coupling or direct coupling or communication connection between each other shown or discussed may be through some interfaces, indirect coupling or communication connection of the system or unit, which may be in electrical, mechanical or other forms.

The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place, or they may be distributed to multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

In addition, each functional unit in various embodiments of the present invention can be integrated into one processing unit, or each unit can exist physically alone, or two or more units can be integrated into one unit.

Although the present invention has been described in detail with reference to the accompanying drawings in conjunction with preferred embodiments, the present invention is not limited thereto. Without departing from the spirit and essence of the invention, those of ordinary skill in the art can make various equivalent modifications or substitutions to the embodiments of the invention, and these modifications or substitutions should be within the scope of the invention/any Those skilled in the art can easily think of changes or substitutions within the technical scope disclosed in the present invention, and they should all be covered by the protection scope of the present invention. Therefore, the protection scope of the present invention should be determined by the protection scope of the claims.

Claims (6)

1. A method for detecting onboard information flash writing, which is characterized by including: Identify the firmware of the target hardware and the first cache and the second cache used to flash onboard information, and set the first cache as a valid cache; After flashing the onboard information, reset the firmware and switch the effective cache to the second cache; Read the actual onboard information in the target hardware, and compare the consistency of the actual onboard information with the flashed onboard information; After flashing the onboard information, reset the firmware and switch the effective cache to the second cache, including: Scan the onboard information of the board and flash the onboard information to the target hardware; Read the currently valid cached information and cache the information as the initial valid cached information; Execute the reset command and switch the effective cache during the reset process; Re-read the valid cache information, and compare the consistency of the re-read valid cache information with the initial effective cache information. If the two are inconsistent, it is determined that the cache switch is successful. 2. The method according to claim 1, characterized in that reading the actual onboard information in the target hardware and comparing the consistency between the actual onboard information and the flashed onboard information includes: After scanning the onboard information, caching the onboard information as initial onboard information; Read the actual onboard information in the target hardware, read the initial onboard information from the specified cache address, compare the consistency of the actual onboard information and the initial onboard information, and determine the onboard information if they are consistent. Flashing successful. 3. An onboard information flash detection system, characterized by including: A target identification unit, used to identify the firmware of the target hardware and the first cache and the second cache for flashing the onboard information, and set the first cache as a valid cache; A flash execution unit, configured to reset the firmware and switch the effective cache to the second cache after flashing the onboard information; The flash verification unit is used to read the actual onboard information in the target hardware and compare the consistency of the actual onboard information with the flashed onboard information; The flash execution unit includes: The board scanning module is used to scan the onboard information of the board and flash the onboard information to the target hardware; The cache reading module is used to read the currently valid cached information and cache the information as the initial valid cached information; The reset execution module is used to execute the reset command and switch the effective cache during the reset process; The switching verification module is used to re-read the effective cache information and compare the consistency of the re-read effective cache information with the initial effective cache information. If the two are inconsistent, it is determined that the cache switch is successful. 4. The system according to claim 3, characterized in that the flash verification unit includes: An initial cache module, configured to cache the onboard information as initial onboard information after scanning the onboard information; The flash verification module is used to read the actual onboard information in the target hardware, read the initial onboard information from the specified cache address, and compare the consistency of the actual onboard information with the initial onboard information. If If the two are consistent, it is determined that the onboard information is successfully written. 5. A terminal, characterized in that it includes: processor; Memory used to store instructions for execution by the processor; Wherein, the processor is configured to perform the method according to any one of claims 1-2. 6. A computer-readable storage medium storing a computer program, characterized in that when the program is executed by a processor, the method according to any one of claims 1-2 is implemented.