CN114237715A - Multi-core memory access instruction verification system and method - Google Patents
Multi-core memory access instruction verification system and method Download PDFInfo
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Abstract
The invention relates to the technical field of processors, in particular to a multi-core memory access instruction verification system and a multi-core memory access instruction verification method. The invention supports the access instruction verification of multi-core multi-cluster, and the number of the cores and the clusters can be matched, thereby realizing parameterization and having expandability. The method supports the real-time comparison of the correctness of the execution of the access instruction of each core in a multi-core system, and comprises the steps of comparing the correctness of data obtained by access when the access instruction is submitted, and comparing the correctness of write data when a storage instruction updates the cache. The verification of atomic operation instructions in the multi-core system and the verification of a second-level cache key interface in the multi-cluster system are supported, and the method has a very strong market application prospect.
Description
Technical Field
The invention relates to the technical field of processors, in particular to a multi-core memory access instruction verification system and a multi-core memory access instruction verification method.
Background
The execution order of instructions in a processor can be divided into a program order and a global memory order, wherein the program order refers to the order of the instructions in a program, the global memory order refers to the order of the access instructions to be finally carried out by the instructions, for a load (access instruction), the time point of the execution is the time point at which load data can be determined, and for a store (store instruction), the time point of the execution is the time point at which the store data can be seen by other cores.
Different memory consistency models have different requirements on the execution sequence of the access instruction, a sequential consistency model has the most strict requirements, and global memory order is consistent with program order, but the performance of the multi-core system is often poor, and the actual multi-core system is added with load forward storage data, storage buffer and other designs to improve the performance, and the addition of the designs can make the requirements of the memory consistency model on the execution sequence of the access instruction loose, and the global memory order is not necessarily consistent with the program order, which brings great difficulty for multi-core verification, and the verification system must know the global memory order of the access instruction accurately to perform data comparison.
At present, no perfect tool in the market can carry out the access and storage instruction verification of the multi-core system. Therefore, a multi-core memory access instruction verification system and method are provided.
Disclosure of Invention
Aiming at the defects of the prior art, the invention discloses a multi-core memory access instruction verification system and a multi-core memory access instruction verification method, which are used for solving the problems that the multi-core system verification and design in the prior art are tightly coupled, and no tool can perfectly support the verification of the multi-core memory access instruction.
The invention is realized by the following technical scheme:
in a first aspect, the present invention provides a method for verifying a multi-core memory access instruction, including the following steps:
s1 the instruction generator generates an instruction, and judges the type of the instruction through the verification system, if the instruction is an access instruction, the access instruction is stored in an access instruction queue, and if the instruction is a storage instruction, the storage instruction is stored in a storage instruction queue;
s2 storing the instruction into the access instruction queue, updating the access instruction information in the DUT, and synchronously updating the access instruction information to the corresponding instruction in the access instruction queue;
s3 judging whether it is a cacheable address according to the address attribute, and executing the access instruction of the corresponding process or writing into the memory model according to the result;
s4, if the access instruction is received, monitoring the submission of the access instruction in the DUT, comparing the access data stored in the verification system with the access data obtained in the DUT, and outputting a comparison result;
and S5, if cache updating information in the DUT is monitored when the memory model is written, writing corresponding data in the storage buffer into the memory model, comparing the write data with the DUT write data, and outputting a comparison result.
Furthermore, in the method, after the instruction is stored in the access instruction queue, whether the instruction is a cacheable address is judged according to the address attribute, if the instruction is a non-cacheable address, the performance time point is a time point when the read request in the DUT is sent to the peripheral interface, and if the instruction is a cacheable address, the performance time point is a time point when the access instruction takes data from the primary cache.
Furthermore, in the method, if the address is a non-cacheable address, when a corresponding access request on the DUT peripheral interface is monitored, which core the request comes from is determined, an access instruction of the core in the verification system is executed, data is obtained from the memory model, and the data is retained for subsequent comparison.
Further, in the method, if the address is a cacheable address, when it is monitored that the instruction in the DUT obtains data, an access instruction of the core in the verification system is executed.
Furthermore, in the method, after the instruction is stored in the storage instruction queue, whether the instruction is a cacheable address is judged according to the address attribute, if the instruction is a non-cacheable address, the performance time point is a time point when the write request in the DUT is sent to the peripheral interface, and if the instruction is a cacheable address, the performance time point is a time point when the storage instruction is written into the cache from the storage buffer.
Furthermore, in the method, if the address is a non-cacheable address, when a corresponding write request on the DUT peripheral interface is monitored, which core the request comes from is determined, a storage instruction of the core in the verification system is executed, data is written into the memory model, write data is compared with DUT write data, and a comparison result is printed.
Furthermore, in the method, if the address is a cacheable address, whether the storage instruction in the DUT is submitted is monitored, and if the storage instruction is submitted, the information of the storage instruction, including the address, the data and the like, is stored in the storage register.
In a second aspect, the present invention provides a multi-core memory access instruction verification system, where the system is used for being executed by the multi-core memory access instruction verification method described in the first aspect, and includes
A DUT monitor for monitoring a DUT for critical signals to cause the verification system to perform corresponding operations based on the monitored DUT signals;
the access instruction queue is used for storing information of the access instruction, and storing the access instruction into the access instruction queue according to the type of the instruction after the instruction generator sends the instruction to the DUT and the verification system;
the storage instruction queue is used for storing information of storage instructions, and storing the storage instructions into the access instruction queue according to the types of the instructions after the instruction generator simultaneously sends the instructions to the DUT and the verification system;
the memory access instruction controller is used for controlling when the memory access instruction information in the verification system is updated, executing the operation of accessing the memory model and updating the memory model or comparing data, and refreshing a queue in the verification system for the behavior of a DUT (device under test) pipeline refreshing;
the storage buffer is used for verifying the storage of corresponding instructions in a storage instruction queue in the system, simultaneously writing corresponding data in the storage buffer into a memory model, and deleting corresponding instruction information in the storage buffer;
the memory model is used for verifying the memory model in the system, and the time point of accessing and updating the memory model by the access instruction is the time point of the access instruction performance;
the access data comparator is used for comparing the data obtained by the instruction in the verification system with the data obtained by the DUT when the access instruction is submitted, and printing a comparison result;
the storage data comparator is used for comparing the write data of the instruction in the verification system with the write data in the DUT and printing a comparison result when the DUT stores the instruction and updates the cache;
the atomic instruction comparator is used for verifying the correctness of the instruction with the atomic operation in the multi-core system;
and the second-level cache comparator is used for comparing the key interfaces of the second-level cache in the DUT and comparing whether the address and the data in the related interfaces are consistent with the data corresponding to the address in the memory template or not.
Furthermore, the DUT monitor monitors the key signals of the DUT, including the address data updating information of the access instruction, the instruction submission information, the store buffer updating information, the first-level cache updating information and the second-level cache key interface signals;
the atomic instruction comparator is used for comparing whether LRSC (low-rate register) instruction retrieval data are correct, whether the execution result of the SC instruction is successful or failed and whether the AMO instruction obtains the correct data;
the key interfaces of the second-level cache comparator for comparing the second-level cache in the DUT comprise a read request interface of the core and the second-level cache, a read request interface of the second-level cache and the next-level memory and a second-level cache monitoring interface.
Furthermore, in the access instruction queue, when the information such as the access instruction address, the attribute and the like in the DUT is updated, the corresponding instruction information in the queue is synchronously updated; when an access instruction in the DUT commits, the corresponding instruction in the queue is deleted.
In the storage instruction queue, when information such as storage instruction addresses, attributes, data and the like in the DUT is updated, corresponding instruction information in the queue is synchronously updated; when an access instruction in the DUT commits, the corresponding instruction in the queue is deleted and the instruction information is stored in the memory buffer.
The invention has the beneficial effects that:
the invention supports the access instruction verification of multi-core multi-cluster, and the number of the cores and the clusters can be matched, thereby realizing parameterization and having expandability.
The method supports real-time comparison of the correctness of the execution of the access instruction of each core in a multi-core system, and comprises the steps of comparing the correctness of data obtained by access when the access instruction is submitted, and comparing the correctness of write data when the storage instruction updates the cache.
The invention supports the verification of atomic operation instructions in a multi-core system, supports the verification of a second-level cache key interface in a multi-cluster system, and has strong market application prospect.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
FIG. 1 is a block diagram of a multi-core memory access instruction verification system according to an embodiment of the present invention;
FIG. 2 is a flow chart of the execution of the access instruction in the verification system according to the embodiment of the invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Example 1
Referring to fig. 1, the embodiment discloses a multi-core access instruction verification system including a DUT monitor, an access instruction queue, a storage instruction queue, an access instruction controller, a storage buffer, a memory model, an access data comparator, a storage data comparator, an atomic instruction comparator, and a secondary cache comparator, which are described below.
The DUT monitor of this embodiment is configured to monitor key signals of the DUT, including address data update information of a memory access instruction, instruction commit information, store buffer update information, first-level cache update information, second-level cache key interface signals, and the like. The verification system performs a corresponding operation based on the monitored DUT signal.
The embodiment accesses the instruction queue and is used for storing the information of the access instruction. The instruction generator simultaneously sends the instruction to the DUT and the verification system, and stores the access instruction into the access instruction queue according to the instruction type.
In a further implementation of this embodiment, when the information such as the address and the attribute of the access instruction in the DUT is updated, the corresponding instruction information in the queue is updated synchronously.
In a further implementation of this embodiment, when an access instruction in the DUT commits, the corresponding instruction in the queue is deleted.
The storage instruction queue is used for storing information of storage instructions. The instruction generator simultaneously sends instructions to the DUT and the verification system, and stores the storage instructions into the access instruction queue according to the instruction types.
In a further implementation of this embodiment, when the information of the storage instruction address, attribute, data, etc. in the DUT is updated, the corresponding instruction information in the queue is updated synchronously.
In a further implementation of this embodiment, when an access instruction in the DUT commits, the corresponding instruction in the queue is deleted and the instruction information is stored in the memory buffer.
The memory access instruction controller is used for controlling when the memory access instruction information in the verification system is updated, when the operations of accessing the memory model and updating the memory model are executed, and when data are compared.
In further implementations of this embodiment, the controller may need to flush the queue in the verification system for DUT pipeline flushing.
In the storage buffer of the embodiment, when the storage instruction in the DUT is submitted and then stored in the store buffer, the corresponding instruction in the storage instruction queue in the verification system is also stored in the storage buffer;
in a further implementation of this embodiment, when data in the DUT is written from the store buffer to the cache, corresponding data in the store buffer is also written to the memory model, and the corresponding instruction information in the store buffer is deleted.
In the memory model of this embodiment, each core verifies the memory model in the system, and each core has a read-write right, and a time point at which the memory access instruction accesses and updates the memory model is a time point of the memory access instruction performance. And only a memory model and no cache model exist in the verification system.
The embodiment of the invention has access to the data comparator, when the access instruction is submitted, the data obtained by the instruction in the verification system and the data obtained by the DUT are compared, and the comparison result is printed.
The storage data comparator of the embodiment compares write data of the instruction in the verification system with write data in the DUT when the DUT storage instruction updates the cache, and prints out a comparison result.
The atomic instruction comparator of the embodiment is used for verifying the correctness of an instruction with an atomic operation in a multi-core system.
In a further implementation of this embodiment, such as a Load-Reserved (Store-Conditional) LRSC instruction in the RISCV instruction set, an AMO instruction, the comparator is used to compare whether the LR instruction retrieves correct data, whether the SC instruction executes successfully or fails, and whether the AMO instruction retrieves correct data.
The second-level cache comparator of this embodiment is used for comparing critical interfaces of a second-level cache in the DUT, and includes a read request interface between a core and the second-level cache, a read request interface between the second-level cache and a next-level memory, and a second-level cache snoop interface, and mainly compares whether addresses and data in these interfaces are consistent with data corresponding to the addresses in the memory template.
The comparator can find the inconsistency of the verification system and the DUT data earlier without waiting for the comparator to report the error of the last access instruction, thereby greatly reducing the debug difficulty and shortening the debug time.
Example 2
In a specific implementation aspect, this embodiment provides an execution flow of an access instruction in the verification system, which is specifically as follows:
the instruction generator sends an instruction to the verification system, and if the instruction type is judged to be an access instruction, the instruction is stored in an access instruction queue;
monitoring the updating information of the access instruction in the DUT, including the information of address, attribute, access size and the like, and synchronously updating the updating information to the corresponding instruction in the access instruction queue;
judging whether the address is a cacheable address according to the address attribute, wherein the determination of a performance time point of the access instruction is influenced, if the address is a non-cacheable address, the performance time point is a time point when the read request in the DUT is sent to a peripheral interface, and if the address is a cacheable address, the performance time point is a time point when the access instruction takes data from a primary cache;
in this embodiment, if the address is a non-cacheable address, when a corresponding access request on the DUT peripheral interface is monitored, which core the request comes from is determined, an access instruction of the core in the verification system is executed, data is obtained from the memory model, and the data is retained for subsequent comparison;
in this embodiment, if the address is a cacheable address, when it is monitored that the instruction in the DUT obtains data, an access instruction of the core in the verification system is executed;
in this embodiment, for a cacheable address, since the access instruction is speculatively executed, data can be obtained from the storage instruction queue, the storage buffer and the memory model, and the access instruction controller needs to select data from a correct source, obtain the data, and store the data for subsequent comparison;
and when the access instruction in the DUT is monitored to be submitted, comparing the access data stored in the verification system with the access data obtained in the DUT, and printing a comparison result.
Example 3
In a specific implementation aspect, the embodiment provides an execution flow of a storage instruction in the verification system, which is specifically as follows:
the instruction generator sends an instruction to the verification system, and if the instruction type is judged to be a storage instruction, the instruction is stored in a storage instruction queue;
monitoring the storage instruction updating information in the DUT, including the information of address, attribute, write data, size and the like, and synchronously updating the storage instruction updating information to the corresponding instruction in the storage instruction queue;
judging whether the address is a cacheable address according to the address attribute, wherein the determination of the performance time point of the storage instruction is influenced, if the address is a non-cacheable address, the performance time point is the time point when the write request in the DUT is sent to the peripheral interface, and if the address is a cacheable address, the performance time point is the time point when the storage instruction is written into the cache from the storage cache;
in this embodiment, if the address is a non-cacheable address, when a corresponding write request on a DUT peripheral interface is monitored, which core the request comes from is determined, a storage instruction of the core in the verification system is executed, data is written into the memory model, write data is compared with DUT write data, and a comparison result is printed;
in this embodiment, if the address is a cacheable address, whether a storage instruction in the DUT is submitted is monitored, and if the storage instruction is submitted, information of the storage instruction, including an address, data, and the like, is stored in the storage buffer;
and monitoring cache updating information in the DUT, if the cache is updated, writing corresponding data in the storage buffer into the memory model, comparing write data with DUT write data, and printing a comparison result.
Example 4
The embodiment provides a method for verifying a multi-core memory access instruction, which is shown in fig. 2 and includes the following steps:
s1 the instruction generator generates an instruction, and judges the type of the instruction through the verification system, if the instruction is an access instruction, the access instruction is stored in an access instruction queue, and if the instruction is a storage instruction, the storage instruction is stored in a storage instruction queue;
s2 storing the instruction into the access instruction queue, updating the access instruction information in the DUT, and synchronously updating the access instruction information to the corresponding instruction in the access instruction queue;
s3 judging whether it is a cacheable address according to the address attribute, and executing the access instruction of the corresponding process or writing into the memory model according to the result;
s4, if the access instruction is received, monitoring the submission of the access instruction in the DUT, comparing the access data stored in the verification system with the access data obtained in the DUT, and outputting a comparison result;
and S5, if cache updating information in the DUT is monitored when the memory model is written, writing corresponding data in the storage buffer into the memory model, comparing the write data with the DUT write data, and outputting a comparison result.
In this embodiment, after the instruction is stored in the access instruction queue, it is determined whether the address is a cacheable address according to the address attribute, if the address is a non-cacheable address, the performance time point is a time point when the read request in the DUT is sent to the peripheral interface, and if the address is a cacheable address, the performance time point is a time point when the access instruction takes data from the primary cache.
In this embodiment, if the address is a non-cacheable address, when a corresponding access request on the DUT peripheral interface is monitored, which core the request comes from is determined, an access instruction of the core in the verification system is executed, data is obtained from the memory model, and the data is retained for subsequent comparison.
In this embodiment, if the address is a cacheable address, when it is detected that the instruction in the DUT obtains data, the access instruction of the core in the verification system is executed.
In this embodiment, after the instruction is stored in the storage instruction queue, it is determined whether the address is a cacheable address according to the address attribute, if the address is a non-cacheable address, the performance time point is a time point when the write request in the DUT is sent to the peripheral interface, and if the address is a cacheable address, the performance time point is a time point when the storage instruction is written from the storage buffer to the cache.
In this embodiment, if the address is a non-cacheable address, when a corresponding write request on the DUT peripheral interface is monitored, which core the request comes from is determined, a storage instruction of the core in the verification system is executed, data is written into the memory model, write data is compared with DUT write data, and a comparison result is printed.
In this embodiment, if the address is a cacheable address, whether the storage instruction in the DUT is committed is monitored, and if the storage instruction is committed, information of the storage instruction, including the address, data, and the like, is stored in the storage buffer.
The key of the embodiment capable of supporting multi-core storage instruction verification is to accurately grasp the execution time point of a storage instruction, wherein the execution means that the operation of the instruction can be seen by other cores. The performance time point of the access instruction is influenced by the attribute of the access address, if the access instruction is an uncacheable address, the performance time point is the time point when the read request in the DUT is sent to the peripheral interface, and if the access instruction is a cacheable address, the performance time point is the time point when the access instruction takes data from the primary cache.
The performance time point of the storage instruction is also influenced by the access address attribute, if the storage instruction is an uncacheable address, the performance time point is the time point when the write request in the DUT is sent to the peripheral interface, and if the storage instruction is a cacheable address, the performance time point is the time point when the storage instruction is written into the cache from the storage buffer. The corresponding instruction in the verification system is executed when the memory access instruction is executed, but not when the memory access instruction is submitted.
For the instruction of the atomic operation, the verification of the correctness of the atomic operation is supported, the verification of the key interface of the second-level cache is supported, and before the error is reported by the storage instruction, the data error is reported in advance by monitoring the interface of the second-level cache, so that the debug efficiency is improved.
The number of the supporting processors and the number of the cluster can be matched, and the expansibility is strong.
In conclusion, the invention supports the access instruction verification of multi-core multi-cluster, and the number of the cores and the clusters can be matched, thereby realizing parameterization and having expandability.
The method supports real-time comparison of the correctness of the execution of the access instruction of each core in a multi-core system, and comprises the steps of comparing the correctness of data obtained by access when the access instruction is submitted, and comparing the correctness of write data when the storage instruction updates the cache.
The invention supports the verification of atomic operation instructions in a multi-core system, supports the verification of a second-level cache key interface in a multi-cluster system, and has strong market application prospect.
The above examples are only intended to illustrate the technical solution of the present invention, but not to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.
Claims (10)
1. A multi-core memory access instruction verification method is characterized by comprising the following steps:
s1 the instruction generator generates an instruction, and judges the type of the instruction through the verification system, if the instruction is an access instruction, the access instruction is stored in an access instruction queue, and if the instruction is a storage instruction, the storage instruction is stored in a storage instruction queue;
s2 storing the instruction into the access instruction queue, updating the access instruction information in the DUT, and synchronously updating the access instruction information to the corresponding instruction in the access instruction queue;
s3 judging whether it is a cacheable address according to the address attribute, and executing the access instruction of the corresponding process or writing into the memory model according to the result;
s4, if the access instruction is received, monitoring the submission of the access instruction in the DUT, comparing the access data stored in the verification system with the access data obtained in the DUT, and outputting a comparison result;
and S5, if cache updating information in the DUT is monitored when the memory model is written, writing corresponding data in the storage buffer into the memory model, comparing the write data with the DUT write data, and outputting a comparison result.
2. The method according to claim 1, wherein after the instruction is stored in the access instruction queue, whether the instruction is a cacheable address is determined according to address attributes, if the instruction is a non-cacheable address, the performance time point is a time point when the read request in the DUT is sent to the peripheral interface, and if the instruction is a cacheable address, the performance time point is a time point when the access instruction takes data from the primary cache.
3. The method as claimed in claim 2, wherein if the address is a non-cacheable address, when a corresponding access request on the DUT peripheral interface is monitored, it is determined from which core the request came, the access instruction of the core in the verification system is executed, data is obtained from the memory model, and the data is retained for subsequent comparison.
4. The method as claimed in claim 2, wherein if the address is a cacheable address, when it is monitored that the instruction in the DUT obtains data, the access instruction of the core in the verification system is executed.
5. The method according to claim 1, wherein after the instruction is stored in the storage instruction queue, whether the instruction is a cacheable address is determined according to the address attribute, if the instruction is a non-cacheable address, the performance time point is a time point when the write request in the DUT is sent to the peripheral interface, and if the instruction is a cacheable address, the performance time point is a time point when the storage instruction is written into the cache from the storage cache.
6. The multi-core memory access instruction verification method according to claim 5, wherein in the method, if the address is an uncacheable address, when a corresponding write request on a DUT peripheral interface is monitored, which core the request comes from is judged, a storage instruction of the core in the verification system is executed, data is written into the memory model, write data is compared with DUT write data, and a comparison result is printed.
7. The method as claimed in claim 5, wherein if the address is a cacheable address, the method monitors whether the store instruction in the DUT is committed, and if the store instruction is committed, the store instruction information including the address, data and the like is stored in the store buffer.
8. A multi-core memory access instruction verification system, which is used for being executed by the multi-core memory access instruction verification method of any one of claims 1 to 7, and is characterized by comprising
A DUT monitor for monitoring a DUT for critical signals to cause the verification system to perform corresponding operations based on the monitored DUT signals;
the access instruction queue is used for storing information of the access instruction, and storing the access instruction into the access instruction queue according to the type of the instruction after the instruction generator sends the instruction to the DUT and the verification system;
the storage instruction queue is used for storing information of storage instructions, and storing the storage instructions into the access instruction queue according to the types of the instructions after the instruction generator simultaneously sends the instructions to the DUT and the verification system;
the memory access instruction controller is used for controlling when the memory access instruction information in the verification system is updated, executing the operation of accessing the memory model and updating the memory model or comparing data, and refreshing a queue in the verification system for the behavior of a DUT (device under test) pipeline refreshing;
the storage buffer is used for verifying the storage of corresponding instructions in a storage instruction queue in the system, simultaneously writing corresponding data in the storage buffer into a memory model, and deleting corresponding instruction information in the storage buffer;
the memory model is used for verifying the memory model in the system, and the time point of accessing and updating the memory model by the access instruction is the time point of the access instruction performance;
the access data comparator is used for comparing the data obtained by the instruction in the verification system with the data obtained by the DUT when the access instruction is submitted, and printing a comparison result;
the storage data comparator is used for comparing the write data of the instruction in the verification system with the write data in the DUT and printing a comparison result when the DUT stores the instruction and updates the cache;
the atomic instruction comparator is used for verifying the correctness of the instruction with the atomic operation in the multi-core system;
and the second-level cache comparator is used for comparing the key interfaces of the second-level cache in the DUT and comparing whether the address and the data in the related interfaces are consistent with the data corresponding to the address in the memory template or not.
9. The system of claim 8, wherein the DUT monitor monitors DUT critical signals including access instruction address data update information, instruction commit information, store buffer update information, and first level cache update information, second level cache critical interface signals;
the atomic instruction comparator is used for comparing whether LRSC (low-rate register) instruction retrieval data are correct, whether the execution result of the SC instruction is successful or failed and whether the AMO instruction obtains the correct data;
the key interfaces of the second-level cache comparator for comparing the second-level cache in the DUT comprise a read request interface of the core and the second-level cache, a read request interface of the second-level cache and the next-level memory and a second-level cache monitoring interface.
10. The system of claim 8, wherein in the access instruction queue, when information such as access instruction addresses and attributes in the DUT is updated, corresponding instruction information in the queue is updated synchronously; when an access instruction in the DUT commits, the corresponding instruction in the queue is deleted.
In the storage instruction queue, when information such as storage instruction addresses, attributes, data and the like in the DUT is updated, corresponding instruction information in the queue is synchronously updated; when an access instruction in the DUT commits, the corresponding instruction in the queue is deleted and the instruction information is stored in the memory buffer.
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