CN114218588A - Anti-attack block cipher encryption method for multi-scenario applications - Google Patents
Anti-attack block cipher encryption method for multi-scenario applications Download PDFInfo
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- CN114218588A CN114218588A CN202111504497.7A CN202111504497A CN114218588A CN 114218588 A CN114218588 A CN 114218588A CN 202111504497 A CN202111504497 A CN 202111504497A CN 114218588 A CN114218588 A CN 114218588A
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- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
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Abstract
The invention relates to an anti-attack block cipher encryption method for multi-scenario application. Firstly, a group of random numbers generated by a random number module are prestored in a register, plaintext is encrypted by designing two groups of round functions at the same time, irrelevant data is encrypted by an irrelevant key at the same time of encrypting the correct plaintext to interfere with a power consumption curve of a current chip, so that the power consumption curve obtained by an attacker contains irrelevant power consumption, the analysis difficulty of the power consumption curve is increased, and meanwhile, a random dummy round is inserted into 10 rounds of encryption in normal operation to prevent fault injection attack; when no attacker attacks, the two sets of round functions can be used simultaneously, and the two sets of plaintext are encrypted simultaneously, so that the encryption speed is increased.
Description
Technical Field
The invention belongs to the field of embedded microcontrollers, and provides a block cipher encryption method capable of preventing attacks to a certain extent.
Background
With the wide range of applications of intelligent devices, data security in the process of data encryption is a considered problem, and how to defend an attacker against attacks in the encryption process is an important aspect of data security. The encryption algorithm is subjected to strict mathematical reasoning verification when being proposed, and is confirmed to be irreversible under the condition of known ciphertext, but when the encryption process is actually realized, other loopholes are always accompanied, and the secret key can be obtained through simple analysis.
Accompanying with information leakage in the encryption process of an attacker, the attacker researches a plurality of attack modes such as energy attack, fault attack and the like, so that defense in the encryption process is an important ring in the defense process, different defense means exist aiming at different attack means, new holes can be introduced into some defense means, and the attacker is difficult to obtain effective information by adopting interference and insertion modes.
Disclosure of Invention
The invention relates to an anti-attack encryption scheme design of a block cipher capable of being applied in multiple scenes. Firstly, a group of random numbers generated by a random number module (RNG) are prestored in a register, the plaintext is encrypted by designing two groups of round functions at the same time, and irrelevant data is encrypted by an irrelevant key at the same time of encrypting the correct plaintext to interfere with a power consumption curve of a current chip, so that the power consumption curve obtained by an attacker contains irrelevant power consumption, the power consumption curve analysis difficulty is increased, and meanwhile, a random dummy wheel is inserted into a 10-round AES encryption algorithm in normal operation to prevent fault injection attack; when no attacker attacks, the two sets of round functions can be used simultaneously, and the two sets of plaintext are encrypted simultaneously, so that the encryption speed is increased.
The technical scheme adopted by the invention for realizing the purpose is as follows: before encryption operation, a random number module writes several groups of random numbers into a register for standby use when encryption and random number fetching operations are not performed, simultaneously generates a signal that the random numbers are not empty, and simultaneously performs round key generation and encryption operations after plaintext writing so as to interfere with power consumption information in an encryption process.
When the controller is idle, the random number module writes a random number into the random number register, finishes the preparation work before encryption and generates a data non-idle signal to the controller;
starting an anti-attack mode enable, starting an encryption mode, and performing a first round of encryption operation and key expansion after writing in a plaintext;
simultaneously, different pseudo-rounds are randomly inserted in the 10 rounds of AES encryption process, after encryption is completed, a correct ciphertext and an interference ciphertext are simultaneously stored in corresponding registers, and the correct ciphertext is read;
when the anti-attack mode is not enabled, two plaintexts can be written simultaneously for encryption for different application scenarios.
The anti-attack block cipher encryption method for multi-scenario application comprises the following steps:
1) writing a plaintext into a plaintext register by a user; the random number module writes a random number into a random number register in the encryption control module and updates the random number in idle time;
2) when encryption operation is started, a controller in an encryption control module reads one group of random numbers, and k dummy wheels are inserted into an ith wheel according to the value of the first group of random numbers to ensure that the real encryption position is random;
3) the controller writes a plaintext, a round key and a random number into a round function A, a round function B, a key expansion A and a key expansion B respectively, and simultaneously starts the round function A, the round function B, the key expansion A and the key expansion B to enable power consumption generated by the round function A, the round function B, the key expansion A and the key expansion B to interfere with each other;
4) and returning to the step 3) to circulate the round function encryption process for multiple times until the current plaintext is encrypted, and writing the ciphertext into a ciphertext register which can be read by a user to finish one encryption operation.
4. The encryption method of the attack-prevention block cipher for the multi-scenario application according to claim 1, wherein for the plaintext encryption, when a user writes an ith plaintext, the plaintext register is in a full state, the plaintext is read into the controller after the start of the operation, and the plaintext register becomes in a null state to continue to write an (i + 1) th plaintext;
and when the ith plaintext is encrypted, the ciphertext register is changed into a full state to be read by the user, the controller encrypts the (i + 1) th plaintext at the moment, and the step 2) is returned until all plaintext encryption of the user is completed.
And (4) performing serial operation for 10 rounds, performing one round of encrypted data operation in one cycle, and rewriting the result of the previous round into a round function to perform the next round of operation.
The invention has the following beneficial effects and advantages:
1. the invention adopts a mode of linkage of the random number module and the encryption module, the random number module writes data into the specific register in idle time and calls the specific register in encryption, thereby preventing the encryption speed from being influenced by the slow data generation of the random number module, and after the random number is prepared, the control logic can automatically call the random number after the attack prevention and is applied in the encryption process.
2. The invention adopts two round functions to carry out parallel operation design, one true and one false design interferes the power consumption of the chip, so that an attacker has interference when acquiring the power consumption, and the attack difficulty is increased; inserting dummy rounds between each round function makes it difficult for an attacker to perform fault injection.
3. The invention can be applied to other block cipher algorithms, in the realization process, the block cipher algorithms such as AES and DES are designed in the same control logic to reduce the chip area consumption, and simultaneously, the multiplexing design can be carried out on the same logic part to further reduce the area consumption.
Drawings
Fig. 1 is a diagram of an encryption algorithm structure with an anti-attack function according to the present invention.
Detailed Description
The present invention will be described in detail below with reference to the accompanying drawings.
The controller of the encryption algorithm with the anti-attack function has the design idea that as shown in fig. 1:
the operation process of the encryption algorithm is that data is written into the algorithm control register through the random number module, and then the controller carries out encryption operation until the operation is finished. A random number module (RNG) writes random numbers into a register in an encryption control module and updates the random numbers when the RNG is idle, after a user writes 128-bit plaintext into the register, when an all-attack-prevention mode is started and encryption operation is started, a controller reads one group of random numbers, k pseudo wheels are inserted into the ith wheel according to the value of the first group of 128-bit random numbers and user setting, the real encryption position is ensured to be random, the controller writes the plaintext and the round keys into a round function A, a round function B, a key expansion A and a key expansion B, simultaneously starts the round function A, the round function B, the key expansion A and the key expansion B to enable the generated power consumption to interfere with each other, after the current round encryption is completed, the current ciphertext and the round keys are written into an internal register, and simultaneously the ciphertext and the round keys generated by the random numbers are written into the original register for the next use, the method prevents the encryption time from being greatly prolonged due to the fact that random numbers are generated by a random digital-analog block too slowly, the random numbers used each time are different in plaintext, the power consumption interference caused by repeated use is prevented from being the same, the round function encryption process is circulated for multiple times, and after the current plaintext is encrypted, a ciphertext is written into a register which can be read by a user to complete encryption operation once. When the user writes the first plaintext, the plaintext register is in a full state, the plaintext is read into the controller after the operation is started, the plaintext register is in an empty state, the plaintext register can be continuously written into the second plaintext, after the encryption of the first plaintext is finished, the ciphertext register is in a full state and is ready to be read by the user, the controller carries out the encryption of the second plaintext at the moment, and the encryption process is analogized until all plaintext encryption of the user is finished.
The round function includes byte substitution, row shift, column mixing, and round key addition. The byte substitution includes an S-box storing 16 × 16 8 bits of data, since each byte in the S-box maps it to a finite field GF (2)8) The inverse of (1) can calculate the corresponding relation between the input and the output of the S box through the expanded Euclidean algorithm and matrix transformation. The row shift can be directly transformed, and then the row and column mixing is realized by multiplying the operation matrix, and the value after the row shift is multiplied by the matrixWherein multiplication and addition between matrix elements is defined in Z2[x]Irreducible polynomial m (x) x8+x4+x3+ x +1 configuration GF (2)8) Is performed. And finally, adding the key in turn to finish the encryption operation in one turn.
The control register comprises a pseudo wheel control enable, a parallel operation interference enable, the number of pseudo wheels and the like. A user can start part of functions according to actual use conditions, and the round function B can also be applied to an encryption algorithm for operation under the condition that parallel operation interference enabling is not started, so that two groups of plaintexts can be encrypted simultaneously, and the efficiency is improved.
In the invention, through the random number generated by the random digital-analog module, the encryption algorithm controller applies the random number to carry out random insertion of the pseudo wheel and interference, so that the attack is difficult to acquire correct power consumption and cannot judge the ongoing process of the chip at the position, further, the power consumption analysis, fault attack and other means can not be used in a targeted manner, and the attack difficulty is increased. In the design, one controller is not only mounted with a single encryption algorithm, but also simultaneously connected with a plurality of grouping algorithms, such as DES, AES and the like, so that multiplexing design is carried out on partial functions, and the chip area consumption of a control logic part is reduced, so that the control logic of the invention can be applied to different use environments by combining different grouping algorithms according to different requirements.
Claims (5)
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN114531239A (en) * | 2022-04-20 | 2022-05-24 | 广州万协通信息技术有限公司 | Data transmission method and system for multiple encryption keys |
| US20230216677A1 (en) * | 2021-12-30 | 2023-07-06 | Nuvoton Technology Corporation | Cipher accelerator and differential fault analysis method for encryption/decryption operation |
| CN116722970A (en) * | 2023-08-09 | 2023-09-08 | 中国科学院长春光学精密机械与物理研究所 | A hardware-based anti-attack gateway security system |
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| CN103916235A (en) * | 2012-12-28 | 2014-07-09 | 北京中电华大电子设计有限责任公司 | Power consumption attack defending method by inserting pseudo wheel operation pair randomly |
| CN105656619A (en) * | 2016-02-02 | 2016-06-08 | 清华大学无锡应用技术研究院 | AES (Advanced Encryption Standard) encryption method and power attack resisting method based on the same |
| CN112765686A (en) * | 2021-01-06 | 2021-05-07 | 苏州裕太微电子有限公司 | Power consumption attack prevention framework and method for algorithm key in chip |
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Patent Citations (4)
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| CN101754205A (en) * | 2009-12-25 | 2010-06-23 | 西安交通大学 | Parallelized multi-receiver signcryption method |
| CN103916235A (en) * | 2012-12-28 | 2014-07-09 | 北京中电华大电子设计有限责任公司 | Power consumption attack defending method by inserting pseudo wheel operation pair randomly |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
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| US20230216677A1 (en) * | 2021-12-30 | 2023-07-06 | Nuvoton Technology Corporation | Cipher accelerator and differential fault analysis method for encryption/decryption operation |
| US12425213B2 (en) * | 2021-12-30 | 2025-09-23 | Nuvoton Technology Corporation | Cipher accelerator and differential fault analysis method for encryption/decryption operation |
| CN114531239A (en) * | 2022-04-20 | 2022-05-24 | 广州万协通信息技术有限公司 | Data transmission method and system for multiple encryption keys |
| CN114531239B (en) * | 2022-04-20 | 2022-08-12 | 广州万协通信息技术有限公司 | Data transmission method and system for multiple encryption keys |
| CN116722970A (en) * | 2023-08-09 | 2023-09-08 | 中国科学院长春光学精密机械与物理研究所 | A hardware-based anti-attack gateway security system |
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