CN114038991A - Spintronic devices, memory cells, memory arrays, and read-write circuits - Google Patents
Spintronic devices, memory cells, memory arrays, and read-write circuits Download PDFInfo
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- CN114038991A CN114038991A CN202111195175.9A CN202111195175A CN114038991A CN 114038991 A CN114038991 A CN 114038991A CN 202111195175 A CN202111195175 A CN 202111195175A CN 114038991 A CN114038991 A CN 114038991A
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- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
- G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
- G11C11/161—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell
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- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
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- G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
- G11C11/165—Auxiliary circuits
- G11C11/1653—Address circuits or decoders
- G11C11/1655—Bit-line or column circuits
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- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
- G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
- G11C11/165—Auxiliary circuits
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- G11C11/1657—Word-line or row circuits
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- G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
- G11C11/165—Auxiliary circuits
- G11C11/1673—Reading or sensing circuits or methods
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- G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
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- H10B—ELECTRONIC MEMORY DEVICES
- H10B61/00—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
- H10B61/20—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices comprising components having three or more electrodes, e.g. transistors
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Abstract
本公开提供了一种自旋电子器件，应用于集成技术领域，包括：底电极，自旋轨道耦合层，设置在所述底电极上，至少一对磁性隧道结，设置在所述自旋轨道耦合层上，每个所述磁性隧道结包括由下而上依次设置的自由层、隧穿层和参考层，每对所述磁性隧道结的两个磁性隧道结的参考层磁化方向相反，顶电极，设置在每个所述磁性隧道结的参考层上。本公开还公开了一种存储单元、存储阵列和读写电路。
The present disclosure provides a spintronic device applied in the field of integration technology, comprising: a bottom electrode, a spin-orbit coupling layer disposed on the bottom electrode, and at least a pair of magnetic tunnel junctions disposed on the spin-orbit On the coupling layer, each of the magnetic tunnel junctions includes a free layer, a tunneling layer and a reference layer sequentially arranged from bottom to top, and the magnetization directions of the reference layers of the two magnetic tunnel junctions of each pair of the magnetic tunnel junctions are opposite. An electrode is provided on the reference layer of each of the magnetic tunnel junctions. The present disclosure also discloses a storage unit, a storage array and a read-write circuit.
Description
Technical Field
The present disclosure relates to the field of integrated circuit technologies, and in particular, to a spintronic device, a memory cell, a memory array, and a read/write circuit.
Background
A spin orbit torque magnetic random access memory (SOT-MRAM) switches the magnetization direction of a free layer by a spin current in a vertical direction induced by a current flowing through a heavy metal layer, and realizes low resistance and high resistance states respectively according to parallel or antiparallel arrangement of the magnetization directions of the free layer and a reference layer. Meanwhile, the SOT-MRAM has the advantages of high speed and high durability, and provides possibility for integrated application. However, the switching of the conventional SOT-MRAM requires in-plane field assist, which is not conducive to integration; and the tunneling magneto-resistance (TMR) of the Magnetic Tunnel Junction (MTJ) is low, generally reaching 100% -150%, which causes the process fluctuation to cause a large misreading probability.
Disclosure of Invention
It is a primary object of the present disclosure to provide a spintronic device, memory cell, memory array, and read/write circuit with no off-field switching and high read/write margin.
To achieve the above object, a first aspect of embodiments of the present disclosure provides a spintronic device, including:
a bottom electrode;
a spin-orbit coupling layer disposed on the bottom electrode;
at least one pair of magnetic tunnel junctions, arranged on the spin orbit coupling layer, wherein each magnetic tunnel junction comprises a free layer, a tunneling layer and a reference layer which are arranged from bottom to top in sequence, and the magnetization directions of the reference layers of the two magnetic tunnel junctions of each pair of magnetic tunnel junctions are opposite;
a top electrode disposed on the reference layer of each of the magnetic tunnel junctions.
In one embodiment, the structure of each of the magnetic tunnel junctions is a chordal structure.
In one embodiment, a straight edge of each of the magnetic tunnel junctions forms a predetermined angle with an axis of the spin-orbit coupling layer in a length direction.
In one embodiment, the bottom electrode comprises:
a first electrode connected to a first end of the spin-orbit coupling layer;
a second electrode connected to a second end of the spin-orbit coupling layer;
wherein the first end and the second end of the spin-orbit coupling layer are oppositely arranged.
In one embodiment, the spin-orbit coupling layer is made of a heavy metal material.
A second aspect of an embodiment of the present disclosure provides a memory cell, including:
a spintronic device as described in the first aspect;
the first transistor comprises a first end, a second end and a third end, the first end of the first transistor is connected with one end of the bottom electrode, the second end of the first transistor is connected with a write word line, the third end of the first transistor is connected with a bit line, and the other end of the bottom electrode is connected with a source line;
a second transistor including a first terminal, a second terminal and a third terminal, wherein the first terminal of the second transistor is connected to one of the top electrodes of the pair of magnetic tunnel junctions, the second terminal of the second transistor is connected to the read word line, and the third terminal of the second transistor is connected to the bit line;
and the third transistor comprises a first end, a second end and a third end, wherein the first end of the third transistor is connected with the other top electrode in the pair of magnetic tunnel junctions, the second end of the third transistor is connected with the reading word line, and the third end of the third transistor is connected with the reverse bit line.
A third aspect of the embodiments of the present disclosure provides a memory array, including: the memory comprises m write word lines, m read word lines, n source lines and m rows and n columns of memory cells, wherein the memory cells are the memory cells in the second aspect of the embodiment of the disclosure, and m and n are positive integers;
the bit line of each memory cell in the same column is connected to the same bit line, and the bit bar line of each memory cell in the same column is connected to the same bit bar line;
the write word line of each memory cell in the same row is connected to the same write word line, and the read word line of each memory cell in the same column is connected to the same read word line.
A fourth aspect of the embodiments of the present disclosure provides a read/write circuit, including:
a memory array as described in the third aspect of the embodiments of the present disclosure;
a bit line decoder for supplying a bit line operating voltage to the n bit lines and the n bit bar lines;
a word line decoder for supplying word line operating voltages to the m write word lines and the m read word lines;
a source line decoder for supplying a bit line operating voltage and an induced current to n source lines;
and the reading operation module is used for reading the data stored in the storage array and carrying out logic operation on the data stored in the storage array.
In one embodiment, the read operation module includes:
the current type sensitive amplifier comprises an input end, a reference end and an output end, wherein the input end of the current type sensitive amplifier is connected with the bit line through the bit line decoder, and the reference end of the current type sensitive amplifier is connected with the bit line through the bit line decoder;
the adder comprises an input end and an output end, and the input end of the adder is connected with the output end of the current-mode sensitive amplifier;
and the register is connected with the output end of the adder.
In one embodiment, the read-write circuit is used for binarizing a neural network.
It can be known from the foregoing embodiments of the present disclosure that the spintronic device, the memory unit, the memory array and the read/write circuit provided by the present disclosure can realize unipolar current pulse driving magnetization switching without external magnetic field determinacy. On the other hand, the magnetization directions of the reference layers of the two magnetic tunnel junctions of each pair of magnetic tunnel junctions are opposite, so that the two magnetic tunnel junctions are always in opposite resistance states, self-reference is realized, and the reading margin is improved. In yet another aspect, the memory array is constructed to implement matrix-vector multiplication operations in conjunction with external circuitry.
Drawings
In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present disclosure, and other drawings can be obtained by those skilled in the art without creative efforts.
Fig. 1 is a schematic structural diagram of a spintronic device provided in an embodiment of the present disclosure;
FIG. 2 is a top view of a spintronic device provided in an embodiment of the present disclosure;
FIG. 3 is a magnetization switching curve of a spintronic device provided in accordance with an embodiment of the present disclosure;
FIG. 4 is a unipolar pulse synchronous inversion curve of a spintronic device provided in an embodiment of the present disclosure;
FIG. 5 is a schematic diagram of a memory cell provided in an embodiment of the present disclosure;
FIG. 6 is a schematic diagram of a memory array provided by an embodiment of the present disclosure;
fig. 7 is a schematic diagram of a read/write circuit according to an embodiment of the disclosure.
Detailed Description
In order to make the objects, features and advantages of the present disclosure more apparent and understandable, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present disclosure, and it is apparent that the described embodiments are only a part of the embodiments of the present disclosure, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments disclosed herein without making any creative effort, shall fall within the protection scope of the present disclosure.
Referring to fig. 1, fig. 1 is a schematic structural diagram of a spintronic device according to an embodiment of the present disclosure, the spintronic device includes: the magnetic tunnel junction structure comprises bottom electrodes 101 and 104, a spin-orbit coupling layer 102 arranged on the bottom electrodes 101 and 104, at least one pair of magnetic tunnel junctions 103 arranged on the spin-orbit coupling layer 102, wherein each magnetic tunnel junction 103 comprises a free layer 1031, a tunneling layer 1032 and a reference layer 1033 which are arranged from bottom to top in sequence, the magnetization directions of the reference layers 1033 of each pair of magnetic tunnel junctions 103 are opposite, and a top electrode 1034 is arranged on the reference layer 1033 of each magnetic tunnel junction 103.
In an embodiment of the present disclosure, the materials of the reference layer 1033 and the free layer 1031 are one or more of CoFeB, Co/Pt, etc. ferromagnetic materials with perpendicular magnetic anisotropy. The spin-orbit coupling layer 102 is made of one or more kinds of heavy metals such as Pt, Ta, and W. The bottom electrodes 101, 104 and top electrode 1034 are made of metals such as Ti/Au, Ti/Pt, Cr/Au, Ta/CuN, etc. More, the tunneling layer 1032 is made of MgO, Al2O3And the like.
Referring to fig. 2, fig. 2 is a top view of a spintronic device according to an embodiment of the present disclosure.
In an embodiment of the present disclosure, the structure of each magnetic tunnel junction 103 is a chordal structure. The straight line side of each magnetic tunnel junction 103 forms a predetermined angle with the axis of the spin-orbit coupling layer 102 in the length direction
The asymmetric shape of the magnetic tunnel junction 103 induces a certain shape anisotropy, and in combination with the DM antisymmetric exchange effect, a field-free deterministic switching of the magnetic tunnel junction 103 can be achieved, and unipolar switching can be achieved. When a current flows through the spin-orbit coupling layer 102, a spin current in a vertical direction is generated due to a spin hall effect of a heavy metal or a Rashaba effect of an interface, so that the free layer 1031 of the magnetic tunnel junction 103 is turned over. Because the magnetization directions of the reference layers 1033 of the two magnetic tunnel junctions 103 are opposite, the two magnetic tunnel junctions 103 always store opposite resistance states.
In the present disclosure, the straight sides of two magnetic tunnel junctions 103 of a pair of magnetic tunnel junctions form a predetermined angle with the axis of the spin-orbit coupling layer 102 in the length direction
May be the same or complementary and are not limited by the present disclosure.
Referring to fig. 3, fig. 3 is a magnetization inversion curve of a spintronic device according to an embodiment of the present disclosure. Setting a predetermined angle of intersection of a pair of magnetic tunnel junctions 103
Sequentially at 45 deg., 60 deg. and 90 deg., and applying a pulse width of 0.5ns along the x-axis direction and a density of 2 × 108A/cm2The synchronous field-free deterministic switching of a pair of magnetic tunnel junctions 103 is achieved.
Referring to fig. 4, fig. 4 is a unipolar pulse synchronous inversion curve of a spintronic device according to an embodiment of the present disclosure. Setting a predetermined angle of intersection of a pair of magnetic tunnel junctions 103
At 45 deg., continuously applying 4 pulses with width of 0.5ns and density of 2 × 10 along x-axis8A/cm2The synchronous repeated flipping of the two magnetic tunnel junctions 103 is achieved by the unipolar current pulses. The unipolar current pulses are easy to operate, simplifying the peripheral drive circuitry.
Referring to fig. 5, fig. 5 is a schematic diagram of a memory cell according to an embodiment of the disclosure. The memory cell includes: the spintronic device 604 shown in FIG. 1; a first transistor 601 including a first terminal, a second terminal and a third terminal, the first terminal of the first transistor is connected to the bottom electrode 101, the second terminal of the first transistor 601 is connected to the write word line WWL, the third terminal of the first transistor 601 is connected to the bit line BL, and the bottom electrode 104 is connected to the source line SL; a second transistor 602 including a first terminal, a second terminal, and a third terminal, the first terminal of the second transistor 602 being connected to one of the top electrodes 1034 of the pair of magnetic tunnel junctions 103, the second terminal of the second transistor 102 being connected to the read word line RWL, the third terminal of the second transistor 102 being connected to the bit line BL; a third transistor 603 including a first terminal, a second terminal, and a third terminal, wherein the first terminal of the third transistor 603 is connected to the other top electrode 1034 of the pair of magnetic tunnel junctions 103, the second terminal of the third transistor 603 is connected to the read word line RWL, and the third terminal of the third transistor 603 is connected to the bit bar line/BL.
In this embodiment, 601 may be considered a write control transistor, 602 and 603 may be considered read control transistors, and 604 may be a spintronic device. When a read operation is performed, the write word line WWL is pulled low, turning off the first transistor 601, the read word line RWL is pulled high, turning on the second transistor 602 and the third transistor 603, while the source line SL is grounded, so that a current flows through the pair of magnetic tunnel junctions 103 via the bit line BL and the bit bar line/BL. The current on the bit line BL and the bit bar line/BL flows into the current-mode sense amplifier CSA to read the storage state of the spintronic device 604, when a write operation is performed, the write word line WWL is pulled high to turn on the first transistor 601, the read word line RWL is pulled low to turn off the second transistor 602 and the third transistor 603, the source line SL is grounded, and the current between the bit line BL and the source line SL flows through the current path of the spin-orbit coupling layer 102 to flip the resistance state of the magnetic tunnel junction 103, thereby implementing the writing of the resistance state.
Referring to fig. 6, fig. 6 is a schematic diagram of a memory array according to an embodiment of the present disclosure, the memory array including: the memory comprises m write word lines, m read word lines, n source lines and m rows and n columns of memory cells, wherein the memory cells are as shown in FIG. 5, and m and n are positive integers; the bit line of each memory unit in the same column is connected to the same bit line, and the bit bar line of each memory unit in the same column is connected to the same bit bar line; the write word line of each memory cell in the same row is connected to the same write word line, and the read word line of each memory cell in the same column is connected to the same read word line.
Referring to fig. 7, fig. 7 is a schematic diagram of a read/write circuit according to an embodiment of the disclosure, the read/write circuit includes:
a memory array as shown in FIG. 6;
a bit line decoder for supplying a bit line operating voltage to the n bit lines and the n bit bar lines;
a word line decoder for supplying word line operating voltages to the m write word lines and the m read word lines;
a source line decoder for supplying a bit line operating voltage and an induced current to the n source lines;
and the reading operation module is used for reading the data stored in the storage array and carrying out logic operation on the data stored in the storage array.
In this embodiment, at the algorithm level, the high and low resistance states are mapped to (+1, 0), respectively. When the input of the front stage is high level, a multiplication result can be output according to the difference of the currents on the bit line BL and the bit line/BL, and the multiplication result is input into an adder and a register; when the input of the previous stage is at a low level, no output is generated, i.e., the output is at a low level. Through a series of multiply-add operations, matrix-vector multiply operation can be realized for the binarization neural network.
In one embodiment, the read operation module includes: the current type sense amplifier comprises an input end, a reference end and an output end, wherein the input end of the current type sense amplifier is connected with a bit line through a bit line decoder, and the other reference end of the current type sense amplifier is connected with an inverted bit line through the bit line decoder; the adder comprises an input end and an output end, and the input end of the adder is connected with the output end of the current-mode sensitive amplifier; and the register is connected with the output end of the adder.
Furthermore, the reference terminal of the current-mode sense amplifier may be connected to the bit line through the bit line decoder, and the input terminal of the current-mode sense amplifier may be connected to the bit bar line through the bit line decoder. The present disclosure is not so limited.
It should be noted that each functional module in each embodiment of the present disclosure may be integrated into one processing module, or each module may exist alone physically, or two or more modules are integrated into one module. The integrated module can be realized in a hardware mode, and can also be realized in a software functional module mode.
The integrated module, if implemented in the form of a software functional module and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present invention may be substantially or partially embodied in the form of a software product, or all or part of the technical solution that contributes to the prior art.
It should be noted that, for the sake of simplicity, the above-mentioned method embodiments are described as a series of acts or combinations, but those skilled in the art should understand that the present invention is not limited by the described order of acts, as some steps may be performed in other orders or simultaneously according to the present invention. Further, those skilled in the art will appreciate that the embodiments described in the specification are presently preferred and that no acts or modules are necessarily required of the invention.
In the above embodiments, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments.
The foregoing is a description of the spintronic device, the memory cell, the memory array and the read/write circuit provided by the present invention, and those skilled in the art will appreciate that the concepts of the embodiments of the present invention may be varied in their specific implementation manners and applications, and that the present disclosure should not be construed as limiting the present invention.
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