Disclosure of Invention
The foregoing objects, features and advantages of the disclosure will be more readily apparent from the following detailed description of the preferred embodiments taken in conjunction with the accompanying drawings.
The application aims to provide a clock acceleration synchronization method, a clock acceleration synchronization device, an electronic device and a computer readable storage medium, which can solve the problems that the traditional clock synchronization solution depends on professional hardware or software, frequent network communication is needed to calibrate time, any clock acceleration or periodic acceleration cannot be carried out, and the research and development efficiency of a transaction execution algorithm is low, the time consumption is long and the cost is high.
In a first aspect, the present application provides a clock acceleration synchronization method, which adopts the following technical scheme:
A clock acceleration synchronization method applied to a service system, the service system comprising a plurality of subsystems, the service system being communicatively connected to a dispatch center, the method comprising:
Receiving a clock control command sent by the dispatching center, wherein the clock control command comprises playback starting time, a first starting time point, acceleration times and service parameters, and the first starting time point is local physical time of the dispatching center;
Obtaining a second starting time point of each subsystem according to the first starting time point and the local physical time of each subsystem;
According to the second starting time point, the acceleration multiple and the playback starting time, obtaining simulation time of each subsystem taking the first starting time point as a reference, and obtaining task scheduling time of each subsystem according to the simulation time and the acceleration multiple, so that each subsystem executes tasks according to the service parameters and the task scheduling time.
In a possible embodiment, the step of obtaining the second starting time point of each subsystem according to the first starting time point and the local physical time of each subsystem includes:
Judging whether the local physical time of each subsystem is consistent with the first starting time point or not according to each subsystem;
if the first starting time point is consistent with the second starting time point of the subsystem, the first starting time point is taken as a second starting time point of the subsystem;
otherwise, a second starting time point of the subsystem is calculated according to the local physical time of the subsystem and the first starting time point.
In a possible implementation manner, the step of calculating the second starting time point of the subsystem according to the local physical time of the subsystem and the first starting time point includes:
Judging whether the first starting time point is earlier than the local physical time of the subsystem;
if yes, the second starting time point of the subsystem is:
BT2=LT-(LT-BT1)/SP
otherwise, the second starting time point of the subsystem is:
BT2=LT-(BT1-LT)/SP
wherein BT 2 represents the second start time point, BT 1 represents the first start time point, LT represents the local physical time of the subsystem, and SP represents the acceleration multiple.
In a possible implementation manner, the step of obtaining the simulation time of each subsystem based on the first starting time point according to the second starting time point, the acceleration multiple and the playback starting time includes:
obtaining the simulation time of the subsystem by adopting a first analytic formula, wherein the first analytic formula comprises:
ST=DT*SP+STp
Where dt=lt-BT 2, ST denotes the analog time, SP denotes the acceleration multiple, ST p denotes the playback start time, LT denotes the local physical time of the subsystem, and BT 2 denotes the second start time point of the subsystem.
In a possible implementation manner, the step of obtaining the task scheduling time of each subsystem according to the simulation time and the acceleration multiple includes:
Obtaining the scheduling time of each task of the subsystem by adopting a second analytic formula, wherein the second analytic formula comprises:
FT2=(LT+FT1-ST)/SP
Wherein FT 2 represents the scheduling time of the task, LT represents the local physical time of the subsystem, FT 1 represents the original execution time of the task, ST represents the simulation time of the subsystem, and SP represents the acceleration multiple.
In a possible embodiment, the method further comprises:
receiving a reset instruction sent by the dispatching center periodically, wherein the reset instruction comprises local physical time of the dispatching center;
Updating the value of the first starting time point to be the local physical time in the reset instruction;
and re-acquiring the second starting time point and the simulation time of each subsystem based on the updated first starting time point so as to calibrate the second starting time point and the simulation time of each subsystem.
In a possible embodiment, the clock control command further includes an instruction playback period, the method further comprising:
and aiming at each subsystem, obtaining a task processing period of a single-round service of the subsystem according to the task scheduling time of each task of the subsystem, and discarding execution of a next-round service of the subsystem under the condition that the task processing period is smaller than the instruction playback period.
In a second aspect, the present application provides a clock acceleration synchronization device, which adopts the following technical scheme:
a clock acceleration synchronization apparatus for use in a business system, the business system comprising a plurality of subsystems, the business system being communicatively coupled to a dispatch center, the apparatus comprising:
The receiving module is used for receiving a clock control command sent by the dispatching center, wherein the clock control command comprises playback starting time, a first starting time point, acceleration times and service parameters, and the first starting time point is local physical time of the dispatching center;
the verification calibration module is used for obtaining a second starting time point of each subsystem according to the first starting time point and the local physical time of each subsystem;
and the acceleration synchronization module is used for obtaining the simulation time of each subsystem taking the first starting time point as a reference according to the second starting time point, the acceleration multiple and the playback starting time, and obtaining the task scheduling time of each subsystem according to the simulation time and the acceleration multiple so as to enable each subsystem to execute tasks according to the service parameters and the task scheduling time.
In a possible embodiment, the step of verifying the calibration module for obtaining the second starting time point of each subsystem according to the first starting time point and the local physical time of each subsystem includes:
Judging whether the local physical time of each subsystem is consistent with the first starting time point or not according to each subsystem;
if the first starting time point is consistent with the second starting time point of the subsystem, the first starting time point is taken as a second starting time point of the subsystem;
otherwise, a second starting time point of the subsystem is calculated according to the local physical time of the subsystem and the first starting time point.
In a possible embodiment, the acceleration synchronization module comprises a first computing unit and a second computing unit;
the first calculation unit is configured to obtain a simulation time of the subsystem by using a first parsing formula, where the first parsing formula includes:
ST=DT*SP+STp
Wherein dt=lt-BT 2, ST denotes an analog time, SP denotes an acceleration multiple, ST p denotes a playback start time, LT denotes a local physical time of the subsystem, and BT 2 denotes a second start time point of the subsystem;
the second calculation unit is configured to obtain a scheduling time of each task of the subsystem by using a second parsing formula.
The second analytical formula includes:
FT2=(LT+FT1-ST)/SP
Where FT 2 represents the scheduled time of the task, FT 1 represents the original execution time of the task.
In one possible embodiment, the system further comprises an update module;
The receiving module is also used for receiving a reset instruction sent by the dispatching center periodically;
The updating module is configured to update a value of a first starting time point to a local physical time in a reset instruction, so as to reacquire a second starting time point and a simulation time of each subsystem based on the updated first starting time point, so as to calibrate the second starting time point and the simulation time of each subsystem.
In a possible implementation, the clock control command further includes an instruction playback period, and the system further includes a processing module;
The processing module is used for obtaining a task processing period of the single-round service of each subsystem according to the task scheduling time of each task of the subsystem, and discarding execution of the next-round service of the subsystem under the condition that the task processing period is smaller than the instruction playback period.
In a third aspect, the present application provides an electronic device, which adopts the following technical scheme:
An electronic device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, the processor implementing the method of the first aspect when executing the computer program.
In a fourth aspect, the present application provides a computer readable storage medium, which adopts the following technical scheme:
a computer readable storage medium comprising a computer program which, when run, controls an electronic device in which the computer readable storage medium resides to carry out the method of the first aspect.
The beneficial effects of the embodiments of the present application include, for example:
the method comprises the steps of receiving a clock control command sent by a dispatching center, calibrating and correcting the first starting time point at the angle of each subsystem according to the first starting time point of the clock control command, namely the local physical time of the dispatching center and the local physical time of each subsystem, so as to obtain a second starting time point of each subsystem, further obtaining simulation time of each subsystem taking the first starting time point (namely the local physical time of the dispatching center) as a reference according to the second starting time point of each subsystem and acceleration times and playback starting time in the clock control command, so that each subsystem can simulate the physical time of the dispatching center more accurately according to the own simulation time, further obtain task dispatching time of each subsystem according to the simulation time and the acceleration times, wherein the task dispatching time is time which takes the simulation time as a reference and is accelerated, and further the tasks of each subsystem on a service system can be accelerated synchronously, and the problems of low research and development efficiency and high time consumption of a transaction execution algorithm can be reduced.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present application more apparent, the technical solutions of the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application, and it is apparent that the described embodiments are some embodiments of the present application, but not all embodiments. The components of the embodiments of the present application generally described and illustrated in the figures herein may be arranged and designed in a wide variety of configurations.
Thus, the following detailed description of the embodiments of the application, as presented in the figures, is not intended to limit the scope of the application, as claimed, but is merely representative of selected embodiments of the application. All other embodiments, based on the embodiments of the application, which a person of ordinary skill in the art would achieve without inventive faculty, are within the scope of the application.
It should be noted that like reference numerals and letters refer to like items in the following figures, and thus once an item is defined in one figure, no further definition or explanation thereof is necessary in the following figures. Furthermore, the terms "first," "second," and the like, if any, are used merely for distinguishing between descriptions and not for indicating or implying a relative importance.
Referring to fig. 1, a schematic block diagram of an electronic device 01 according to an embodiment of the present application may include, but is not limited to, a memory 03 and a processor 02.
Wherein the processor 02 and the memory 03 are both located in the electronic device 01 but are separately located. However, it should be understood that the memory 03 may be replaced with a computer-readable storage medium, and that both the memory 03 and the computer-readable storage medium may be separate from the electronic device 01 and accessible to the processor 02 via a bus interface. Furthermore, the memory 03 may be integrated into the processor 02, and may be, for example, a cache and/or general-purpose registers.
In this embodiment, both the computer-readable storage medium and the memory 03 may be used to store a computer program, and the processor 02 can implement the clock acceleration synchronization method according to the embodiment of the present application when executing the computer program.
It should be noted that, the electronic device 01 shown in fig. 1 is a schematic structural diagram, and the electronic device 01 may further include more or fewer components than those shown in fig. 1, or have a different configuration from that shown in fig. 1. The components shown in fig. 1 may be implemented in hardware, software, or a combination thereof. The electronic device 01 may be, but is not limited to, a computer, a cell phone, an IPad, a server, a notebook, a mobile internet device, etc.
The clock acceleration synchronization method provided by the application can be applied to an application environment shown in fig. 2. The method is applied to a clock acceleration synchronization system. The clock acceleration synchronization system comprises a plurality of service system servers and a scheduling server, wherein the service system servers comprise a plurality of subsystem servers. Each subsystem server is provided with a subsystem, and the subsystem comprises a transaction system, a quotation system, an algorithm system and a transaction matching system. The dispatching server is provided with a dispatching center, and is communicated with each server area through a message distribution assembly, and the dispatching server also comprises a screen supporting man-machine interaction. And each subsystem server is also provided with a time acceleration receiver and a task scheduler, and the task schedulers are used for scheduling the tasks of the subsystem on the subsystem server, namely, the task schedulers are in one-to-one correspondence with the subsystems. The subsystem server and the scheduling server may be implemented as separate servers or as a cluster of multiple servers.
In one embodiment, as shown in FIG. 3, a clock acceleration synchronization method is provided. The present embodiment is mainly exemplified by the application of the method to a service system server as in fig. 2. The method is applied to a service system, the service system comprises a plurality of subsystems, and the service system is in communication connection with a dispatching center.
Step S100, a clock control command sent by a dispatching center is received.
The clock control command comprises playback starting time, a first starting time point, acceleration times and service parameters, wherein the first starting time point is local physical time of the dispatching center.
Specifically, a developer inputs scheduling information to a scheduling center through a screen of a scheduling server, and the scheduling center reads the scheduling information, wherein the scheduling information comprises an instruction period, acceleration times and service parameters. And the dispatching center generates a clock control command of the round of test according to the dispatching information, and broadcasts the clock control command to the service system server through the message distribution component.
Step S200, obtaining a second starting time point of each subsystem according to the first starting time point and the local physical time of each subsystem.
Specifically, after the time acceleration receiving server on each subsystem server receives the clock control command, the first starting time point is calibrated and corrected according to the first starting time point and the local physical time of the subsystem server where the first starting time point is located, so as to obtain a second starting time point of the subsystem server, namely a second starting time point of the subsystem.
Step S300, according to the second starting time point, the acceleration multiple and the playback starting time, obtaining the simulation time of each subsystem taking the first starting time point as a reference.
Specifically, the task scheduler on each subsystem server calculates the simulation time of each subsystem based on the first starting time point according to the second starting time point of the corresponding subsystem and the acceleration multiple and the playback starting time in the clock control command.
Step S400, obtaining task scheduling time of each subsystem according to the simulation time and the acceleration times, so that each subsystem executes tasks according to the service parameters and the task scheduling time.
The service parameter is an environmental parameter.
Specifically, the task scheduler on each subsystem server obtains the task scheduling time of the corresponding subsystem according to the simulation time and the acceleration multiple of the clock control command of the subsystem server where the task scheduler is located, and the task scheduler schedules the corresponding subsystem to execute the task according to the task scheduling time.
In the clock acceleration synchronization method, according to the first starting time point of the clock control command, namely, the local physical time of the dispatching center and the local physical time of each subsystem, the first starting time point is calibrated and corrected at the angle of each subsystem to obtain the second starting time point of each subsystem, and further, according to the second starting time point of each subsystem and the acceleration multiple and the playback starting time in the clock control command, the simulation time of each subsystem taking the first starting time point (namely, the local physical time of the dispatching center) as a reference is obtained, so that each subsystem can simulate the physical time of the dispatching center more accurately according to the own simulation time, and further, the task scheduling time of each subsystem is obtained according to the simulation time and the acceleration multiple.
In one embodiment, as shown in fig. 4, a flow chart of the sub-steps of the step S200 is shown, including the following steps.
Step S210, for each subsystem, determining whether the local physical time of the subsystem is consistent with the first starting time point.
If so, step S220 is performed.
Otherwise, step S230 is performed.
Step S220, taking the first starting time point as a second starting time point of the subsystem.
Step S230, a second starting time point of the subsystem is calculated according to the local physical time and the first starting time point of the subsystem.
It should be appreciated that when the first timestamp coincides with the local physical time of the subsystem, it is indicated that the subsystem is clock synchronized with the dispatch center, i.e., there is no time difference. When the first timestamp is consistent with the local physical time of the subsystem, the fact that the time difference exists between the subsystem and the dispatching center is indicated, and the first starting timestamp needs to be corrected.
Because the local physical time between the subsystems is different, when the first starting time point is corrected, the first starting time point needs to be independently corrected by taking a single subsystem as a unit, namely, different corrected first starting time points exist for different subsystems, and the second starting time point is the corrected first starting time point.
In one embodiment, step S230 specifically includes:
It is determined whether the first start time point is earlier than a local physical time of the subsystem.
If yes, the second starting time point of the subsystem is:
BT2=LT-(LT-BT1)/SP
otherwise, the second starting time point of the subsystem is:
BT2=LT-(BT1-LT)/SP
wherein BT 2 represents the second start time point, BT 1 represents the first start time point, LT represents the local physical time of the subsystem, and SP represents the acceleration multiple.
It can be clearly known that when the first starting time point is earlier than the local physical time of the subsystem, the difference between the local physical time and the first starting time point is divided by the acceleration multiple to obtain a time difference after acceleration, (LT-BT 1)/SP is the time difference after acceleration, the local physical time is used for subtracting the time difference after acceleration to obtain a second starting time point, when the first starting time point is later than the local physical time of the subsystem, the difference between the first starting time point and the local physical time is in the acceleration multiple to obtain the time difference after acceleration, (BT 1 -LT)/SP is the time difference after acceleration, and the local physical time is used for adding the time difference after acceleration to obtain the second starting time point of the subsystem.
Obviously, when the second starting time point is calculated, the acceleration multiple is considered, so that the local physical time of the dispatching center can be accurately simulated by the subsystems, and the local physical time of the dispatching center can be synchronously accelerated by the subsystems.
Further, in one embodiment, step S310 specifically includes obtaining a simulation time of the subsystem by using a first analytical formula.
Specifically, the first analytical formula includes st=dt×sp+st p.
DT=LT-BT2。
Where ST denotes an analog time, SP denotes an acceleration multiple, ST p denotes a playback start time, LT denotes a local physical time of the subsystem, and BT 2 denotes a second start time point of the subsystem.
The time difference between the local physical time of the subsystem and the second starting time point, namely DT, is obtained, and then the time difference is multiplied by the acceleration multiple and then the playback starting time is added to obtain the simulation time.
It should be appreciated that since a period of time has elapsed from the time when the second start time point is obtained in step S200 is performed to the time when the analog time is calculated in step S300, it is necessary to consider this period of time when calculating the analog time in order for the analog time to more accurately simulate the playback start time of the clock control instruction.
In the method for obtaining the simulation time of the subsystem, the time lapse during the program execution is considered, so that the obtained simulation time can simulate the playback start time in the clock control instruction more accurately.
In one embodiment, step S400 may specifically include obtaining the scheduling time of each task of the subsystem by using a second parsing formula.
The second analytical formula includes:
FT2=(LT+FT1-ST)/SP
Wherein FT 2 represents the scheduling time of the task, LT represents the local physical time of the subsystem, FT 1 represents the original execution time of the task, ST represents the simulation time of the subsystem, and SP represents the acceleration multiple.
The scheduling time of each task obtained by the method is the time after the original execution time is accelerated by taking the simulation time as a reference. Therefore, each task is executed at the scheduled time, and clock synchronous acceleration can be realized.
Further, the clock control command further includes an instruction playback period, and on this basis, as shown in fig. 5, the clock acceleration synchronization method further includes step S500.
Step S500, for each subsystem, according to the task scheduling time of each task of the subsystem, obtaining the task processing period of the single-round service of the subsystem, and discarding the execution of the next round service of the subsystem under the condition that the task processing period is smaller than the instruction playback period.
Specifically, the task scheduler obtains the task processing period of the single-round service of the subsystem according to the scheduling time of each task of the corresponding subsystem, generally, the scheduling time of the latest executed task. When the task processing period is smaller than the instruction playback period in the clock control command, the task scheduler discards the scheduling of the next round of service after the task of the single round of service is scheduled.
By the method, the next-round service of the subsystem with the task processing period smaller than the instruction playback period is abandoned, so that only a single-round service is executed in a single instruction playback period, and the situation that the next-round service is executed without processing the upper-round service under the acceleration condition can be avoided to a certain extent.
Because clock deviation may exist on the server where each subsystem is located, when the service system runs for a period of time in the above-mentioned clock synchronization acceleration method, the clock deviation may cause accumulation, and the clock synchronization acceleration deviation between the subsystems may be larger.
Based on the above consideration, on the basis of the above-described clock synchronization acceleration method, as shown in fig. 6, when the single-round playback task is being executed and has not yet ended, the clock acceleration synchronization method further includes:
Step S600, receiving a reset instruction sent by the dispatching center regularly.
Wherein the reset instruction includes local physical time of the dispatch center.
Specifically, when the playback end time has not yet reached, the scheduling center broadcasts a reset instruction, that is, a rest instruction, to the service system, and the service system receives the reset instruction.
In step S700, the value of the first starting time point is updated to be the local physical time in the reset instruction.
Specifically, after the service system receives the reset instruction, the time acceleration receiver of each subsystem updates the first starting time point to the local physical time in the reset instruction.
Based on the updated first starting time point, the steps S200 to S400 are repeated, i.e. the second starting time point and the simulation time of each subsystem are re-acquired, so as to re-calibrate the second starting time point and the simulation time of each subsystem, and further, the scheduling time of each task is re-acquired.
When each round of service is carried out, the method can be adopted to calibrate the time of each subsystem for a plurality of times so as to reduce clock deviation among the subsystems, and the simulation time taking the physical time of the dispatching center as a reference can be more accurately simulated, thereby further realizing clock acceleration synchronization among the subsystems.
Further, as shown in fig. 6, the clock acceleration synchronization method further includes step S800.
Step S800, according to the received stop instruction, the system is reset.
Specifically, the dispatching center sends a stop instruction, and the service system resets the system after receiving the stop instruction. The operation of system reset includes, but is not limited to, performing data backup on the task execution result, cleaning the memory of each subsystem, comparing the test result, and outputting the test result.
In one embodiment, as shown in fig. 7, the subsystem, the time acceleration receiver corresponding to the subsystem, and the timing diagram of the clock acceleration mechanism between the dispatch centers.
And after the subsystem is started, immediately registering the subsystem on the time acceleration receiver, subscribing a playback synchronous request to a dispatching center, and responding to the subscribed playback synchronous request by the dispatching center so as to broadcast a clock control command like the time acceleration receiver.
When the scheduling center reads the scheduling information, a clock control command is generated according to the scheduling information, the clock control command is broadcasted, and after the time acceleration receiver receives the clock control command, the first starting time point is checked, and the second starting time point is acquired.
It should be understood that, although the steps in the flowcharts of fig. 2-6 are shown in order as indicated by the arrows, these steps are not necessarily performed in order as indicated by the arrows. The steps are not strictly limited to the order of execution unless explicitly recited herein, and the steps may be executed in other orders. Moreover, at least some of the steps of fig. 2-6 may include multiple sub-steps or stages that are not necessarily performed at the same time, but may be performed at different times, nor does the order in which the sub-steps or stages are performed necessarily occur in sequence, but may be performed alternately or alternately with at least a portion of other steps or sub-steps or stages of other steps.
In one embodiment, as shown in fig. 8, a clock acceleration synchronization device is provided, and the clock acceleration synchronization device is applied to a service system, wherein the service system comprises a plurality of subsystems, and the service system is in communication connection with a dispatching center, and the clock acceleration synchronization device comprises a receiving module 04, a verification calibration module 05 and an acceleration synchronization module 06.
And the receiving module 04 is used for receiving the clock control command sent by the dispatching center.
The clock control command comprises playback starting time, a first starting time point, acceleration times and service parameters, wherein the first starting time point is local physical time of the dispatching center;
The verification calibration module 05 is configured to obtain a second starting time point of each subsystem according to the first starting time point and the local physical time of each subsystem.
And the acceleration synchronization module 06 is configured to obtain, according to the second start time point, the acceleration multiple, and the playback start time, a simulation time of each subsystem based on the first start time point, and obtain, according to the simulation time and the acceleration multiple, a task scheduling time of each subsystem, so that each subsystem executes a task according to the service parameter and the task scheduling time of each subsystem.
In the clock acceleration synchronization device, after the receiving module 04 receives the clock control command, the verification calibration module 05 calibrates and corrects the first start time point at the angle of each subsystem according to the first start time point of the clock control command, that is, the local physical time of the dispatching center, and the local physical time of each subsystem, so as to obtain the second start time point of each subsystem, the acceleration synchronization module 06 obtains the simulation time of each subsystem taking the first start time point (that is, the local physical time of the dispatching center) as a reference according to the second start time point of each subsystem and the acceleration multiple and the playback start time in the clock control command, so that each subsystem can more accurately simulate the physical time of the dispatching center according to the simulation time, and further obtain the task scheduling time of each subsystem according to the simulation time and the acceleration multiple, wherein the task scheduling time is the time after acceleration based on the simulation time, so that the tasks of each subsystem on the service system can be synchronously accelerated, and further reduce the test time consumption of the transaction execution algorithm to improve the problems of low development and development time consumption and high cost.
Further, referring to fig. 8, the clock acceleration synchronization apparatus further includes an update module 09, a system reset module 08, and a processing module 07.
The processing module 07 is configured to obtain, for each subsystem, a task processing period of a single-round service of the subsystem according to task scheduling time of each task of the subsystem, and discard execution of a next-round service of the subsystem when the task processing period is less than an instruction playback period.
The receiving module 04 is further configured to receive a reset instruction sent by the dispatch center periodically.
An updating module 09, configured to update the value of the first starting time point to the local physical time in the reset instruction.
After the updating module 09 updates, the verification calibration module 05 and the acceleration calibration module re-execute the corresponding tasks, and re-acquire the second starting time point and the simulation time of each subsystem, so as to re-calibrate the second starting time point and the simulation time of each subsystem, and further re-acquire the scheduling time of each task.
And the system reset module 08 is used for carrying out system reset according to the received stop instruction. Wherein stop
In one embodiment, the verification calibration module 05 performs the above steps S210-S230 to obtain the second starting time point of each subsystem according to the first starting time point and the local physical time of each subsystem.
The acceleration synchronization module 06 comprises a first calculation unit 061 and a second calculation unit 062.
The first calculating unit 061 is configured to obtain the simulation time of the subsystem by using a first parsing formula.
The first analytical formula includes:
ST=DT*SP+STp
Where dt=lt-BT 2, ST denotes the analog time, SP denotes the acceleration multiple, ST p denotes the playback start time, LT denotes the local physical time of the subsystem, and BT 2 denotes the second start time point of the subsystem.
And the second calculating unit 062 is used for obtaining the scheduling time of each task of the subsystem according to the second analytic formula.
The second analytical formula includes:
FT2=(LT+FT1-ST)/SP
Where FT 2 represents the scheduled time of the task, FT 1 represents the original execution time of the task.
For specific limitations of the clock acceleration synchronization device, reference may be made to the above limitation of the clock acceleration synchronization method, and no further description is given here. The various modules in the clock acceleration synchronization device described above may be implemented in whole or in part by software, hardware, and combinations thereof. The above modules may be embedded in hardware or may be independent of the processor 02 in the computer device, or may be stored in software in the memory 03 in the computer device, so that the processor 02 may call and execute operations corresponding to the above modules.
In the several embodiments provided in the present disclosure, it should be understood that the disclosed apparatus, system diagrams, and methods may be implemented in other manners. The apparatus, system, and method embodiments described above are merely illustrative, for example, flow diagrams and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of apparatus, methods and computer program products according to various embodiments of the present disclosure. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.
In addition, functional modules in various embodiments of the present disclosure may be integrated together to form a single part, or each module may exist alone, or two or more modules may be integrated to form a single part.
The functions, if implemented in the form of software functional modules and sold or used as a stand-alone product, may be stored in a computer-readable storage medium. Based on such understanding, the technical solution of the present disclosure may be embodied in essence or a part contributing to the prior art or a part of the technical solution, or in the form of a software product stored in a storage medium, including several instructions for causing a computer device (which may be a personal computer, an electronic device 01, or a network device, etc.) to perform all or part of the steps of the method according to the embodiments of the present disclosure. The storage medium includes a usb disk, a removable hard disk, a Read-Only Memory 03 (ROM), a random access Memory 03 (RAM, random Access Memory), a magnetic disk, an optical disk, or other various media capable of storing program codes. It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises an element.
The foregoing is merely an alternative embodiment of the present disclosure, and is not intended to limit the present disclosure, so that various modifications and variations may be made to the present disclosure by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present disclosure should be included in the protection scope of the present disclosure.