CN103011066B - Chip - Google Patents
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- CN103011066B CN103011066B CN201110294373.0A CN201110294373A CN103011066B CN 103011066 B CN103011066 B CN 103011066B CN 201110294373 A CN201110294373 A CN 201110294373A CN 103011066 B CN103011066 B CN 103011066B
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Abstract
The invention discloses a chip, which has high resistance to rupture. The chip is provided with a plurality of surfaces, wherein the surfaces comprise the maximum surface with the maximum area in all the surfaces and a lateral surface connected to an edge of the maximum surface. A nanostructure layer is formed on at least the lateral surface and has the effect of dispersing the chip stress, so that the chip has high resistance to rupture, and wear and even rupture of the chip due to external force in a semiconductor process or other processing processes can be avoided.
Description
Technical field
The present invention relates to a kind of chip, and especially, the present invention relates to a kind of chip with high resistance disruptiveness.
Background technology
Electronic industry development is in recent years advanced by leaps and bounds, and various multi-functional portable electronic products in people's life, live people more and more convenient as all incorporated in intelligent mobile phone, notebook computer, panel computer etc.In the behind of electronic industry development, the maturation development that is located thereon the semiconductor industry of trip has great contribution.Except the people's livelihood, Military Electronics industry,, if solar energy industry and illumination aspect are as LED industry, all there is the relevance of quite large degree energy aspect with semiconductor industry.In addition, semi-conductive technology also can be applicable to other fields such as raw skill, and it is wide that it involves scope, and the foundation stone that is referred to as science and technology in modern age was not yet.
The chip that semiconductor technology is produced can be used in above-mentioned various application widely, the qualification rate of chip can say the quality that has directly determined end product, therefore, on the material of chip and production method all circles all with the quantity research that has high input to guarantee its quality.No matter it is the chip of which kind of application, must pass through multiple tracks processing technology, for example, wafer cutting, etching, surface treatment, encapsulation, IC test supervisor, could obtain electronic component or the photoelectric cell of practical application.
In the technique of above-mentioned various process chip, chip often can be subject to the External Force Acting that degree is different.Generally speaking, the various functional structures on chip are arranged on the main surface that chip has maximum area conventionally, and each structure often can cause the defect on material on chip, and easily in these defects, produce the concentrated phenomenon of stress.When suffered external force increases gradually, the stress concentration phenomenon on these regions can be more violent.Because current chip material is all the material of using fragility, for example, Silicon Wafer, therefore above-mentioned stress concentration phenomenon easily makes die stress concentrate place's generation slight crack even to cause chip rupture, and then reduces chip yield and improve its production cost simultaneously.
Summary of the invention
Therefore, the object of the present invention is to provide a kind of chip with high resistance disruptiveness, to solve the problem of prior art.
According to a specific embodiment, chip of the present invention has a plurality of surfaces, and it is included in a largest face in each surface with maximum area, and the side surface that connects largest face edge.At least on side surface, be formed with the nanostructured layers of tool dispersive stress function, with the stress of dispersed chip.
In this specific embodiment, nanostructured layers can comprise a plurality of nanostructures, for example nanoneedle or nano-pillar.On the side surface of these nanostructures respectively at chip, form stress concentration point, when chip is stressed, on nanostructured layers a plurality of stress concentration points by stress dispersion on whole nanostructured layers, therefore, can avoid stress concentration in the functional structure of chip, and then prevent that chip from producing slight crack and even breaking.
About the advantages and spirit of the present invention, can be further understood by the following detailed description and accompanying drawings.
Accompanying drawing explanation
Fig. 1 is according to the schematic diagram of the chip of a specific embodiment of the present invention.
Fig. 2 is the actual look figure of the nanostructured layers of Fig. 1.
Fig. 3 is the generalized section of the nanostructured layers of Fig. 2.
Fig. 4 A is the schematic diagram that the chip of Fig. 1 carries out three-point bending resistance test.
Fig. 4 B is the chart of the corresponding etching period of the maximum load that can bear of the chip of Fig. 4 A.
Fig. 5 is according to the generalized section of the chip of another specific embodiment of the present invention.
Fig. 6 is according to the schematic diagram of the chip of another specific embodiment of the present invention.
Fig. 7 is according to the schematic diagram of the chip of another specific embodiment of the present invention.
Wherein, description of reference numerals is as follows:
1,2,3,4: chip
10,20,30,40: largest face
12,22,32,42: side surface
14,24,34,44: nanostructured layers
140: nanoneedle
142: nano-pillar
L: reference line
Embodiment
Refer to Fig. 1, Fig. 1 is according to the schematic diagram of the chip 1 of a specific embodiment of the present invention, and in practice, this chip 1 can be one of them of solar chip, LED chip and semiconductor chip, or other is with the chip of semiconductor technology processing.As shown in Figure 1, have a plurality of surfaces on chip 1, wherein, the largest face 10 of area maximum is commonly used to arrange various functional structures thereon.Take semiconductor chip as example, in largest face, the electrode structures such as gate, drain or source electrode can be set, or chip itself can be P type semiconductor, is formed with n type semiconductor layer in largest face, vice versa.In addition, in the largest face of solar chip or LED chip, also equally the structures such as electrode can be set.Should be noted that, general chip is flaky texture, and its largest face has two sides relative to each other conventionally, in this, only indicates for purpose of brevity one of them largest face for drawing.
In this specific embodiment, largest face 10 edges of chip 1 are connected with side surface 12, and side surface 12 is according to the shape of chip 1 and quantitatively different.Due to the slice-shaped that is shaped as of chip 1, so the area of side surface 12 is less compared to largest face 10, and generally speaking, on side surface 12, space can not arrange above-mentioned functional structure.10 angles with 90 ° of side surface 12 and largest face, however the present invention is not limited to 90 ° of angles of this specific embodiment, and can be between 0 ° to 180 °.In addition,, in another specific embodiment, the junction of side surface and largest face can have leads fillet.Above-mentioned various chip form is determined according to user's demand, and the present invention is not limited this.
On chip 10, further have nanostructured layers 14, it is formed on side surface 12.In nanostructured layers 14, comprise a plurality of nanostructures, for example nanoneedle or nano-pillar.Please with reference to Fig. 2 and Fig. 3, the actual look figure of the nanostructured layers 14 that Fig. 2 is Fig. 1, the generalized section of the nanostructured layers 14 that Fig. 3 is Fig. 2.The nanostructured layers that note that Fig. 2 is to obtain via the side surface of etching silicon chip in practice.As shown in FIG. 2 and 3, nanostructured layers 14 comprises from the outward extending nanoneedle 140 of side surface 12 and nano-pillar 142.
No matter by which kind of process, nanoneedle 140 all can form the defect on material while forming on side surface 12 with nano-pillar 142 on side surface 12, for example, in Fig. 3, nanoneedle 140 and nano-pillar 142 can connect side surface 12 parts at it and form fault in material.In addition, each nanostructure in nanostructured layers 14 may be connected to each other, and at the place of being connected to each other, can produce fault in material equally.What is more, nanostructure itself has fault in material.Generally speaking, easily there is the concentrated phenomenon of stress in fault in material place, and in other words, when chip 1 is subject to tension force, nanoneedle 140, nano-pillar 142, both and side surface 12 junctions or each nanostructure place of being connected to each other may have the concentrated phenomenon of stress.
Above-mentioned single nanoneedle 140 is minimum with the size of nano-pillar 142, and, the nanoneedle 140 that includes a myriad of in nanostructured layers 14 is dispersed throughout wherein with nano-pillar 142, therefore the part on nanostructured layers 14 covering side surfaces 12 can be treated as by fault in material point, forms.Therefore, nanostructured layers 14 by the suffered stress of chip 1 concentrate on respectively all nanoneedle 140 with nano-pillar 142 on formed fault in material point.With regard to result, stress is to be scattered in the part being covered by nanostructured layers 14 on whole side surface 12 on the contrary, and in other words, this is the stress dispersion phenomenon of a face, but not the stress concentration phenomenon of point or line.
When chip is subject to tension force, the stress producing is dispersed on the nanostructured layers that is covered in side surface, and the fault in material of script on chip, for example, the formed defect of functional structure in largest face or chip is carried out to other and process the defect cause, can avoid violent stress concentration phenomenon to cause slight crack even to break.Therefore, the nanostructured layers in this specific embodiment with stress dispersion effect can help chip opposing tension force, in other words, can promote the intensity of the resistance to fracture of chip own.
In this specific embodiment, nanostructure is nanoneedle and nano-pillar, and in practice, above-mentioned nanoneedle and nano-pillar can be formed on the side surface of chip by electrochemical etching process.For example, nanostructured layers 14 in Fig. 2 can be surpassed and form for 40 minutes side surface 12 etchings of chip 1 by electrochemical etching process, the nanoneedle forming after etching or nano-pillar, distance between two adjacent tops is between 10 nanometer to 1000 nanometers, and its degree of depth is between 0.1 micron to 100 microns.Because the yardstick of nanoneedle or nano-pillar is minimum, in chip manufacture process, even if nanostructured layers is subject to lateral forces (that is, be parallel to the power of side surface), the nanostructure in structure sheaf also can not scraped.On the other hand, the minimum yardstick of nanostructure can not affect the material behavior of chip on macroscopic, only strengthens its resistance to rupture.
Please refer to Fig. 4 A and Fig. 4 B, the schematic diagram that the chip 1 that Fig. 4 A is Fig. 1 carries out three-point bending resistance test, Fig. 4 B shows maximum load that chip 1 can bear and the chart of etching period.Note that chip 1 is, by chemical etching mode, side surface 12 is carried out to the etching of different time in this, then tests by three-point bending resistance method of testing the characteristic curve obtaining as shown in Figure 4 B.The technique of above-mentioned chemical etching mode for example, the side surface of chip 1 can be dipped in the etching solution that the concentration ratio hydrofluoric acid of 250: 1 (HF) and silver nitrate (AgNO3) mix, carry out respectively the chip side surface etching of 20 minutes, 40 minutes and 60 minutes.As shown in Figure 4 B, the longitudinal axis in chart is the maximum load that chip 1 can bear, that is, when crooked chip 1 makes it produce slight crack or break, the tension force that chip 1 bears; The longitudinal axis is for forming the etching period of 14 processes of nanostructured layers.In addition the maximum load that, reference line L can bear for do not form the chip of nanostructured layers on side surface.
By Fig. 4 B, can be found out, through etching in 20 minutes, make the chip 1 of nanostructured layers 14, the maximum load that can bear is approximately 3N, is greater than and does not form the maximum load 2N that the chip of nanostructured layers can bear.In addition,, when etching period increases, the maximum load that chip 1 can bear also increases thereupon.Hence one can see that, forms the intensity that nanostructured layers really can help chip resistance to fracture and increase chip on the side surface of chip.
On the other hand, nanostructured layers 14 makes chip 1 can bear larger load and is unlikely to break, and represents that chip 1 can have higher bendable curvature.When chip can bear larger load and have higher bendable curvature, except more difficult because being subject to tension force breaks in general processing technology, originally the technique that cannot carry out because of the tensile property of chip material also can be carried out under the situation of not changing chip material, therefore, the usefulness of chip itself and applicable field thereof have further been promoted.
As above-mentioned, nanostructured layers 14 is the resistance to ruptures with the form strengthening chip of stress dispersion face, therefore applicable to various chips, as amorphous, monocrystalline or polycrystalline chip, in practice, chip can be by glass (SiO
2), silicon (Si), germanium (Ge), carbon (C), aluminium (Al), gallium nitride (GaN), GaAs (GaAs), gallium phosphide (GaP), aluminium nitride (AlN), sapphire (sapphire), spinelle (spinnel), alundum (Al2O3) (Al
2o
3), carborundum (SiC), zinc oxide (ZnO), magnesium oxide (MgO), titanium dioxide lithium aluminium (LiAlO
2), titanium dioxide lithium gallium (LiGaO
2) or four magnesium oxide two aluminium (MgAl
2o
4) at least one is made, but not as limit.
In above-mentioned specific embodiment, nanostructured layers 14 is formed thereon by etched side surface 12, yet the present invention is not limited this.For example, nanostructured layers also can be by being formed on side surface as modes such as extension, plated films.Different according to the method that forms nanostructured layers, the nanostructure comprising in nanostructured layers is difference to some extent also, but not only limit to the kenel of above-mentioned nanoneedle or nano-pillar.
On the other hand, the material of nanostructured layers can be identical with chip material, also can be different.For example, if form nanostructured layers with etching mode, can directly etching chip side surface and obtain the nanostructured layers with the identical material of chip, also can on side surface, first form heterogeneous thin layer, and thin layer etching is obtained to the nanostructured layers different with chip material.In addition, with extension or plated film mode, form the method for nanostructured layers, can directly select the material of or different material identical with chip to carry out technique.
Refer to Fig. 5, Fig. 5 is according to the generalized section of the chip 2 of another specific embodiment of the present invention.As shown in Figure 5, in edge one scope that the largest face 20 of chip 2 is connected with side surface 22, can form nanostructured layers 24 equally.The nanostructured layers 24 that is formed at largest face 20 edges also can help chip 2 opposing tension force.In practice, be arranged in largest face edge scope nanostructured layers can with side surface on nanostructured layers in same technique, form in the lump, for example, when using engraving method etched side surface, etching solution carries out etching and on both, forms nanostructured layers simultaneously the edge of largest face simultaneously.Generally speaking, the nanostructured layers forming in largest face, its scope is extended 1 centimeter from largest face edge towards center, however the present invention is not limited this.In practice, according to the mode of chip material and formation nanostructured layers, nanostructured layers can have different scopes in largest face, its functional structure on face that do not have the greatest impact.
Above-mentioned specific embodiment is to form nanostructured layers on whole side surface, and in another specific embodiment, this nanostructured layers can cover part side surface, equally also has the effect of dispersive stress.Further, nanostructured layers also can be formed at respectively on all side surfaces.In theory, the scope that nanostructured layers covers is wider, the resistance to rupture that its tool is higher.Please refer to Fig. 6, Fig. 6 is according to the schematic diagram of the chip 3 of another specific embodiment of the present invention.As shown in Figure 6, chip 3 be shaped as rectangle sheet, 30 of largest face are rectangle, and 4 edges of largest face 30 connect respectively 4 side surfaces 32.Nanostructured layers 34 is formed on each side surface 32 simultaneously, the intensity with the stress on this dispersed chip with lifting chip.
On the other hand, according to the shape of chip, nanostructured layers can be formed on difform side surface.Please refer to Fig. 7, Fig. 7 is according to the schematic diagram of the chip 4 of another specific embodiment of the present invention.As shown in Figure 7, chip 4 is a thin rounded flakes body, and being shaped as of its largest face 40 is round, and 42 of side surfaces that connect largest face 40 edges are annular surface, but not the rectangular surfaces of a upper specific embodiment.Nanostructured layers 44 is formed on the side surface 42 of ring-type, to increase the resistance to rupture of the chip 4 of thin rounded flakes body.
In practice, the shape of chip is not limited to the described rectangle sheet of above-mentioned each specific embodiment or thin rounded flakes body, and may have various shape.For example, except rectangle or circle, the largest face of chip can be rhombus, ellipse or square, depending on user's demand.Nanostructured layers can be formed at the side surface of the chip of above-mentioned various shapes, helps various chip opposings break and improve Die strength.
In sum, chip of the present invention has largest face to connect the side surface at largest face edge, and forms the nanostructured layers that dispersibles stress on side surface.The chip compared to traditional side surface without nanostructured layers, chip of the present invention has stronger resistance to rupture, that is the intensity of chip is more traditional higher.Except the processing technology chips general more difficult because being subject to tension force breaks, chip itself can resistance to tool the processing technology of high-tension more, and the usefulness field applicable with it of further having improved chip.
By the above detailed description of preferred embodiments, hope can be known description feature of the present invention and spirit more, and not with above-mentioned disclosed preferred embodiment, category of the present invention is limited.On the contrary, its objective is that hope can contain in the category of the scope of the claims of being arranged in of various changes and tool equality institute of the present invention wish application.Therefore, the category of the scope of the claims that the present invention applies for should be done the broadest explanation according to above-mentioned explanation, to cause it to contain the arrangement of all possible change and tool equality.
Claims (20)
1. a chip, comprises:
A plurality of surfaces, described a plurality of surfaces comprise:
One largest face, has area maximum in described a plurality of surface; And
One side surface, connects an edge of this largest face; And
One nanostructured layers, it is at least formed on this side surface, in order to disperse the stress of this chip.
2. chip as claimed in claim 1, wherein the angle of this side surface and this largest face is between 0 ° to 180 °.
3. chip as claimed in claim 2, wherein the angle of this side surface and this largest face is between 45 ° to 90 °.
4. chip as claimed in claim 1, is wherein by one, to lead fillet to be connected to each other between this side surface and this largest face.
5. chip as claimed in claim 1, wherein this side surface is a rectangular surfaces or an annular surface.
6. chip as claimed in claim 1, wherein this largest face of this chip is shaped as rectangle, rhombus, circle, ellipse or square.
7. chip as claimed in claim 1, wherein this nanostructured layers is also formed in the scope on this edge of this largest face, and this scope is extended 1 centimeter in the center towards this largest face from this edge.
8. chip as claimed in claim 1, wherein this nanostructured layers comprises a plurality of nanostructures.
9. chip as claimed in claim 8, the shape of wherein said a plurality of nanostructures comprise in nano-pillar and nanoneedle at least one of them.
10. chip as claimed in claim 9, wherein the spacing on two adjacent these nanostructure tops is between 10 nanometer to 1000 nanometers.
11. chips as claimed in claim 9, the degree of depth of wherein said a plurality of nanostructures is between 0.1 micron to 100 microns.
12. chips as claimed in claim 8, wherein said a plurality of nanostructures are that a kind of method wherein by etching, extension and film plating process is formed at this side surface.
13. chips as claimed in claim 1, wherein this chip is one of them of an amorphous chip, a single crystalline chip and a polycrystalline chip.
14. chips as claimed in claim 13, wherein this single crystalline chip is a silicon single crystal wafer.
15. chips as claimed in claim 13, wherein this chip is that at least one in the group being comprised of glass, silicon, germanium, carbon, aluminium, gallium nitride, GaAs, gallium phosphide, aluminium nitride, alundum (Al2O3), carborundum, zinc oxide, magnesium oxide, titanium dioxide lithium aluminium, titanium dioxide lithium gallium and four magnesium oxide two aluminium is made.
16. chips as claimed in claim 1, wherein this chip is a P type semiconductor, and in this largest face, forms a n type semiconductor layer.
17. chips as claimed in claim 1, wherein this chip is a N type semiconductor, and in this largest face, forms a p type semiconductor layer.
18. chips as claimed in claim 1, wherein the material of this nanostructured layers is identical with the material of this chip.
19. chips as claimed in claim 1, wherein the material of this nanostructured layers and the material of this chip are different.
20. chips as claimed in claim 1, wherein this chip is semiconductor chip.
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| CN201110294373.0A CN103011066B (en) | 2011-09-21 | 2011-09-21 | Chip |
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|---|---|---|---|
| CN201110294373.0A CN103011066B (en) | 2011-09-21 | 2011-09-21 | Chip |
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| Publication Number | Publication Date |
|---|---|
| CN103011066A CN103011066A (en) | 2013-04-03 |
| CN103011066B true CN103011066B (en) | 2014-03-19 |
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Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105845757A (en) * | 2015-01-14 | 2016-08-10 | 叶哲良 | Bendable solar chip capable of optimizing thickness and conversion efficiency |
| TWI588085B (en) * | 2015-03-26 | 2017-06-21 | 環球晶圓股份有限公司 | Micro-nano wafer and manufacturing method thereof |
| CN105552187A (en) * | 2015-12-16 | 2016-05-04 | 中国科学院半导体研究所 | GaN thin film prepared by GaN nano-patterned substrate homoepitaxy and method |
| CN106229396A (en) * | 2016-08-29 | 2016-12-14 | 中国科学院半导体研究所 | A kind of group III-nitride bioprobe and preparation method thereof |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1812053A (en) * | 2005-01-07 | 2006-08-02 | 三星康宁株式会社 | Epitaxial growth method |
| JP2007088416A (en) * | 2005-08-22 | 2007-04-05 | Tokyo Electron Ltd | Conveyance tray for semiconductor wafer and semiconductor wafer conveyance system |
| CN101225544A (en) * | 2006-11-22 | 2008-07-23 | 硅电子股份公司 | Epitaxially coated semiconductor wafer and device and method for producing an epitaxially coated semiconductor wafer |
| CN101593675A (en) * | 2008-05-28 | 2009-12-02 | 中国科学院半导体研究所 | A method for growing epitaxial wafers with nanofold structure active region |
| CN101916735A (en) * | 2010-07-19 | 2010-12-15 | 江阴长电先进封装有限公司 | Manufacturing method of flip chip encapsulation structure taking carbon nano tube cluster as salient point of chip |
-
2011
- 2011-09-21 CN CN201110294373.0A patent/CN103011066B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1812053A (en) * | 2005-01-07 | 2006-08-02 | 三星康宁株式会社 | Epitaxial growth method |
| JP2007088416A (en) * | 2005-08-22 | 2007-04-05 | Tokyo Electron Ltd | Conveyance tray for semiconductor wafer and semiconductor wafer conveyance system |
| CN101225544A (en) * | 2006-11-22 | 2008-07-23 | 硅电子股份公司 | Epitaxially coated semiconductor wafer and device and method for producing an epitaxially coated semiconductor wafer |
| CN101593675A (en) * | 2008-05-28 | 2009-12-02 | 中国科学院半导体研究所 | A method for growing epitaxial wafers with nanofold structure active region |
| CN101916735A (en) * | 2010-07-19 | 2010-12-15 | 江阴长电先进封装有限公司 | Manufacturing method of flip chip encapsulation structure taking carbon nano tube cluster as salient point of chip |
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